DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a Non-Final office action based on application 18/752,950 filed June 6, 2024. Claims 1-20 are current pending and have been considered below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (Pre-Grant Publication 2023/0171954) in view of Son (Pre-Grant Publication 2022/0139836) and Ramaswamy (US Patent 10,020,360).
Regarding claim 1 & 7, Kim discloses an integrated circuit device comprising:
a substrate (Fig. 7, 101) comprising a cell array area (CAR) and a peripheral area (PR);
a plurality of lower electrodes (140) in the cell array area;
at least one supporter layer (145) contacting the plurality of lower electrodes and extending in a first direction parallel to a top surface of the substrate;
a dielectric film (150) covering the plurality of lower electrodes and the at least one supporter layer;
an upper electrode (160) covering the dielectric film;
a plate layer (163) surrounding a top surface and a side surface of the upper electrode;
an interlayer insulating layer (180) covering a top surface of the oxide layer and the side surface of the upper electrode; and
a peripheral contact plug (194) passing through the interlayer insulating layer and in the peripheral area of the substrate,
wherein the upper electrode comprises at least one protruding areas (163a-163c) protruding in a lateral direction,
the lateral direction is a horizontal direction from the cell array area toward the peripheral area (Fig. 7).
Kim does not disclose an oxide layer contacting a top surface of the plate layer and extending in a second direction parallel to the substrate or the lateral direction is a horizontal direction from the cell array area toward the peripheral area, the integrated circuit device defines an air gap conformally surrounding the at least one protruding area of the upper electrode in the lateral direction. However Son (Pre-Grant Publication 2022/0139836) discloses an integrated circuit device comprising:
A capacitor structure (Fig. 12a-12b) including a lower electrode (210), a dielectric layer (220) and an upper electrode (232/234), wherein an oxide etch stop layer (240p; Paragraph [0089])) is formed in contact with a top surface of the plate layer (234p) of the upper electrode and extending in a second direction parallel to a substrate (101).
It would have been obvious to those having ordinary skill in the art at the time to form the oxide etch stop layer on the plate layer of the upper electrode because it will allow for subsequent etching processes to be accurately controlled and prevent over-etching/damage to certain layers below the etch stop layer.
Ramaswamy discloses an integrated device comprising:
A plurality of capacitors (30/32) wherein an air gaps/voids (Fig. 1, 56/58) is formed around the capacitor and between a side surface of the capacitor to space the capacitor from a side surface of an insulating layer (50).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the air gap adjacent a side surface of the capacitor because the air gap will serve to alter/influence the electrical properties/performance of the capacitors (Col. 7, Lines 62- Col. 8, Lines 1-18).
Regarding claim 2, Kim further discloses:
The upper electrode comprises silicon germanium layer (162; Paragraph [0047]).
Kim does not disclose the plate layer comprises tungsten. However Son further discloses:
The upper electrode can include plate layer (234) including main electrode layer (Fig. 22d, 236) that can comprises tungsten (W) (Paragraph [0106]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the plate layer to comprises a metal such a tungsten because tungsten metal material will serve to protect underlying layers during subsequent processing and provide improved adhesion to insulating material formed on the plate layer thereby improving device reliability (Paragraph [0115]).
Regarding claim 3, Kim, Son, and Ramaswamy disclose all of the limitations of claim 1 (addressed above). Kim does not disclose the oxide layer has a thickness of 10-60 angstroms. However Son further discloses:
The oxide etch stop layer can have a thickness of about 300-1500 angstroms (Paragraph [0107]).
Although Son does not disclose the oxide has a thickness of 10-60 angstroms it would have been obvious to those having ordinary skill in the art to try to form the oxide layer having a thickness of 10-60 angstroms since it would reduce the height/size of the memory device and it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller 105 USPQ 233 MPEP 2144.05 IIA.
Regarding claim 4, Kim further discloses:
an upper electrode contact plug (191) passing through the oxide layer and a part of the upper electrode, and the upper electrode contact plug electrically connected to the upper electrode, wherein a bottom surface of the upper electrode contact plug contacts the plate layer (Paragraph [0054]).
Regarding claim 5, Kim further discloses:
an upper electrode contact plug (191) passing through the oxide layer and a part of the upper electrode, and the upper electrode contact plug electrically connected to the upper electrode, wherein the upper electrode contact plug passes through the plate layer (Paragraph [0054]).
Regarding claim 6, Kim further discloses:
the interlayer insulating layer comprises tetraethyl orthosilicate (TEOS) (Paragraph [0052]).
Claim(s) 10, 12-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (Pre-Grant Publication 2023/0171954) in view of S Ramaswamy (US Patent 10,020,360).
Regarding claim 10 & 12, Kim discloses an integrated circuit comprising:
a substrate (Fig. 7, 101) comprising a cell array area (CAR) and a peripheral area (PR);
a capacitor structure (CS) comprising a plurality of lower electrodes (140) in the cell array area, a dielectric film (150) on the plurality of lower electrodes, and an upper electrode(160) covering the dielectric film;
a plate layer (163) covering a side surface and a top surface of the capacitor structure;
and an interlayer insulating layer (180) covering a top surface and a side surface of the plate layer.
Kim does not disclose the integrated circuit device defines an air gap located between the side surface of the plate layer and the interlayer insulating layer. Ramaswamy discloses an integrated device comprising:
A plurality of capacitors (30/32) wherein an air gaps/voids (Fig. 1, 56/58) is formed around the capacitor and between a side surface of the capacitor to space the capacitor from a side surface of an insulating layer (50).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the air gap adjacent a side surface of the capacitor because the air gap will serve to alter/influence the electrical properties/performance of the capacitors (Col. 7, Lines 62- Col. 8, Lines 1-18).
Regarding claim 13, Kim further discloses:
an upper electrode contact plug (191) passing through a part of the upper electrode to be electrically connected to the upper electrode; and a peripheral contact plug (194) passing through the interlayer insulating layer located in the peripheral area of the substrate.
Regarding claim 14 & 15, Kim further discloses:
wherein a bottom surface of the upper electrode contact plug passes through a part of the plate layer (Paragraph [0054]) or
a bottom surface of the upper electrode contact plug is at a level lower than a bottom surface of the plate layer (Paragraph [0054]).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (Pre-Grant Publication 2023/0171954) in view of Son (Pre-Grant Publication 2022/0139836) and Ramaswamy (US Patent 10,020,360).
Regarding claim 11, Kim and Ramaswamy disclose all of the limitations of claim 10 (addressed above). Kim further discloses:
The upper electrode comprises silicon germanium layer (162; Paragraph [0047]).
the interlayer insulating layer comprises tetraethyl orthosilicate (TEOS) (Paragraph [0052]).
Kim does not disclose the plate layer comprises tungsten. However Son further discloses:
The upper electrode can include plate layer (234) including main electrode layer (Fig. 22d, 236) that can comprises tungsten (W) (Paragraph [0106]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the plate layer to comprises a metal such a tungsten because tungsten metal material will serve to protect underlying layers during subsequent processing and provide improved adhesion to insulating material formed on the plate layer thereby improving device reliability (Paragraph [0115]).
Claim(s) 17 & 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (Pre-Grant Publication 2023/0171954) in view of Son (Pre-Grant Publication 2022/0139836), Ramaswamy (US Patent 10,020,360), and Aoki (Pre-Grant Publication 2011/0049600).
Regarding claim 17, Kim discloses an integrated circuit comprising:
a substrate (Fig. 7, 101) comprising a memory cell area (CAR) and a peripheral circuit area (PR) around the memory cell area;
a plurality of cell transistors in the memory cell area (Paragraph [0029]);
a peripheral circuit transistor in the peripheral circuit area (Paragraph[0040]);
a capacitor structure (CS) comprising lower electrodes (140) on the plurality of cell transistors, a dielectric film (150) located on surfaces of the lower electrodes, and an upper electrode (160) located on the dielectric film;
a plate structure (163) covering the capacitor structure;
a first interlayer insulating film (180) between the peripheral circuit transistor in the peripheral circuit area and the plate structure (163) in the memory cell area.
an upper electrode contact plug (191) passing through a part of the upper electrode in the memory cell area and electrically connected to the upper electrode (Paragraph [0054]); and
a peripheral contact plug (194) passing through the first interlayer insulating film in the peripheral circuit area.
Kim does not disclose an oxide layer contacting a top surface of the plate layer and extending in a second direction parallel to the substrate, the integrated circuit device defines an air gap conformally surrounding the at least one protruding area of the upper electrode in the lateral direction, or a second interlayer insulating film on the oxide layer and covering the oxide layer and a peripheral contact plug sequentially passing through the second interlayer insulating film, the oxide layer, and the first interlayer insulating film in the peripheral circuit area. However Son (Pre-Grant Publication 2022/0139836) discloses an integrated circuit device comprising:
A capacitor structure (Fig. 12a-12b) including a lower electrode (210), a dielectric layer (220) and an upper electrode (232/234), wherein an oxide etch stop layer (240p; Paragraph [0089])) is formed in contact with a top surface of the plate layer (234p) of the upper electrode and extending in a second direction parallel to a substrate (101).
It would have been obvious to those having ordinary skill in the art at the time to form the oxide etch stop layer on the plate layer of the upper electrode because it will allow for subsequent etching processes to be accurately controlled and prevent over-etching/damage to certain layers below the etch stop layer.
Ramaswamy discloses an integrated device comprising:
A plurality of capacitors (30/32) wherein an air gaps/voids (Fig. 1, 56/58) is formed around the capacitor and between a side surface of the capacitor to space the capacitor from a side surface of an insulating layer (50).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the air gap adjacent a side surface of the capacitor because the air gap will serve to alter/influence the electrical properties/performance of the capacitors (Col. 7, Lines 62- Col. 8, Lines 1-18).
Aoki discloses an integrated circuit comprising:
A capacitor (Fig. 2) formed in a memory region including a lower electrode layer (216), a dielectric film (217) and a upper electrode (218) wherein a first insulating layer (219), an oxide/insulating layer (222) and a second insulating layer (223) are formed over the capacitor in the memory and in peripheral/logic region.
A peripheral contact plug (220a/b & 226a/b) is formed passing through the first insulating layer (219), the oxide/insulating layer (222) and the second insulating layer (223).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the first insulating layer, oxide layer, and second insulating layer stacked together because it will serve to provide insolation between the conductive interconnect/plug formed adjacent to each other and prevent undesired coupling.
Regarding claim 18, Kim further discloses:
The upper electrode comprises silicon germanium layer (162; Paragraph [0047]).
the interlayer insulating layer comprises tetraethyl orthosilicate (TEOS) (Paragraph [0052]).
Kim does not disclose the plate layer comprises tungsten. However Son further discloses:
The upper electrode can include plate layer (234) including main electrode layer (Fig. 22d, 236) that can comprises tungsten (W) (Paragraph [0106]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the plate layer to comprises a metal such a tungsten because tungsten metal material will serve to protect underlying layers during subsequent processing and provide improved adhesion to insulating material formed on the plate layer thereby improving device reliability (Paragraph [0115]).
Allowable Subject Matter
Claims 8-9, 16 & 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claim 8 is considered allowable because none of the prior art either alone or combination discloses a thickness of the air gap in the lateral direction is 300 angstroms to 500 angstroms.
Claim 9 is considered allowable because none of the prior art either alone or combination discloses the peripheral contact plug is physically spaced apart from the air gap.
Claim 16 is considered allowable because none of the prior art either alone or combination discloses the peripheral contact plug is physically spaced apart from the air gap.
Claim 19 is considered allowable because none of the prior art either alone or combination discloses the oxide layer has a thickness of 10 angstroms to 60 angstroms, and the air gap has a thickness of 300 angstroms to 500 angstroms.
Claim 20 is considered allowable because none of the prior art either alone or combination discloses a bottom surface of the oxide layer is at a same level as the top surface of the plate structure and an uppermost end of the air gap.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yang (Pre-Grant Publication 2025/0365931) discloses a three dimensional semiconductor device comprising a capacitor structure including a supporting structures adjacent to lower electrode and a upper electrode over a top and side surface of the capacitor structure.
Lee (US Patent 12,363,890) discloses a semiconductor device comprising: A upper electrode of a capacitor structure having curved sidewall surface contacting a insulating layer.
Tung (Pre-Grant Publication 2023/0320073) disclose a semiconductor structure comprising lower electrode adjacent supporting structures wherein the lower electrode having a slop profile on a top portion.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON C FOX whose telephone number is (571)270-5016. The examiner can normally be reached M-F 9:00AM-6:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BRANDON C FOX/Examiner, Art Unit 2818
/DAVID VU/Primary Examiner, Art Unit 2818
Prosecution Insights