Prosecution Insights
Last updated: July 17, 2026
Application No. 18/752,968

WAFER CENTER MONITOR

Non-Final OA §102§103
Filed
Jun 25, 2024
Priority
Jun 07, 2024 — CN 202410741005.3
Examiner
HARRISTON, WILLIAM A
Art Unit
Tech Center
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
953 granted / 1066 resolved
+29.4% vs TC avg
Moderate +8% lift
Without
With
+8.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
16 currently pending
Career history
1089
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
65.6%
+25.6% vs TC avg
§102
11.5%
-28.5% vs TC avg
§112
1.0%
-39.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1066 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Drawings The drawings filed on 06/25/2024 are acceptable. Specification The abstract of the disclosure and the specification filed on 06/25/2024 are acceptable. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-3, and 6 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Huynh (US 5,822,213). Regarding claim 1, Huynh (US 5,822,213) discloses: A semiconductor processing tool, comprising: a wafer stage (spindle 108, column 4 line 65); and an imaging system (laser diode 102, CCD array 104 and microcontroller 110 taken together, column 5, lines 20-44) configured to determine a spatial relationship between a processed area of a semiconductor substrate (106) on the wafer stage (108) and a plurality of fiducial markers (60, 62, column 5 lines 11-13) placed at a corresponding plurality of locations along a perimeter of the semiconductor substrate. Column 4 line 63 – column 5 line 20 teaches the imaging system calculates the wafers center (the claimed processed area ) and orientation by monitoring the wafer center and the fiducial markers 60, 62. Regarding claim 2, Hyunh further discloses: wherein the wafer stage (108) is a wafer stage of a plasma processing tool (column 1 lines 18-22). Regarding claim 3, Hyunh further discloses: wherein the wafer stage (108) is a wafer stage of an optical inspection tool (column 5 lines 20-44). Regarding claim 6, Huynh further discloses: wherein the plurality of fiducial markers (60, 62) are spaced from an edge of the semiconductor substrate by a same distance (figure 2). Claim(s) 8, 9, 12, 18, 19, 22 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Taravade (US 6,120,607). Regarding claim 8, Taravade (US 6,120,607) discloses: A method of manufacturing an integrated circuit (IC), comprising: forming a plurality of fiducial markers (110, 115, column 4 lines 4-10) over a semiconductor substrate (100, column 4 line 1), the fiducial markers (110, 115) placed at a perimeter of the semiconductor substrate (100) at a corresponding plurality of locations; and forming a plurality of instances of the IC on or over the semiconductor substrate (100, column 3 lines 65-67). Regarding claim 9, Taravade further discloses: wherein the fiducial markers (110, 115) are instances of a same marker design (column 4 lines 8-11). Regarding claim 12, Taravade further discloses: wherein the fiducial markers (110, 115) are spaced from an edge of the semiconductor substrate by a same distance (column 4 lines 4-8. Regarding claim 18, Taravade further discloses: A semiconductor wafer (100), comprising: a semiconductor substrate (100); a plurality of instances of the IC on or over the semiconductor substrate (column 3 lines 65-67); and a plurality of fiducial markers (110, 115) over the semiconductor substrate, the fiducial markers placed at a perimeter of the semiconductor substrate at a corresponding plurality of locations (column 4 lines 4-10). Regarding claim 19, Taravade further discloses: wherein the fiducial markers (110, 115) are instances of a same marker design (column 4 lines 4-10). Regarding claim 22, Taravade further discloses: wherein the fiducial markers (110, 115) are spaced from an edge of the semiconductor substrate by a same distance (column 4 lines 4-8). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 4, 5 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hyunh. Regarding claim 4, Hyunh does not disclosed the claimed limitations. However, Applicant is advised that the limitation "wherein the imaging system is configured to determine a distance of a perimeter of the processed area from a perimeter of the semiconductor substrate at each of the plurality of locations ", is an intended use limitation rather than a required structural limitation further limiting the scope of the device claim. The applied prior art can be so modified or used and therefore renders unpatentable such claims. See, for example, M.P.E.P. § 2111.04, and precedents cited therein. Therefore the claimed limitations are considered met Regarding claim 5, Hyunh does not disclose the claimed limitations. Applicant is advised that the limitation "wherein the imaging system is configured to determine an offset of a center of the processed area from a center of the semiconductor substrate", is an intended use limitation rather than a required structural limitation further limiting the scope of the device claim. The applied prior art can be so modified or used and therefore renders unpatentable such claims. See, for example, M.P.E.P. § 2111.04, and precedents cited therein. Therefore the claimed limitations are considered met. Regarding claim 7, Hyunh does not disclose “wherein the fiducial markers each include a laser scribe dot matrix having a plurality of dots arranged in rows and columns”. However, a change in size or shape or both is an unpatentable modification when it results in optimum conditions that differ from the prior art in degree but not in kind. In Re Rose, 220 F.2d 459, 105 USPQ 237, In reDailey, 357 F.2d 669, 149 USPQ 47). In the instant case the prior art device would not perform differently if modified to the claimed shape or size. Therefore the claimed limitations are considered met. Claim(s) 10-11, 17, 20, 21, 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Taravade. Regarding claim 10, Taravade does not disclose “wherein the fiducial markers include an alphanumeric character”. However, a change in size or shape or both is an unpatentable modification when it results in optimum conditions that differ from the prior art in degree but not in kind. In Re Rose, 220 F.2d 459, 105 USPQ 237, In reDailey, 357 F.2d 669, 149 USPQ 47). In the instant case the prior art device would not perform differently if modified to the claimed shape or size. Therefore the claimed limitations are considered met. Regarding claim 11, Taravade does not disclose wherein the fiducial markers have a long axis oriented along a radial of the semiconductor substrate. However, a change in size or shape or both is an unpatentable modification when it results in optimum conditions that differ from the prior art in degree but not in kind. In Re Rose, 220 F.2d 459, 105 USPQ 237, In reDailey, 357 F.2d 669, 149 USPQ 47). In the instant case the prior art device would not perform differently if modified to the claimed shape or size. Therefore the claimed limitations are considered met. Regarding claim 17, Taravade does not disclose “wherein the fiducial markers are located on axes of a rectilinear coordinate space that are rotated with respect to a crystal orientation of the semiconductor substrate”. However, a change in size or shape or both is an unpatentable modification when it results in optimum conditions that differ from the prior art in degree but not in kind. In Re Rose, 220 F.2d 459, 105 USPQ 237, In reDailey, 357 F.2d 669, 149 USPQ 47). In the instant case the prior art device would not perform differently if modified to the claimed shape or size. Therefore the claimed limitations are considered met. Regarding claim 20, Taravade does not disclose “wherein the fiducial markers include an alphanumeric character”. However, a change in size or shape or both is an unpatentable modification when it results in optimum conditions that differ from the prior art in degree but not in kind. In Re Rose, 220 F.2d 459, 105 USPQ 237, In reDailey, 357 F.2d 669, 149 USPQ 47). In the instant case the prior art device would not perform differently if modified to the claimed shape or size. Therefore the claimed limitations are considered met. Regarding claim 21, Taravade does not disclose wherein the fiducial markers have a long axis oriented along a radial of the semiconductor substrate. However, a change in size or shape or both is an unpatentable modification when it results in optimum conditions that differ from the prior art in degree but not in kind. In Re Rose, 220 F.2d 459, 105 USPQ 237, In reDailey, 357 F.2d 669, 149 USPQ 47). In the instant case the prior art device would not perform differently if modified to the claimed shape or size. Therefore the claimed limitations are considered met. Regarding claim 23, Taravade does not disclose “wherein the fiducial markers are located on axes of a rectilinear coordinate space that are rotated with respect to a crystal orientation of the semiconductor substrate”. However, a change in size or shape or both is an unpatentable modification when it results in optimum conditions that differ from the prior art in degree but not in kind. In Re Rose, 220 F.2d 459, 105 USPQ 237, In reDailey, 357 F.2d 669, 149 USPQ 47). In the instant case the prior art device would not perform differently if modified to the claimed shape or size. Therefore the claimed limitations are considered met. Allowable Subject Matter Claims 13-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 13, the prior art does not disclose “imaging a processed area perimeter in relation to the plurality of fiducial markers” in combination with the remaining claimed features. Regarding claim 14, the p[prior art does not disclose “placing an edge cover ring over the fiducial markers and performing a plasma process on the semiconductor substrate”. In combination with the remaining claimed features. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM A HARRISTON whose telephone number is (571)270-3897. The examiner can normally be reached Mon-Fri, 9AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WILLIAM A HARRISTON/Primary Examiner, Art Unit 2899
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Prosecution Timeline

Jun 25, 2024
Application Filed
Jun 30, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
98%
With Interview (+8.2%)
2y 2m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1066 resolved cases by this examiner. Grant probability derived from career allowance rate.

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