DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities: line 11, before “wherein the first via has a shape” is blank which appears to be a typo.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6, 13-14, and 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, lines 12-13 recites “wherein the first via has a shape that tapers with a narrowing width from an end at the base chip to an end away from the base chip”. Line 2 of this claim recites “a base chip including a first via”. Since the first via is part of the base chip, it is not clear how the first via can be away from the base chip. An object cannot be away from itself. This issue renders the claim indefinite.
Claim 13, line 1 recites “wherein the second via has a first width”. It is not clear, from this limitation, whether or not this first width is the same as the first width of claim 11, from which this claim depends, or is intended to be a new width. Line 3 recites “wherein the second width is larger than the first width”. No second width has been claimed in this claim, or in any claim from which it depends. This issue renders the claim indefinite.
Claim 16, line 26 recites “the second thickness ranges from 0 microns to about 10 microns”. If the second thickness were 0 microns, then the second semiconductor substrate would not exist. Line 28 recites “is included in an lowermost chip stacks”. It is not clear, from this limitation, whether or not there are supposed to be more than one lowermost chip stack or just one, since stacks is plural and an indicates singularity. It is also unclear how a chip stack could be lowermost, since all of them are on the base chip. These issues render the claim indefinite.
Note that dependent claims necessarily inherit any indefiniteness from the claims on which they depend.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHOI (US 20210143126) in view of LIN (US 11063008).
Regarding claim 1, as best as the examiner is able to ascertain the claimed invention, CHOI discloses a semiconductor package, comprising:
a base chip including a first via (the lower chip 310 including 312 and via 314, see fig 1 and 7, para 37); and
chip stacks (the stacks of 320 and 322 over 310 and under the top chip 320 which are at least indirectly on 310, see fig 1 and 7, para 37 and 41) on the base chip;
wherein the base chip comprises a first protection layer (312 and the protection layer of 310 not pictured, see fig 1 and 7, para 38) provided in an upper portion (the protection layer of 310 is on the upper side of 312 see fig 1 and 7, para 38),
wherein each of the chip stacks comprises a second protection layer (fig 1 and 7, 322, para 40), a plurality of memory chips (the memory chips 320 between 310 and the top 320, see fig 1 and 7, para 40) on the second protection layer, and a second via (the vias 324, see fig 1 and 7, 324, para 40),
wherein the first protection layer is in contact with the second protection layer in the lowermost chip stacks (310, 312 and 322 are in a least indirect contact, see fig 1 and 7),
wherein each second via penetrates the plurality of memory chips in each of the chip stacks (the vias 324 penetrate 320 in CS1 and CS2, see fig 1 and 7, para 40).
CHOI fails to explicitly disclose a device wherein the first via has a shape that tapers with a narrowing width from an end at the base chip to an end away from the base chip and each second via has a shape that tapers with a narrowing width away from the base chip.
LIN teaches a device wherein the first via has a shape that tapers with a narrowing width from an end at the base chip to an end away from the base chip (the via 110 in the bottom substrate 10 tapers in width away from bottom of 104 to its narrowest surface above 100, see fig 2K , para 19) and each second via has a shape that tapers with a narrowing width away from the base chip (the vias 110 in each upper substrate 10 taper in width away from the bottom substrate 10, see fig 2K , para 19.
CHOI and LIN are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHOI with the via shape of LIN because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHOI with the via shape of LIN in order to increase yield and decrease costs (see LIN par a36).
Regarding claim 2, as best as the examiner is able to ascertain the claimed invention, CHOI and LIN disclose the semiconductor package of claim 1.
CHOI fails to explicitly disclose a device, wherein the first protection layer and the second protection layer comprise at least one of silicon oxide (SiO2), silicon carbon nitride (SiCN), or silicon oxycarbide (SiCO).
LIN teaches a device, wherein the first protection layer and the second protection layer comprise at least one of silicon oxide (SiO2), silicon carbon nitride (SiCN), or silicon oxycarbide (SiCO) (the protection layers 116 can be SiO, see fig 2K, para 16).
CHOI and LIN are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHOI with the material of LIN because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHOI with the material of LIN in order to increase yield and decrease costs (see LIN par a36).
Regarding claim 3, as best as the examiner is able to ascertain the claimed invention, CHOI and LIN disclose the semiconductor package of claim 1.
CHOI further discloses a device, wherein the first protection layer further comprises a first connection pad (316 is in 312, see fig 1 and 7, para 38),
wherein the second protection layer further comprises a second connection pad (322 comprises a connection circuit, see fig 1 and 7, para 40),
wherein the first connection pad and the second connection pad are in contact with each other (322 and 316 are at least indirectly connected by 324, see fig 1 and 7),
wherein the first via extends from the first connection pad, and wherein the second via extends from the second connection pad (314 extends from 316 and 324 extends from 322, see fig 1 and 7).
Regarding claim 5, as best as the examiner is able to ascertain the claimed invention, CHOI and LIN disclose the semiconductor package of claim 1.
CHOI further discloses a device, wherein the first and second vias comprise a plurality of first vias and a plurality of second vias, which are arranged along a first direction parallel to a top surface of the base chip (there are pluralities of 314 and 324 arranged in the horizontal directions, see fig 1 and 7).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHOI (US 20210143126) in view of LIN (US 11063008) and further in view of YU (US 20150235949).
Regarding claim 4, as best as the examiner is able to ascertain the claimed invention, CHOI and LIN disclose the semiconductor package of claim 1,
wherein an end portion of the second via is connected to the landing pad (324 is connected to 326 at least indirectly, see fig 1 and 7, para 40).
CHOI fails to explicitly disclose a device wherein an uppermost memory chip further comprises a landing pad provided in an upper portion thereof.
YU teaches a device wherein an uppermost memory chip further comprises a landing pad provided in an upper portion thereof (upper layer 102B has a landing pad 112, see fig 3A, para 25).
CHOI, LIN and YU are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHOI and LIN with the landing pad of YU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHOI and LIN with the landing pad of YU in order to improve heat dissipation (see YU para 21).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHOI (US 20210143126) in view of LIN (US 11063008) and further in view of LEE (US 20220037235).
Regarding claim 6, as best as the examiner is able to ascertain the claimed invention, CHOI and LIN disclose the semiconductor package of claim 5.
CHOI fails to explicitly disclose a device, wherein the plurality of first vias have a shape whose width along the first direction decreases as a distance to a bottom surface of the base chip decreases along a second direction perpendicular to the top surface of the base chip.
LEE teaches a device, wherein the plurality of first vias have a shape whose width along the first direction decreases as a distance to a bottom surface of the base chip decreases along a second direction perpendicular to the top surface of the base chip (the chip 100 can include both upwards and downwards tapering vias, see fig 5, para 50-51).
CHOI, LIN and LEE are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHOI and LIN with the via shape of LEE because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHOI and LIN with the via shape of LEE in order to increase the density of the device (see LEE para 37).
Claim(s) 7-9 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHOI (US 20210143126) in view of YU (US 20150235949).
Regarding claim 7, CHOI discloses a semiconductor package, comprising:
a base chip (the lower chip 310 including 312 and via 314, see fig 1 and 7, para 37); and
chip stacks (the stacks of 320 and 322 over 310 and under the top chip 320 which are at least indirectly on 310, see fig 1 and 7, para 37 and 41) on the base chip,
wherein the base chip comprises a first semiconductor substrate (fig 1 and 7, 310, para 37),
wherein each of the chip stacks comprises a plurality of memory chips (the memory chips 320 between 310 and the top 320, see fig 1 and 7, para 40) and a plurality of first vias (fig 1 and 7, 324, para 40),
wherein each of the memory chips comprises a second semiconductor substrate (fig 1 and 7, 320, para 40) and an interconnection layer (fig 1 and 7, 322, para 40) on the second semiconductor substrate,
wherein the first semiconductor substrate has a first thickness along a first direction perpendicular to a top surface of the base chip (310 can have a thickness of 40-100 microns, see fig 1 and 7, para 36),
wherein the second semiconductor substrate has a second thickness along the first direction (320 can have a thickness of 40-100 microns, see fig 1 and 7, para 40); and
wherein the plurality of the first vias penetrate the plurality of memory chips (324 go through 320, see fig 1 and 7).
CHOI fails to explicitly disclose a device wherein the second thickness is smaller than or equal to 10 % of the first thickness.
YU teaches a device wherein the second thickness is smaller than or equal to 10 % of the first thickness (the bottom tier 102A can have a substrate 104a that is 750 microns, and the upper tier 102B can have a substrate 104B that is 10 microns, which is less than 10% of the first thickness, see fig 1, para 21).
CHOI and YU are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHOI with the thicknesses of YU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHOI with the thicknesses of YU in order to improve heat dissipation (see YU para 21).
Regarding claim 8, CHOI and YU disclose the semiconductor package of claim 7.
CHOI further discloses a device, wherein the interconnection layer further comprises an insulating layer and interconnection patterns in the insulating layer (322 can include a circuit as in 312, see fig 1 and 7, para 40).
CHOI fails to explicitly disclose a device wherein the first via which is included in an uppermost memory chip penetrates a portion of the interconnection layer.
YU teaches a device wherein the first via which is included in an uppermost memory chip penetrates a portion of the interconnection layer (the upper via 114A penetrates the interconnect layer 108B and 104B, see fig 1A, para 22-23).
CHOI and YU are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHOI with the via geometry of YU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHOI with the via geometry of YU in order to improve heat dissipation (see YU para 21).
Regarding claim 9, CHOI and YU disclose the semiconductor package of claim 7.
CHOI further discloses a device, further comprising a second via (fig 1 and 7, 314, para 37) penetrating the base chip,
wherein the plurality of first vias and the second vias are electrically connected to each other (314 and 324 are connected, see fig 1 and 7).
Regarding claim 15, CHOI and YU disclose the semiconductor package of claim 7.
CHOI fails to explicitly disclose a device, wherein the second thickness ranges from 0 microns to about 10 microns.
YU teaches a device wherein, wherein the second thickness ranges from 0 microns to about 10 microns (the upper tier 102B can have a substrate 104B that is 10 microns, see fig 1, para 21).
CHOI and YU are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHOI with the specific lair thicknesses of YU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHOI with the specific lair thicknesses of YU in order to improve heat dissipation (see YU para 21).
Claim(s) 10-11 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHOI (US 20210143126) in view of YU (US 20150235949) and further in view of LEE (US 20220037235)).
Regarding claim 10, CHOI and YU disclose the semiconductor package of claim 9.
CHOI further discloses a device wherein each of the chip stack does not have a liner (324 does not have a liner, see fig 7).
CHOI fails to explicitly disclose a device further comprising a first barrier metal on side and top surfaces of the plurality of first vias,
a second barrier metal disposed on side and bottom surfaces of the second via; and
a liner on a side surface of the second barrier metal.
LEE teaches a device further comprising a first barrier metal on side and top surfaces of the plurality of first vias (the barrier 320 on the upward facing side surfaces of 330, see fig 5, para 31),
a second barrier metal disposed on side and bottom surfaces of the second via (the barrier layer 220 on downward facing side surfaces of 230, see fig 5, para 29); and
a liner on a side surface of the second barrier metal (fig 5, 210, para 29).
CHOI, YU and LEE are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHOI and YU with the barriers and liners of LEE because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHOI and YU with the barriers and liners of LEE in order to increase the density of the device (see LEE para 37).
Regarding claim 11, CHOI and YU disclose the semiconductor package of claim 9.
CHOI further discloses a device, wherein the second via has a first width along a second direction parallel to the top surface of the base chip (314 has a width, see fig 1 and 7, para 37).
CHOI fails to explicitly disclose a device wherein the first width is smaller than or equal to about 10 microns.
LEE teaches a device wherein the first width is smaller than or equal to about 10 microns (second via 200 can have the width of 0.2 microns, see fig 5, para 44).
CHOI, YU and LEE are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHOI and YU with the layer dimensions of LEE because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHOI and YU with the layer dimensions of LEE in order to increase the density of the device (see LEE para 37).
Regarding claim 13, as best as the examiner is able to ascertain the claimed invention, CHOI and YU disclose the semiconductor package of claim 11.
CHOI further discloses, wherein the second via has a first width in the second direction (314 has a width, see fig 1 and 7, para 37).
CHOI fails to explicitly disclose a device wherein the second width is larger than the first width, and wherein the second width is smaller than or equal to about 60 microns.
LEE teaches a device wherein the second width is larger than the first width, and wherein the second width is smaller than or equal to about 60 microns (the width of the second via 300 is less than that of the first via 200, and is 10 microns, see fig 2, para 34).
CHOI, YU and LEE are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHOI and YU with the layer dimensions of LEE because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHOI and YU with the layer dimensions of LEE in order to increase the density of the device (see LEE para 37).
Claim(s) 12 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHOI (US 20210143126), YU (US 20150235949) and LEE (US 20220037235) further in view of LEE-834 (US 20220028834).
Regarding claim 12, CHO, LEEI and YU disclose the semiconductor package of claim 11.
CHOI further discloses, wherein the plurality of first vias have a first height in the first direction (vias 324 have a height, see fig 1 and 7, para 40).
CHOI fails to explicitly disclose a device wherein a first aspect ratio, which is a value obtained by dividing the first height by the second width, is less than or equal to 15.
LEE-834 teaches a device wherein a first aspect ratio, which is a value obtained by dividing the first height by the second width, is less than or equal to 15 (the upper aspect ratio can be 10, see fig 2, para 39).
CHOI, LEE and LEE-834 are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHOI and LEE with the specific dimensions of LEE-834 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHOI and LEE with the specific dimensions of LEE-834 in order to improve reliability (see LEE-834 para 44).
Regarding claim 14, as best as the examiner is able to ascertain the claimed invention, CHO, LEEI and YU disclose the semiconductor package of claim 13.
CHOI further discloses, wherein the second via has a second height in the first direction (the vias 314 have a height, see fig 1 and 7).
CHOI fails to explicitly disclose wherein a device a second aspect ratio, which is a value obtained by dividing the second height by the first width, is less than or equal to 17.
LEE-834 teaches a device wherein a second aspect ratio, which is a value obtained by dividing the second height by the first width, is less than or equal to 17 (the lower aspect ratio can be 10, see fig 2, para 38).
CHOI, LEE and LEE-834 are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHOI and LEE with the specific dimensions of LEE-834 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHOI and LEE with the specific dimensions of LEE-834 in order to improve reliability (see LEE-834 para 44).
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHOI (US 20210143126) in view of KURODA (US 20160379958) and LEE (US 20220037235).
Regarding claim 16, as best as the examiner is able to ascertain the claimed invention, CHOI discloses a semiconductor package, comprising:
a package substrate (package substrate 100, see fig 7, para 30);
an interposer substrate (interposer 200, see fig 7, para 32) on the package substrate;
a chip structure (the chip structure comprising CS1, CS2, 310, 320, 330, 310, 318, 312, 314, 316, 322, 324 and 326, see fig 1 and 7, para 35, 37 and 39), disposed on the interposer substrate; and
a logic chip (chip 400 can be a logic chip, see fig 7, para 46) disposed on the interposer substrate and spaced apart from the chip structure along a first direction parallel to a top surface of the package substrate (400 is spaced apart from CS1 and CS2 in the horizontal direction in fig 7),
wherein the chip structure comprises:
a base chip including a first via (the lower chip 310 including 312 and via 314, see fig 1 and 7, para 37);
chip stacks (the stacks of 320 and 322 over 310 and under the top chip 320 which are at least indirectly on 310, see fig 1 and 7, para 37 and 41) on the base chip; and
a dummy plate on the chip stacks (the top chip 320 which does not have a via 324, see fig 1 and 7, para 41),
wherein the base chip comprises a first semiconductor substrate (fig 1 and 7, 310, para 37) and a first protection layer (fig 1 and 7, 312, para 37) on the first semiconductor substrate,
wherein the chip stacks comprise a second protection layer (fig 1 and 7, 322, para 40), a plurality of memory chips (the memory chips 320 between 310 and the top 320, see fig 1 and 7, para 40) on the second protection layer, and a second via (fig 1 and 7, 324, para 40),
wherein the memory chips comprise a second semiconductor substrate (the chip 400, see fig 1 and 7, para 46) and an interconnection layer (fig 1 and 7, 402, para 46) on the second semiconductor substrate,
wherein the interconnection layer of an uppermost memory chips in each of the chip stacks comprises a landing pad (the bump 326 below the top substrate 320, see fig 1 and 7),
wherein the second protection layer comprises a connection pad (the connectors 326 below each 320 below the top 320, see fig 1 and 7, para 40),
wherein the dummy plate comprises a third semiconductor substrate (the top chip 320, see fig 1 and 7, para 40),
wherein the first semiconductor substrate has a first thickness along a second direction perpendicular to the top surface of the package substrate (310 can have a thickness of 40-100 microns, see fig 1 and 7, para 36),
wherein the second semiconductor substrate has a second thickness along the second direction (320 can have a thickness of 40-100 microns, see fig 1 and 7, para 39),
wherein the first thickness is larger than or equal to about 100 microns (310 can be 100 microns thick, see para 36),
wherein the first protection layer is in contact with the second protection layer, which is included in an lowermost chip stacks (312 and 322 are in at least indirect contact, see fig 7).
CHOI fails to explicitly disclose a device wherein the second thickness ranges from 0 microns to about 10 microns,
wherein a width of the first via along the first direction is larger than a width of the second via along the first direction.
KURODA teaches a device wherein the second thickness ranges from 0 microns to about 10 microns (the thickness of the upper substrate 21 can be 5 microns, see fig 10K, para 89).
CHOI and KURODA are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHOI with the layer dimensions of KURODA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHOI with the layer dimensions of KURODA in order to make a high-performance device at low cost (see KURODA para 125).
CHOI and KURODA fail to explicitly disclose a device wherein a width of the first via along the first direction is larger than a width of the second via along the first direction.
LEE teaches a device wherein a width of the first via along the first direction is larger than a width of the second via along the first direction (the width of the via 1400 through the bottom chip 11 is such that it is larger than the width of the via 3200 through the top chip, see fig 12, para 23 and 73-74).
CHOI, KURODA and LEE are analogous art because they both are directed towards semiconductor interconnect devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of CHOI and KURODA with the specific layer dimensions of LEE because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of CHOI and KURODA with the specific layer dimensions of LEE in order to increase the density of the device (see LEE para 37).
Regarding claim 17, as best as the examiner is able to ascertain the claimed invention, CHOI, KURODA and LEE disclose the semiconductor package of claim 16.
CHOI further discloses a device, wherein the third semiconductor substrate has a third thickness along the second direction, and
the third thickness ranges from about 700 microns to about 775 microns (the thickness of 400 can be 750 microns, see fig 7, para 46).
Regarding claim 18, as best as the examiner is able to ascertain the claimed invention, CHOI, KURODA and LEE disclose the semiconductor package of claim 16.
CHOI further discloses a device, wherein the number of the memory chips in each of the chip stacks is 2N, where N is a positive integer (there can be 32 chips 320, of which a number 2N can be chosen to the be the stack, see fig 1 and 7, para 41).
Regarding claim 19, as best as the examiner is able to ascertain the claimed invention, CHOI, KURODA and LEE disclose the semiconductor package of claim 16.
CHOI further discloses a device, wherein the first and second vias comprise a plurality of first vias (there are a plurality of vias 324 spaced apart horizontally, see fig 1 and 7) and a plurality of second vias (there are a plurality of vias 314 spaced apart horizontally, see fig 1 and 7), which are arranged along the first direction.
Regarding claim 20, as best as the examiner is able to ascertain the claimed invention, CHOI, KURODA and LEE disclose the semiconductor package of claim 16.
CHOI further discloses a device, wherein, except for the uppermost one of the chip stacks, the landing pad in one of the chip stacks is in contact with the connection pad in another chip stack (the 326 for each memory chip 320 CS1 is at least indirectly in contact with a connector 322 in CS2, see fig 1 and 7).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
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