DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file (KR10-2023-0181989 Republic of Korea 12/14/2023).
Information Disclosure Statement
The information Disclosure Statement (IDS) Form PTO-1449, filed 06/25/2024, 08/06/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein was considered by the examiner.
Drawings
The drawings submitted on 06/25/2024. These drawings are review and accepted by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-17 are rejected under both 35 U.S.C. 102(a)(1) as being anticipated by Futatsuyama (US 2019/0371382 A1).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Futatsuyama, for example in Figs. 1-31, discloses a semiconductor device (e.g., 100; in Figs. 1, 5-6, 8-9, 11, 15, 21 related in Figs. 2-4, 7, 10, 12-14, 16-20, 22-31), comprising:
a first structure (e.g., Cell region or 502; in Figs. 6, 8, 15, 21 related in Figs. 1-5, 7, 9-14, 16-20, 22-31) having a first side surface (e.g., contact to Lane R; in Figs. 6, 8, 15, 21 related in Figs. 1-5, 7) and a second side surface opposing each other (e.g., contact to other Lane R; in Figs. 6, 8, 12, 15, 21 related in Figs. 1-5, 7, 9-11, 13-14, 16-20, 22-31), and including a first memory block (included WLHU, Cell region, WLHU; in Figs. 6, 8, 12, 15, 21 related in Figs. 1-5, 7, 9-11, 13-14, 16-20, 22-31) and a second memory block (included WLHU, Cell region, WLHU; in Figs. 6, 8, 12, 15, 21 related in Figs. 1-5, 7, 9-11, 13-14, 16-20, 22-31) sequentially arranged in a first direction from the first side surface to the second side surface (see for example ; in Figs. 6, 8, 15, 21 related in Figs. 1-5, 7, 9-14, 16-20, 22-31); and
a second structure including a peripheral circuit and overlapping the first structure (e.g., above/under memory cell array; in Figs. 8, 15, 21 related in Figs. 1-7, 9-14, 16-20, 22-31),
wherein the first memory block has a first connection region (e.g., Cell region; in Figs. 12-13, 15, 21 related in Figs. 1-11, 14, 16-20, 22-31), a first memory cell array region, and a second connection region sequentially arranged in the first direction (e.g., from Z to Y direction; in Figs. 6, 9, 12, 15, 21 related in Figs. 1-5, 7-8, 10-11, 13-14, 16-20, 22-31),
wherein the second memory block has a third connection region, a second memory cell array region, and a fourth connection region sequentially arranged in the first direction (e.g., WLHU; in Figs. 11-13, 15, 21 related in Figs. 1-10, 14, 16-20, 22-31),
wherein the first memory block includes first gate electrodes that are spaced apart from each other (e.g., WL; in Figs. 15, 21 related in Figs. 1-14, 16-20, 22-31) and extend from the first connection region to the second connection region (e.g., from X to Y direction; in Figs. 15, 21 related in Figs. 1-14, 16-20, 22-31),
wherein the second memory block includes second gate electrodes that are spaced apart from each other (e.g., WL; in Figs. 15, 21 related in Figs. 1-14, 16-20, 22-31) and extend from the third connection region to the fourth connection region (e.g., from X to Y direction; in Figs. 15, 21 related in Figs. 1-14, 16-20, 22-31),
wherein the first gate electrodes of the first memory block include (see for example in Figs. 15, 21 related in Figs. 1-14, 16-20, 22-31):
first word lines having first word line pads that are disposed in the second connection region (see for example in Figs. 15, 21 related in Figs. 1-14, 16-20, 22-31); and
a first upper gate line having a first upper gate pad that is disposed in the first connection region and disposed on the first word lines (see for example in Figs. 15, 21 related in Figs. 1-14, 16-20, 22-31),
wherein the second gate electrodes of the second memory block include (see for example in Figs. 15, 21 related in Figs. 1-14, 16-20, 22-31):
second word lines having second word line pads that are disposed in the third connection region (see for example in Figs. 15, 21 related in Figs. 1-14, 16-20, 22-31); and
a second upper gate line having a second upper gate pad that is disposed in the fourth connection region and disposed on the second word lines (see for example in Figs. 15, 21 related in Figs. 1-14, 16-20, 22-31), and
wherein the first structure includes:
first word line contact plugs connected to the first word line pads (see for example in Figs. 15, 21 related in Figs. 1-14, 16-20, 22-31);
a first upper gate contact plug connected to the first upper gate pad (see for example in Figs. 15, 21 related in Figs. 1-14, 16-20, 22-31);
second word line contact plugs connected to the second word line pads (see for example in Figs. 15, 21 related in Figs. 1-14, 16-20, 22-31); and
a second upper gate contact plug connected to the second upper gate pad (see for example in Figs. 15, 21 related in Figs. 1-14, 16-20, 22-31).
Regarding claim 2, Futatsuyama, for example in Figs. 1-31, discloses wherein the first word line contact plugs penetrate the first word line pads and are in contact with the first word line pads (see for example in Figs. 15-19, 21 related in Figs. 1-14, 20, 22-31), wherein the first upper gate contact plug penetrates the first upper gate pad and is in contact with the first upper gate pad (see for example in Figs. 15-19, 21 related in Figs. 1-14, 20, 22-31), wherein the second word line contact plugs penetrate the second word line pads and are in contact with the second word line pads (see for example in Figs. 15-19, 21 related in Figs. 1-14, 20, 22-31), and wherein the second upper gate contact plug penetrates the second upper gate pad and is in contact with the second upper gate pad (see for example in Figs. 15-19, 21 related in Figs. 1-14, 20, 22-31).
Regarding claim 3, Futatsuyama, for example in Figs. 1-31, discloses wherein the first upper gate line further has a first inner upper gate pad disposed in the second connection region (see for example in Figs. 15-19, 21 related in Figs. 1-14, 20, 22-31), wherein the second upper gate line further has a second inner upper gate pad disposed in the third connection region (see for example in Figs. 15-19, 21 related in Figs. 1-14, 20, 22-31), wherein the first structure further includes: a first inner upper gate contact plug connected to the first inner upper gate pad (see for example in Figs. 15-19, 21 related in Figs. 1-14, 20, 22-31); and a second inner upper gate contact plug connected to the second inner upper gate pad (see for example in Figs. 15-19, 21 related in Figs. 1-14, 20, 22-31).
Regarding claim 4, Futatsuyama, for example in Figs. 1-31, discloses wherein the first
gate electrodes further include a third upper gate line that is disposed on the first upper gate line (see for example in Figs. 8, 15-19, 21 related in Figs. 1-7, 9-14, 20, 22-31), wherein the second gate electrodes further include a fourth upper gate line that is disposed on the second upper gate line (see for example in Figs. 8, 15-19, 21 related in Figs. 1-7, 9-14, 20, 22-31), wherein the first structure further includes: a third upper contact plug connected to the third upper gate line; and a fourth upper contact plug connected to the fourth upper gate line (see for example in Figs. 8, 15-19, 21 related in Figs. 1-7, 9-14, 20, 22-31).
Regarding claim 5, Futatsuyama, for example in Figs. 1-31, discloses wherein the third upper gate line includes a third upper gate pad that is disposed in the first connection region and in contact with the third upper contact plug (see for example in Figs. 8, 15-19, 21 related in Figs. 1-7, 9-14, 20, 22-31), wherein the fourth upper gate line includes a fourth upper gate pad that is disposed in the fourth connection region and in contact with the fourth upper contact plug (see for example in Figs. 8, 15-19, 21 related in Figs. 1-7, 9-14, 20, 22-31), and wherein the first structure includes: a third upper contact plug connected to the third upper gate pad; and a fourth upper contact plug connected to the fourth upper gate pad (see for example in Figs. 8, 15-19, 21 related in Figs. 1-7, 9-14, 20, 22-31).
Regarding claim 6, Futatsuyama, for example in Figs. 1-31, discloses wherein the third upper gate line includes a third upper gate pad that is disposed in the second connection region and in contact with the third upper contact plug (see for example in Figs. 8, 15-19, 21 related in Figs. 1-7, 9-14, 20, 22-31), and wherein the fourth upper gate line includes a fourth upper gate pad that is disposed in the third connection region and in contact with on the fourth upper contact plug (see for example in Figs. 8, 15-19, 21 related in Figs. 1-7, 9-14, 20, 22-31).
Regarding claim 7, Futatsuyama, for example in Figs. 1-31, discloses wherein each of the first and second word lines has a first thickness (see for example in Figs. 8, 15-19, 21 related in Figs. 1-7, 9-14, 20, 22-31), and Wherein each of the first and second upper gate electrodes has a second thickness that is greater than the first thickness (see for example in Figs. 8, 15-19, 21 related in Figs. 1-7, 9-14, 20, 22-31).
Regarding claim 8, Futatsuyama, for example in Figs. 1-31, discloses wherein each of the third and fourth upper gate electrodes has a third thickness that is greater than the second thickness (see for example in Figs. 8, 15-19, 21 related in Figs. 1-7, 9-14, 20, 22-31).
Regarding claim 9, Futatsuyama, for example in Figs. 1-31, discloses wherein the first gate electrodes include third word lines disposed on a level higher than a level of the first word lines and disposed on a level lower than a level of the first upper gate line (see for example in Figs. 8, 15-19, 21 related in Figs. 1-7, 9-14, 20, 22-31), wherein the second gate electrodes further include fourth word lines disposed on a level higher than a level of the second word lines, and disposed on a level lower than a level of the second upper gate line (see for example in Figs. 8, 15-19, 21 related in Figs. 1-7, 9-14, 20, 22-31), wherein the third word lines have third word line pads disposed in the first connection region, wherein the fourth word lines have fourth word line pads disposed in the fourth connection region (see for example in Figs. 8, 15-19, 21 related in Figs. 1-7, 9-14, 20, 22-31), and wherein the first structure further includes: third word line contact plugs connected to the third word line pads; and fourth word line contact plugs connected to the fourth word line pads (see for example in Figs. 8, 15-19, 21 related in Figs. 1-7, 9-14, 20, 22-31).
Regarding claim 10, Futatsuyama, for example in Figs. 1-31, discloses wherein the first gate electrodes of the first memory block further include a first lower gate line that is disposed on a level lower than a level of the first word lines (see for example in Figs. 8, 15-19, 21 related in Figs. 1-7, 9-14, 20, 22-31), wherein the second gate electrodes of the second memory block further include a second lower gate line disposed on a level lower than a level of the second word lines (see for example in Figs. 8, 15-19, 21 related in Figs. 1-7, 9-14, 20, 22-31), wherein the first lower gate line has a first lower gate pad disposed in the second connection region, wherein the second lower gate line has a second lower gate pad that is disposed in the third connection region (see for example in Figs. 8, 15-19, 21 related in Figs. 1-7, 9-14, 20, 22-31), and wherein the first structure further includes: a first lower gate contact plug connected to the first lower gate pad; and a second lower gate contact plug connected to the second lower gate pad (see for example in Figs. 8, 15-19, 21 related in Figs. 1-7, 9-14, 20, 22-31).
Regarding claim 11, Futatsuyama, for example in Figs. 1-31, discloses further comprising: a capping insulating structure disposed between the first memory block and the second memory block (see for example in Figs. 8, 15-19, 21 related in Figs. 1-7, 9-14, 20, 22-31), wherein a portion of the capping insulating structure covers the first word line pads, and wherein the first word line contact plugs penetrate a portion of the capping insulating structure and are in contact with the first word line pads (see for example in Figs. 8, 15-19, 21 related in Figs. 1-7, 9-14, 20, 22-31).
Regarding Independent Claim 12, Futatsuyama, for example in Figs. 1-31, discloses a semiconductor device (e.g., 100; in Figs. 1, 5-6, 8-9, 11, 15, 21 related in Figs. 2-4, 7, 10, 12-14, 16-20, 22-31), comprising:
a first structure (e.g., Cell region or 502; in Figs. 6, 8, 15, 21 related in Figs. 1-5, 7, 9-14, 16-20, 22-31) having a first side surface (e.g., contact to Lane R; in Figs. 6, 8, 15, 21 related in Figs. 1-5, 7) and a second side surface opposing each other (e.g., contact to other Lane R; in Figs. 6, 8, 12, 15, 21 related in Figs. 1-5, 7, 9-11, 13-14, 16-20, 22-31), and including a first connection region, a first memory cell array region, a second connection region (included WLHU, Cell region, WLHU; in Figs. 6, 8, 12, 15, 21 related in Figs. 1-5, 7, 9-11, 13-14, 16-20, 22-31), a third connection region, a second memory cell array region, and a fourth connection region sequentially arranged from the first side surface in a first direction toward the second side surface (included WLHU, Cell region, WLHU; in Figs. 6, 8, 12, 15, 21 related in Figs. 1-5, 7, 9-11, 13-14, 16-20, 22-31); and
a second structure including a peripheral circuit and overlapping the first structure (e.g., above/under memory cell array; in Figs. 8, 15, 21 related in Figs. 1-7, 9-14, 16-20, 22-31), wherein the first structure includes:
first-side conductive layers disposed in the first connection region, the first memory cell array region, and the second connection region (see for example in Figs. 8, 11-13, 15-19, 21 related in Figs. 1-7, 9-10, 14, 20, 22-31);
a first vertical memory structure penetrating the first-side conductive layers in the first memory cell array region (see for example in Figs. 8, 11-13, 15-19, 21 related in Figs. 1-7, 9-10, 14, 20, 22-31);
second-side conductive layers disposed in the third connection region, the second memory cell array region, and the fourth connection region (see for example in Figs. 8, 11-13, 15-19, 21 related in Figs. 1-7, 9-10, 14, 20, 22-31); and
a second vertical memory structure penetrating the second-side conductive layers in the second memory cell array region (see for example in Figs. 8, 11-13, 15-19, 21 related in Figs. 1-7, 9-10, 14, 20, 22-31),
wherein the first-side conductive layers include:
a first lower conductive group having first lower pads that are arranged in a staircase shape in the second connection region (see for example in Figs. 8, 11-13, 15-19, 21 related in Figs. 1-7, 9-10, 14, 20, 22-31); and
a first upper conductive group disposed on a level higher than a level of the first lower conductive group and having first upper pads that are arranged in a staircase shape in the first connection region (see for example in Figs. 8, 11-13, 15-19, 21 related in Figs. 1-7, 9-10, 14, 20, 22-31),
wherein the second-side conductive layers include:
a second lower conductive group disposed at a same level as the first lower conductive group and having second lower pads that are arranged in a staircase shape in the third connection region (see for example in Figs. 8, 11-13, 15-19, 21 related in Figs. 1-7, 9-10, 14, 20, 22-31); and
a second upper conductive group disposed at a same level as the first upper conductive group and having second upper pads that are arranged in a staircase shape in the fourth connection region (see for example in Figs. 8, 11-13, 15-19, 21 related in Figs. 1-7, 9-10, 14, 20, 22-31).
Regarding claim 13, Futatsuyama, for example in Figs. 1-31, discloses wherein, among the first-side conductive layers, a number of first-side conductive layers of the first lower conductive group is greater than a number of first-side conductive layers of the first upper conductive group (see for example in Figs. 8, 11-13, 15-19, 21 related in Figs. 1-7, 9-10, 14, 20, 22-31).
Regarding claim 14, Futatsuyama, for example in Figs. 1-31, discloses wherein, among the first-side conductive layers, the first-side conductive layers of the first lower conductive group include first lower word lines, which have first lower word line pads, and second lower word lines, which are disposed on a level higher than a level of the first lower word lines and have second lower word line pads (see for example in Figs. 8, 11-13, 15-19, 21 related in Figs. 1-7, 9-10, 14, 20, 22-31), and wherein the first structure further includes dummy conductive layers disposed at a same level as the second lower word lines and vertically overlapping the first lower word line pads (see for example in Figs. 8, 11-13, 15-19, 21 related in Figs. 1-7, 9-10, 14, 20, 22-31; see paragraph [0191], [0195]).
Regarding claim 15, Futatsuyama, for example in Figs. 1-31, discloses further comprising: first gate contact plugs connected to the first and second lower pads (see for example in Figs. 15-19, 21 related in Figs. 1-14, 20, 22-31); and second gate contact plugs connected to the first and second upper pads (see for example in Figs. 15-19, 21 related in Figs. 1-14, 20, 22-31).
Regarding claim 16, Futatsuyama, for example in Figs. 1-31, discloses wherein a thickness of at least one of the first-side conductive layers of the first lower conductive group is greater than a thickness of at least one of the first-side conductive layers of the first upper conductive group (see for example in Figs. 8, 15-19, 21 related in Figs. 1-7, 9-14, 20, 22-31).
Regarding claim 17, Futatsuyama, for example in Figs. 1-31, discloses wherein the first upper conductive group has third upper pads arranged in a staircase shape in the second connection region (see for example in Figs. 8, 15-19, 21 related in Figs. 1-7, 9-14, 20, 22-31), and wherein the second upper conductive group has fourth upper pads arranged in a staircase shape in the third connection region (see for example in Figs. 8, 15-19, 21 related in Figs. 1-7, 9-14, 20, 22-31).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Futatsuyama (US 2019/0371382 A1) in view of Baek et al (US 12,075,624 B2 hereinafter “Baek”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 18, Futatsuyama, for example in Figs. 1-31, discloses a data storage system (see for example in Fig. 1 related in Figs. 2-31), comprising:
a semiconductor device (e.g., 100; in Fig. 1 related in Figs. 2-31); and
a controller electrically connected to the semiconductor device (e.g., 200; in Fig. 1 related in Figs. 2-31) and controlling the semiconductor device (see for example; in Fig. 1 related in Figs. 2-31),
wherein the semiconductor device includes:
a first structure (e.g., Cell region or 502; in Figs. 6, 8, 15, 21 related in Figs. 1-5, 7, 9-14, 16-20, 22-31) having a first side surface (e.g., contact to Lane R; in Figs. 6, 8, 15, 21 related in Figs. 1-5, 7) and a second side surface opposing each other (e.g., contact to other Lane R; in Figs. 6, 8, 12, 15, 21 related in Figs. 1-5, 7, 9-11, 13-14, 16-20, 22-31), and including a first memory block (included WLHU, Cell region, WLHU; in Figs. 6, 8, 12, 15, 21 related in Figs. 1-5, 7, 9-11, 13-14, 16-20, 22-31) and a second memory block sequentially arranged in a first direction (included WLHU, Cell region, WLHU; in Figs. 6, 8, 12, 15, 21 related in Figs. 1-5, 7, 9-11, 13-14, 16-20, 22-31); and
a second structure including a peripheral circuit and overlapping the first structure (e.g., above/under memory cell array; in Figs. 8, 15, 21 related in Figs. 1-7, 9-14, 16-20, 22-31),
wherein the first memory block has a first connection region, a first memory cell array region (included WLHU, Cell region, WLHU; in Figs. 6, 8, 12, 15, 21 related in Figs. 1-5, 7, 9-11, 13-14, 16-20, 22-31), and a second connection region sequentially arranged in the first direction (included WLHU, Cell region, WLHU; in Figs. 6, 8, 12, 15, 21 related in Figs. 1-5, 7, 9-11, 13-14, 16-20, 22-31),
wherein the second memory block has a third connection region, a second memory cell array region, and a fourth connection region sequentially arranged in the first direction (included WLHU, Cell region, WLHU; in Figs. 6, 8, 12, 15, 21 related in Figs. 1-5, 7, 9-11, 13-14, 16-20, 22-31),
wherein the first memory block includes first gate electrodes that are spaced apart from each other in a vertical direction (e.g., WL; in Figs. 15, 21 related in Figs. 1-14, 16-20, 22-31) and extend from the first connection region to the second connection region (e.g., from X to Y direction; in Figs. 15, 21 related in Figs. 1-14, 16-20, 22-31),
wherein the second memory block includes second gate electrodes that are spaced apart from each other in the vertical direction (e.g., WL; in Figs. 15, 21 related in Figs. 1-14, 16-20, 22-31) and extend from the third connection region to the fourth connection region (e.g., from X to Y direction; in Figs. 15, 21 related in Figs. 1-14, 16-20, 22-31),
wherein the first gate electrodes of the first memory block include:
first word lines having first word line pads that are disposed in the second connection region (see for example in Figs. 15-19, 21 related in Figs. 1-14, 20, 22-31); and a first upper gate line having a first upper gate pad that is disposed in the first connection region and disposed on the first word lines (see for example in Figs. 15-19, 21 related in Figs. 1-14, 20, 22-31),
wherein the second gate electrodes of the second memory block includes:
a second word lines having second word line pads that are disposed in the third connection region (see for example in Figs. 15-19, 21 related in Figs. 1-14, 20, 22-31); and
a second upper gate line having a second upper gate pad that is disposed in the fourth connection region and disposed on the second word lines (see for example in Figs. 15-19, 21 related in Figs. 1-14, 20, 22-31),
wherein the first structure includes:
first word line contact plugs connected to the first word line pads (see for example in Figs. 15-19, 21 related in Figs. 1-14, 20, 22-31);
a first upper gate contact plug connected to the first upper gate pad (see for example in Figs. 15-19, 21 related in Figs. 1-14, 20, 22-31);
second word line contact plugs connected to the second word line pads (see for example in Figs. 15-19, 21 related in Figs. 1-14, 20, 22-31); and
a second upper gate contact plug connected to the second upper gate pad (see for example in Figs. 15-19, 21 related in Figs. 1-14, 20, 22-31).
However, Futatsuyama is silent with regard to the controller electrically connected to the semiconductor device through a input/output pad.
In the same field of endeavor, Baek, for example in Figs. 1-13, discloses the controller electrically connected to the semiconductor device through a input/output pad (e.g., 2210 through 2005; in Fig. 1B related in Figs. 2-13).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Futatsuyama such as semiconductor memory device (see for example in Figs. 1-31 of Futatsuyama) by incorporating the teaching of Baek such as three-dimensional semiconductor memory device (see for example in Figs. 1-13 of Baek). In order to provided is a three-dimensional semiconductor memory device including a first substrate that includes a cell array region and a connection region; first and second electrode layers that are sequentially stacked and spaced apart from each other (Baek, see abstract).
Regarding claim 19, the above Futatsuyama/Baek, combination discloses wherein the first upper gate line further includes a first inner upper gate pad that is disposed in the second connection region, wherein the second upper gate line further includes a second inner upper gate pad that is disposed in the third connection region (see for example in Figs. 15-19, 21 related in Figs. 1-14, 20, 22-31 of Futatsuyama and also see in Figs. 1-13 of Baek, as discussed above), and wherein the first structure further includes: a first inner upper gate contact plug connected to the first inner upper gate pad (see for example in Figs. 15-19, 21 related in Figs. 1-14, 20, 22-31 of Futatsuyama and also see in Figs. 1-13 of Baek, as discussed above); and a second inner upper gate contact plug connected to the second inner upper gate pad (see for example in Figs. 15-19, 21 related in Figs. 1-14, 20, 22-31 of Futatsuyama and also see in Figs. 1-13 of Baek, as discussed above).
Regarding claim 20, the above Futatsuyama/Baek, combination discloses wherein a thickness of each of the first and second upper gate lines is greater than a thickness of each of the first and second word lines (see for example in Figs. 15-19, 21 related in Figs. 1-14, 20, 22-31 of Futatsuyama and also see in Figs. 1-13 of Baek, as discussed above).
Conclusion
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/THA-O H BUI/ Primary Examiner, Art Unit 2825 12/11/2025