Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/753,221 filed on 06/25/2024.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Pub # 2003/0057497 to Higashida et al. (Higashida).
Regarding independent claim 1, Higashida discloses a semiconductor device (Fig. 2) comprising:
a semiconductor substrate (Fig. 2: 4a) having at least one element region in which a transistor is disposed;
an interlayer insulating film (6) disposed above the semiconductor substrate; and
a semiconductor layer (Fig. 2: n p n and see Examiner’s Mark-up below) disposed above the interlayer insulating film, wherein the semiconductor layer (n p n) includes:
a first semiconductor layer (see Examiner’s Mark-up below - 1) of a first conductivity type (n) connected (via source wiring) to a gate of the transistor;
a second semiconductor layer (see Examiner’s Mark-up below - 2) of a second conductivity type (p) connected to the first semiconductor layer; and
a third semiconductor layer (see Examiner’s Mark-up below - 3) of the first conductivity type connected to the second semiconductor layer and connected to a low potential terminal (see Examiner’s Mark-up below) of the transistor.
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Regarding claim 2, Higashida discloses wherein the semiconductor substrate further includes a peripheral region disposed (see Examiner’s Mark-up above from claim 1) around the at least one element region (see Examiner’s Mark-up above from claim 1) when the semiconductor substrate is viewed from above, and the semiconductor layer (n p n) is disposed in the peripheral region.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4-8 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2003/0057497 to Higashida et al. (Higashida) in view of US Pub # 2010/0025693 to Malhan et al. (Malhan).
Regarding claim 4, Higashida disclose all of the limitations of claim 1 from which this claim depends.
Higashida fails to explicitly discloses wherein a material that constitutes the semiconductor layer has a smaller band gap than a material that constitutes the semiconductor substrate.
Malhan discloses wherein a material that constitutes the semiconductor layer has a smaller band gap than a material that constitutes the semiconductor substrate (¶0013).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have modify the material that constitutes the semiconductor layer and the semiconductor substrate of Higashida with the band gap of the semiconductor layer and the semiconductor substrate as taught by Malhan in order to have a high breakdown voltage between the transistor cell region and the diode forming region (¶0014).
Regarding claim 5, Higashida disclose all of the limitations of claim 1 from which this claim depends.
Higashida disclose the concentration of the n-type layer 1a and p-type layer 1b are, for example, approximately 5x1020 cm-3, 7x1017 cm-3 (¶0037). thereby forming the bidirectional zener diode.
Higashida fails to explicitly discloses wherein a peak concentration of a first conductivity type impurity in each of the first semiconductor layer and the third semiconductor layer is X 10¹⁸ cm⁻³ or more, and a peak concentration of a second conductivity type impurity in the second semiconductor layer is 5x10¹⁷ cm⁻³ or less.
The concentration of the first, second and third semiconductor layer of ¶0037 result in the claimed difference in concentration but is silent as to the concentration range between them (in other words, fails to disclose 1x1018 cm-3 is for the third semiconductor layer. However, the concentrations selected is a result effective variable affecting the formation of the bidirectional diode so as to get desire break down voltage ¶0037). Accordingly, it would have been obvious to one of ordinary skill in the art at, or before the filing of the instant invention to vary, through routine experimentation, concentration in order to optimize the functionality of the device (see MPEP §2144.05). Further, the specification contains no disclosure of either the critical nature of the claimed concentration or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990)
Regarding claims 6 and 7, Higashida disclose all of the limitations of claim 1 from which this claim depends. Higashida discloses wherein the first conductivity type is n-type and the second conductivity type is p-type (¶0037), and a region in the first semiconductor layer being in contact with the second semiconductor layer (Fig. 2) (claim 6) and wherein the first conductivity type is p-type and the second conductivity type is n-type (see Fig. 2) (claim 7).
Higashida fails to explicitly disclose a region in the first semiconductor layer being in contact with the second semiconductor layer and a lower n-type impurity concentration than a region in the first semiconductor layer being in contact with the gate (claim 6) and a region in the third semiconductor layer being in contact with the second semiconductor layer has a lower p-type impurity concentration than a region in the third semiconductor layer being in contact with the low potential terminal (claim 7).
The impurity concentration of the first, second and third semiconductor layer of ¶0037 result in the claimed difference in impurity concentration but is silent as to the impurity concentration being lower. However, the impurity concentration selected is a result effective variable affecting the formation of the bidirectional diode so as to get desire break down voltage ¶0037). Accordingly, it would have been obvious to one of ordinary skill in the art at, or before the filing of the instant invention to vary, through routine experimentation, impurity concentration in order to optimize the functionality of the device (see MPEP §2144.05). Further, the specification contains no disclosure of either the critical nature of the claimed impurity concentration or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990)
Regarding claim 8, Higashida discloses the semiconductor layer is made of polysilicon (see abstract).
Higashida fails to explicitly discloses wherein the semiconductor substrate is made of a wide-gap semiconductor.
Malhan discloses wherein the semiconductor substrate is made of a wide-gap semiconductor (¶0015).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the semiconductor substrate of Higashida with the wide-gap semiconductor substrate as taught by Malhan in order for the semiconductor device to have a high breakdown voltage between the transistor cell region and the diode forming region (¶0016).
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 3 recites:
“wherein the at least one element region includes two element regions, and the semiconductor layer is disposed in a range sandwiched between the two element regions when the semiconductor substrate is viewed from above.”
The considered prior art of record appears to fail to teach or render obvious the instant limitation in combination with all of the limitations of the independent claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pat # 8,344,457 to Noguchi et al., US Pat # 5798554 to Grimaldi et al. and US Pat # 8492867 to Yamamoto et al.
Noguchi discloses an n type semiconductor substrate 1, channel regions 4, first insulating films 11, gate electrodes 13, source regions 15, body regions 14, second insulating films 16, a gate pad electrode 18, a source electrode 17, and protection diodes 12d, the gate electrodes 13 are formed into a stripe shape on the surface of the n type semiconductor substrate 1 with gate oxide films which is the first insulating films interposed therebetween, the gate electrodes 13 are formed by patterning polysilicon which has been deposited and then doped with impurities to reduce the resistance, the channel regions 4 are p type impurity regions formed in the surface of the n type semiconductor substrate 1 into a stripe shape along the gate electrodes 13, the source regions 15 are n+ impurity regions formed in the surface of the channel regions 4 along the gate electrodes 13 and each of the body regions 14 is a p+ type impurity region formed along the gate electrodes 13, and between the adjacent source regions 15 in the surface of the channel region 4, so as to stabilize the electric potential of the substrate.
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/MOHSEN AHMADI/ Primary Examiner, Art Unit 2896
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