Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the gate electrode having a vertically asymmetrical shape in claim 19 must be shown or the feature(s) canceled from the claim(s). Currently, the drawings show a gate electrode having a vertical symmetry in that they are symmetrical across a vertical axis, and a horizontal asymmetry in that they are asymmetrical across a horizontal axis. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The claim language “the gate electrode has a vertically asymmetrical shape” does not particularly point out the subject matter shown in the figures. Vertical symmetry is defined as symmetry across a vertical axis. Examiner believes claim 19 is intended to read “the gate electrode has a horizontally asymmetrical shape” to indicate that the gate electrode’s lower portion is not a reflection of the gate electrode’s upper portion, as shown in Applicant’s figures.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-18 are rejected under 35 U.S.C. 103 as being unpatentable over Imam (CN 116741824 A) in view of JP WO2015177914 A1.
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Regarding claim 1, JP WO2015177914 A1 discloses a power semiconductor device (Fig. 18), comprising: a substrate (101) having a first conductivity-type (Abstract "a first conductivity type semiconductor substrate"); a drift layer (102) on the substrate, the drift layer having the first conductivity-type (Abstract "a first conductivity type drift layer"); a well region (body layer/well region 105) on the drift layer, the well region having a second conductivity-type (Abstract "second conductivity type body layer"); a source region (107) on the well region, the source region having the first conductivity-type (Abstract "a first conductivity type source"); a gate electrode (111) in a gate trench (109, labeled in Fig. 9C) penetrating the source region and the well region (Shown); a gate insulating layer (110) between the gate electrode and the well region (Shown in Fig. 18); a dielectric layer (112) on the gate electrode (Shown); and a drain electrode (116) on a lower surface of the substrate (Shown), wherein a lower surface (Bottom most surface of 111) of the gate electrode has a first width, an upper surface (upper most surface of 111) of the gate electrode has a second width that is greater than the first width (Shown) and a side surface of the gate electrode has a step portion where a width of the gate electrode changes (See attached figure). However, JP WO2015177914 A1 does not disclose the step portion is positioned at a level lower than a level of a lower surface of the source region.
On the other hand, Imam discloses the step portion (Shown in fig. 1) is positioned at a level lower than a level of a lower surface of the source region (Comprises 220 and 230). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify JP WO2015177914 A1 according to the teachings of Imam such that the gate electrode would be recessed further into the device layers and the gate electrode would be elongated such that the step portion would be positioned at a level lower than a level of a lower surface of the source region, in order to improve electrical performance and efficiency by increasing the contact area between the gate electrode and the surrounding layers.
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Regarding claim 2, JP WO2015177914 A1 discloses wherein a surface of the well region facing the gate electrode has a bent shape and comprises a first surface and a second surface extending from the first surface (See attached figure).
Regarding claim 3, JP WO2015177914 A1 discloses the first surface extending along the source region and the well region (Shown in Fig. 18); and the second surface extending downwardly through the well region (Shown in above attached figure). However, JP WO2015177914 A1 does not disclose the first surface being a curved surface.
On the other hand, Imam the first surface being a curved surface (Fig. 2E; bottom of pg. 9 "140A of the present invention includes a rounded corner such that the subsequently formed gate dielectric layer 150 and the gate electrode 160 may be contoured such that the stress generated by such a profile is less than the stress generated by the sharp-angled profile"). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify JP WO2015177914 A1 according to the teachings of Imam such that the first surface would be a curved surface curving into the second surface, in order to improve consistency of deposition, adhesion, and avoid voids in the layers by avoiding sharp corners at material interfaces.
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Regarding claim 4, JP WO2015177914 A1 discloses the first surface is an upper surface of the well region; and the second surface extends downwardly through the well region (See attached figure).
Regarding claim 5, JP WO2015177914 A1 discloses wherein an angle between the first surface and the second surface is a right angle (Shown).
Regarding claim 6, Imam discloses wherein the lower surface of the gate electrode is positioned at a level lower than a level of a lower surface of the well region (Fig. 1 shows lowest portion of gate electrode 160 positioned lower than lower surface of well region comprising 120 and 130).
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Regarding claim 7, JP WO2015177914 A1 discloses wherein the gate insulating layer has a first thickness on a bottom surface of the gate trench and a second thickness on a sidewall of the gate trench, the second thickness is less than the first thickness (See attached figure).
Regarding claim 8, Imam discloses wherein the upper surface of the gate electrode is positioned at a same level or a lower level than an upper surface of the source region (Fig. 1 shows upper surface of gate electrode 160 positioned lower than an upper surface of upper surface of source region comprising 220 and 230).
Regarding claim 9, JP WO2015177914 A1 discloses wherein the upper surface of the gate electrode is positioned at a level higher than a level of an upper surface of the source region (Shown in Fig. 18).
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Regarding claim 10, JP WO2015177914 A1 discloses wherein the gate electrode is spaced apart from the source region in a horizontal direction by the well region and the gate insulating layer (See attached figure).
Regarding claim 11, JP WO2015177914 A1 discloses further comprising: a source electrode (Fig. 18, 113) on the dielectric layer, the source electrode being electrically connected to the source region (Shown).
Regarding claim 12, JP WO2015177914 A1 discloses wherein the substrate, the drift layer, and the well region comprise SiC (Top of pg. 4 "SiC substrate made of silicon carbide (SiC) (substrate) 101"; bottom of pg. 6 "epitaxial layer 102 of silicon carbide"; process P2 describes the well region being formed in the drift layer by ion implantation, therefore the well region would necessarily also comprise SiC).
Regarding claim 13, JP WO2015177914 A1 discloses a field relief region (Fig. 18, portion of body layer/well region 105 immediately beneath lower surface of gate electrode 111) between the gate insulating layer and the drift layer (Shown), the field relief region having the second conductivity-type (Abstract "second conductivity type body layer").
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Regarding claim 14, JP WO2015177914 A1 discloses a power semiconductor device (Fig. 18), comprising: a substrate (101) having a first conductivity-type (Abstract "a first conductivity type semiconductor substrate"); a drift layer (102) on the substrate, the drift layer having the first conductivity-type (Abstract "a first conductivity type drift layer"); a well region (body layer/well region 105) on the drift layer, the well region having a second conductivity-type (Abstract "second conductivity type body layer"); a source region (107) on the well region, the source region having the first conductivity-type (Abstract "a first conductivity type source"); a gate electrode (111) in a gate trench (109, labeled in Fig. 9C) penetrating the source region and the well region (Shown); a gate insulating layer (110) between the gate electrode and the well region (Shown in Fig. 18); a dielectric layer (112) on the gate electrode (Shown); and a drain electrode (116) on a lower surface of the substrate (Shown), wherein the gate electrode includes a first region having a first width that is a maximum width of the first region, and a second region on the first region, the second region having a second width greater than the first width (See attached figure), the well region includes a channel region (Bottom of pg. 5 "The channel region... is the surface of the trench 109 and the surface of the p-type body layer 105 sandwiched between the trenches 109") adjacent to the gate electrode (Shown). However, JP WO2015177914 A1 does not disclose the channel region includes a region overlapping the first region in a horizontal direction and overlapping the second region in a vertical region.
On the other hand, Imam discloses the channel region includes a region overlapping the first region in a horizontal direction and overlapping the second region in a vertical region (See attached
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figure; bottom of pg. 7 "during the operation of the element, a vertical channel region may be created through the well region 130, the doped region 120, and the epitaxial layer 110"; the channel region would inherently follow the form of the gate electrode). would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify JP WO2015177914 A1 according to the teachings of Imam such that the gate electrode would be recessed further into the device layers and the gate electrode would be elongated such that the channel region would include a region overlapping the first region in a horizontal direction and overlapping the second region in a vertical direction, in order to improve electrical performance and efficiency by increasing the contact area between the gate electrode and the surrounding layers.
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Regarding claim 15, JP WO2015177914 A1 discloses wherein the channel region has a bent shape and extends along the gate electrode (See attached figure).
Regarding claim 16, Imam discloses wherein the channel region extends from the source region to the drift layer (The channel region would inherently follow the contour of the gate electrode through layers 130, 120 and 110 from the source region to the drift layer).
Regarding claim 17, Imam discloses wherein a length of the first region is greater than a length of the second region in the vertical direction (Shown in Fig. 1).
Regarding claim 18, JP WO2015177914 A1 discloses wherein the gate electrode has a recessed portion on an upper surface, the recessed portion is recessed towards the substrate (Shown).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over JP WO2015177914 A1 in view of Jung (KR 20190100012 A).
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Regarding claim 19, JP WO2015177914 A1 discloses a power semiconductor device (Fig. 18), comprising: a substrate (101) having a first conductivity-type (Abstract "a first conductivity type semiconductor substrate"); a drift layer (102) on the substrate, the drift layer having the first conductivity-type (Abstract "a first conductivity type drift layer"); a well region (body layer/well region 105) on the drift layer, the well region having a second conductivity-type (Abstract "second conductivity type body layer"); a source region (107) on the well region, the source region having the first conductivity-type (Abstract "a first conductivity type source"); a gate electrode (111) in a gate trench (109, labeled in Fig. 9C) penetrating the source region and the well region (Shown); a gate insulating layer (110) covering an internal surface of the gate trench (Shown); and a drain electrode (116) on a lower surface of the substrate (Shown), wherein an upper surface of the gate electrode has a maximum width (Shown in Fig. 18) and the gate electrode has a horizontally asymmetrical shape (Shown), and the well region includes a region facing the gate electrode that has a bent shape (See attached figure). However, JP WO2015177914 A1 does not disclose a field relief region covering a portion of an external surface of the gate insulating layer the field relief region having the second conductivity-type.
On the other hand, Jung discloses a field relief region (Fig. 11, 200) covering a portion of an external surface of the gate insulating layer (200 is shown covering insulating layer 125), the field relief region having the second conductivity-type (Bottom of pg. 4 "the second conductivity type shield 200"). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify JP WO2015177914 A1 according to the teachings of Jung such that a field relief region would cover a portion of an external surface of the gate insulating layer and have a second conductivity-type, in order to prevent or lessen damage to the gate insulating film due to concentrated electric fields at the edge of the trench (Jung Background section “an electric field concentrated near the edge of the trench destroys the trench insulating film. To prevent this, the P shield is formed on the bottom surface of the trench”; terms “second conductive shield” and “P shield” are indicated to be interchangeable throughout Jung’s specification).
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Regarding claim 20, JP WO2015177914 A1 discloses wherein a first thickness of the gate insulating layer on a bottom surface of the gate trench is different from a second thickness of the gate insulating layer on a sidewall of the gate trench (See attached figure).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL J SMITH whose telephone number is (703)756-5706. The examiner can normally be reached M-F 8-5 EST.
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/S.J.S./ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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