DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities: “…a plurality of items of the first data is arranged on one axis and a plurality of values of the respective items is arranged…” should be amended to read: “…a plurality of items of the first data are arranged on one axis and a plurality of values of the respective items are arranged…”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites: “…each group of a plurality of semiconductor chips having the same test environment,” in which “a plurality of semiconductor chips” is confusing because a plurality of semiconductor chips has already been recited. Furthermore, “the same test environment” has no antecedent basis. For examination purposes it will be assumed that the above should be replaced with: “…each group of the plurality of semiconductor chips having a same test environment”.
Claim 3 recites “…the second data indicates pass/fail for each category…”; here “each category” has no antecedent basis. For examination purposes it will be assumed that the above should be changed to recite: “…the second data indicates pass/fail for one or more categories…”
Claims 2 and 4-5 depend from claim 1, therefore they inherit the same issues and are rejected for the same reasons.
Claims 6 and 7 copy much of the language of claim 1, therefore they are rejected for the same reasons as claim 1.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-7 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
At Step 1 of the 101 analysis, all claims are directed to one of the statutory categories of invention.
At Step 2A Prong One, the judicial exceptions are bolded in the copy of claim 1 below:
A semiconductor test result analysis device comprising:
a first acquirer structured to acquire first data of a plurality of items related to a test process of a plurality of semiconductor chips;
a second acquirer structured to acquire second data indicating test results of the plurality of semiconductor chips in the test process; and
a graph generator structured to generate, in a region in which a plurality of items of the first data is arranged on one axis and a plurality of values of the respective items is arranged in a direction orthogonal to the axis, a graph image in which corresponding values are connected by lines over the plurality of items for each group of a plurality of semiconductor chips having the same test environment, wherein the graph generator changes a form of the lines for each group in the graph image according to a ratio of semiconductor chips whose test results have been failed in each group.
Acquiring data by an acquirer is encompassed by a person reading data from a list or noting observations. Generating a graph in the manner described above is encompassed by a person reading data values and drawing a graph with the aid of a pen and paper.
At Step 2A Prong Two, the preamble recites that a semiconductor test result analysis device. This may or may not be limiting, since the preamble may or may not limit a claim (see MPEP §2111.02). Assuming arguendo that this is limiting, it simply recites that a set of judicial exceptions is performed on a device encompassed by a general-purpose computer in the field of semiconductor testing (see MPEP § 2106.05(f)(2) and MPEP §2106.05(h)). Therefore, the additional elements do not integrate the judicial exceptions into a practical application.
At Step 2B, when considered as a whole, the claim does not amount to significantly more than the judicial exceptions for the reasons given above.
Claim 2 describes what data is gathered but does not fix the issues of claim 1, therefore claim 2 is also rejected.
Claim 3 recites generating graphs for multiple categories of tests, and is therefore rejected for essentially the same reasons as claim 1.
Claim 4 applies a decision tree generator and outputter to output an item which is considered important to predicting a test result. Again, a person is capable of performing such a task with pen and paper, therefore claim 4 is also rejected.
Claim 5 recites setting the important item as one of the items in the graph; again, this represents a further judicial exception and claim 5 is also rejected.
Claims 6 and 7 recite many of the limitations of claim 1, and any other limitations are encompassed by applying a general-purpose computer to the judicial exceptions as noted in the rejection of claim 1. Therefore, claims 6 and 7 are rejected for the same reasons as claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Taira (US 20020132381 A1) in view of The Economist (“Seeking safety: European asylum application flows: acceptances and rejections” taken on 11 August 2026 from https://www.economist.com/graphic-detail/2015/05/12/seeking-safety; hereinafter “Econ”).
Regarding claim 1, Taira discloses a semiconductor test result analysis device (Abstract: “Semiconductor integrated circuit device fabricating method and testing method are provided.”). Taira further discloses a test process of a plurality of semiconductor chips (¶45: in S101 chips are formed on wafers; ¶46: in S102 the chips on the wafers are tested for defects). While Taira does not explicitly disclose acquiring first data of a plurality of items related to the above test process, Taira does have access to such data (Abstract: lots are known; ¶49 and Fig. 3: a probe check is implemented; the check is implemented on lots, uses jigs; the test devices used are accessible by Taira; to test each chip it would be reasonable to direct instruments to the coordinates of each chip). Furthermore, Taira discloses an instrument which may be used as a first acquirer, second acquirer, and graph generator (Fig. 4, a system comprising the elements in Fig. 4 which includes computers; see also ¶63).
It would have been obvious for Taira to structure a first acquirer to acquire first data of a plurality of items related to a test process of a plurality of semiconductor chips in order to keep track of data related to the test process in case it is needed for evaluating the test results.
Taira further discloses acquiring second data indicating test results of the plurality of semiconductor chips in the test process (¶63 and Fig. 4, the system comprising the elements in Fig. 4 includes PC 7 for test results collection). Finally, Taira discloses detecting trouble and monitoring operations, including a display (¶63). A host computer displays a trouble detection and operation on the basis of test results and operation information (¶73).
Taira does not explicitly disclose the remaining limitations of claim 1.
Econ generates a graph image (an alluvial diagram) in a region in which a plurality of items (“Origin”, “Destination”, and “Total decisions”; “Decisions by origin” is also present, but it represents a second line of questioning) are arranged on one axis and a plurality of values of the respective items are arranged in a direction orthogonal to the axis (for example, for “Origin” the countries of “Syria”, “Serbia” etc. are arranged orthogonally), in which corresponding values are connected by lines over the plurality of items for every group satisfying a relation (for example, there is a line for a group of Syrians applying for asylum in Sweden and being accepted), wherein the form of the line for each group is changed according to some metric (line thickness is proportional to the number of asylum seekers represented).
Econ demonstrates that alluvial diagrams are used in seeking to understand complex, multi-parameter datasets.
Furthermore, the examiner takes official notice that troubleshooting possible causes of failures is known in product testing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Econ with the invention of Taira by structuring a graph generator to generate, in a in a region in which a plurality of items of the first data are arranged on one axis and a plurality of values of the respective items are arranged in a direction orthogonal to the axis, a graph image in which corresponding values are connected by lines over the plurality of items for each group of the plurality of semiconductor chips having a same test environment, wherein the graph generator changes a form of the lines for each group in the graph image according to a metric. Doing so would provide a user with an intuitive visualization of a complex dataset indicating parameters involved in the testing of semiconductor chips. Furthermore, it would have been obvious to cause the metric by which the lines’ forms are changed to be a ratio of semiconductor chips whose test results have been failed in each group. Doing so would enable a user to visualize potential factors influencing chip failure results.
Regarding claim 2, Taira in view of Econ teaches the limitations of claim 1. Furthermore, noting from the rejection of claim 1 that Taira has access to a number of items such as a probe card, a jig, semiconductor test devices, lot numbers, coordinates of semiconductor chips on a wafer, etc., it would have been obvious to cause the first data to include at least one of: a pushing amount of a probe card into each of the semiconductor chips, a jig ID, an ID of an operator in charge of a test, an ID of a semiconductor test device, a lot ID of each of the semiconductor chips, coordinates of each of the semiconductor chips on a wafer, and the number of tests. Doing so would enable one to troubleshoot these as potential causes of failure results. The examiner notes that, when troubleshooting a process, it is often useful to have more data relevant to the process so that more potential sources of failure can be studied with greater certainty. The examiner also considers the list of data in claim 2 to be clearly relevant to the process of failure testing semiconductor chips on a wafer using a probe card.
Regarding claims 6-7, claims 6 and 7 recite a semiconductor test result analysis method comprising and a non-transitory computer-readable recording medium encoded with a computer program for causing a computer to realize the limitations of claim 1, therefore claims 6 and 7 are rejected for the same reasons as claim 1.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Taira (US 20020132381 A1) in view of The Economist (“Seeking safety: European asylum application flows: acceptances and rejections” taken on 11 August 2026 from https://www.economist.com/graphic-detail/2015/05/12/seeking-safety; hereinafter “Econ”), and further in view of Bismuth (US 20200309850 A1).
Regarding claim 3, Taira in view of Econ teaches the limitations of claim 1,but does not explicitly teach the limitations of claim 3. Claim 3 is encompassed by semiconductor chips being given a pass/fail status for one or more categories, and for the graph generation described in claim 1 to occur for each category.
Bismuth tests electronic circuitry including chips on a wafer (see Fig. 1 and ¶15). Bismuth teaches that multiple kinds of tests can be performed (¶19: a connectivity test, functionality tests, and other tests may be performed on a DUT).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Bismuth with the invention of Taira in view of Econ by causing the second data to indicate pass/fail for one or more categories determined in advance as the test results, the graph generator to generate a graph image for each category, and the graph generator to change a form of a line for each group in a graph image of a certain category according to a ratio of semiconductor chips whose test results of the corresponding category have been failed in each group. Doing so would enable a user to visualize potential factors influencing chip failure results for each category of failure.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Taira (US 20020132381 A1) in view of The Economist (“Seeking safety: European asylum application flows: acceptances and rejections” taken on 11 August 2026 from https://www.economist.com/graphic-detail/2015/05/12/seeking-safety; hereinafter “Econ”), and further in view of Muller (“Introduction to machine learning with Python”).
Regarding claim 4, Taira in view of Econ teaches the limitations of claim 1 but does not explicitly teach the limitations of claim 4.
Muller teaches that decision trees are widely used for classification (pg. 70). Decision trees learn a sequence of if/else questions to apply to feature values (i.e. input data) to arrive at a true result (i.e. output data) in a most efficient way (see pg. 71 under “Building decision trees”; see also Fig. 2-26 on pg. 74 giving an example of a decision tree). Decision trees can also be used to determine “feature importance”, that is how important input features are to the decisions the tree makes (see pg. 77 under “Feature importance in trees”; see also Fig. 2-28 on pg. 78, where “worst radius” is the most important feature in a Breast Cancer dataset for predicting whether a tumor is benign or malignant).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Muller with the invention of Taira in view of Econ by including a decision tree generator structured to generate a decision tree with each item of the first data as a feature amount and the second data as a target value; and an outputter structured to cause information of a feature amount having a relatively high importance in the decision tree to be displayed as an item having a large influence on the test results together with the graph image. Doing so would enable one to see what item in the first data has a highest influence on a semiconductor chip’s test result.
Regarding claim 5, Taira in view of Econ and Muller teaches the limitations of claim 4 but does not explicitly teach the limitations of claim 5. However, it would have been obvious to cause the graph generator to automatically set an item corresponding to the feature amount having a relatively high importance in the decision tree as an item of the first data set in the graph image. Doing so would ensure that the graph depicts the item which is most influential on semiconductor chip failure results, maximizing the graph’s usefulness in helping a user visualize potential factors influencing chip failure results.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ETHAN WESLEY EDWARDS whose telephone number is (571)272-0266. The examiner can normally be reached Monday - Friday, 7:30am-5pm.
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ETHAN WESLEY EDWARDS
Examiner
Art Unit 2857
/E.W.E./ Examiner, Art Unit 2857
/ANDREW SCHECHTER/ Supervisory Patent Examiner, Art Unit 2857
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