DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4, 8, 18-19, & 23 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sharma et al. (US 2023/0209800) [Hereinafter Sharma].
Regarding claim 1, Sharma teaches An integrated circuit product comprising:
a first integrated circuit die [fig. 10D, die 1072, para 67] having a first die interface [annotated fig. 10D],
the first integrated circuit die (fig. 10D, 1072) being formed using a semiconductor substrate [fig. 10D, package substrate 1062, para 67 & para 34 teaches dies being made within a wafer such as silicon wafer];
a second integrated circuit die [fig. 10D, die 1074, para 67] having a second die interface [annotated fig.10D
the second integrated circuit die (fig. 10D, 1072) being formed using the semiconductor substrate (fig. 10D, 1062);
a scribe line of a first surface of the semiconductor substrate [annotated fig. 10D],
the first integrated circuit die (fig. 10D, 1072) being adjacent to the scribe line [annotated fig. 10D] and
the second integrated circuit die (fig. 10D, 1074) being adjacent to the scribe line [annotated fig. 10D]; and
a jumper die [fig. 10D, bridge die 1064, para 67] coupled to the first die interface and coupled to the second die interface [para 67, “A bridge die 1064 is in the open cavity 1066. A first die 1068, a second die 1070, a third die 1072, and a fourth die 1074 are coupled together by the bridge die 1064.”],
wherein the jumper die spans the scribe line [annotated fig. 10D],
a first portion of the jumper die is stacked with a first portion of the first integrated circuit die [annotated fig. 10D], and
a second portion of the jumper die is stacked with a first portion of the second integrated circuit die [annotated fig. 10D].
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ANNOTATED FIG. 10D
Regarding claim 4, Sharma teaches The integrated circuit product as recited in claim 1 further comprising:
an additional die [fig. 10D, die 1068, para 67] coupled to the first integrated circuit die [para 67] and stacked with the first integrated circuit die (fig. 10D, 1072),
the additional die (fig. 10D, 1068) being laterally adjacent to the jumper die (fig. 10D, 1064) with respect to the first surface of the semiconductor substrate (fig. 10D, 1062),
wherein a space between the additional die and the jumper die has the same width as the scribe line [fig. 10D; wherein the space between each die and the bridge die are the same].
Regarding claim 8, Sharma teaches The integrated circuit product as recited in claim 1 further comprising:
at least one additional integrated circuit die [fig. 10D, die 1068, para 67] adjacent to the first integrated circuit die (fig. 10D, 1072) or the second integrated circuit die and diagonally opposite to the other integrated circuit die of the first integrated circuit die and the second integrated circuit die [fig. 10D; wherein die 1068 is diagonally opposite of second die 1074]; and
wherein a third portion of the jumper die [fig. 10D; portion of bridge die 1064 coupled to die 1068] is stacked with a first portion of the at least one additional integrated circuit die attached to a corresponding die interface of the at least one additional integrated circuit die and spans a second scribe line [annotated fig. 10D] between the first integrated circuit die or the second integrated circuit die and the at least one additional integrated circuit die, and
wherein the second scribe line intersects the scribe line [annotated fig. 10D].
Regarding claim 18, Sharma teaches A method for manufacturing a three-dimensional integrated circuit product, the method comprising:
vertically attaching a jumper die [fig. 10D, bridge die 1064, para 67] to a first die interface [annotated fig. 10D] of a first integrated circuit die [fig. 10D, die 1072, para 67] and a second die interface [annotated fig. 10D] of a second integrated circuit die [fig. 10D, die 1074, para 67],
the first integrated circuit die and the second integrated circuit die being formed using a semiconductor substrate [fig. 10D, package substrate 1062, para 67 & para 34 teaches dies being made within a wafer such as silicon wafer],
the first integrated circuit die being separated from the second integrated circuit die by a scribe line of a first surface of the semiconductor substrate [fig. 10D; scribe lines between dies],
the jumper die spanning the scribe line and overlapping a first portion of the first integrated circuit die (fig. 10D, 1072) and overlapping a second portion of the second integrated circuit die (fig. 10D, 1074).
Regarding claim 19, Sharma teaches The method as recited in claim 18 wherein the first integrated circuit die is adjacent to or diagonally opposite to the second integrated circuit die [fig. 10D].
Regarding claim 23, Sharma teaches The three-dimensional integrated circuit product formed by the method as recited in claim 18 [rejection of claim 18 disclosed above].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2-3 & 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma & Mekking et al. (US 2020/0348587).
Regarding claim 2, Sharma teaches The integrated circuit product as recited in claim 1.
Sharma fails to explicitly disclose wherein the scribe line is an inter-reticle scribe line.
However Mekking teaches wherein the scribe line is an inter-reticle scribe line. [fig. 2; wherein the reticle exposure fields overlap as noted in para 21 and the scribe lines 30 between die become multipurpose zones serving as inter-reticle and intra-reticle boundaries.].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the scribe lines to serve as both inter-reticle and intra-reticle scribe lines for seamless stitching and enable a larger functional multi-chip assembly.
Regarding claim 3, Sharma teaches The integrated circuit product as recited in claim 1.
Sharma fails to explicitly disclose wherein the scribe line is an intra-reticle scribe line.
However Mekking teaches wherein the scribe line is an inter-reticle scribe line. [fig. 2; wherein the reticle exposure fields overlap as noted in para 21 and the scribe lines 30 between die become multipurpose zones serving as inter-reticle and intra-reticle boundaries.].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the scribe lines to serve as both inter-reticle and intra-reticle scribe lines for seamless stitching and enable a larger functional multi-chip assembly.
Regarding claim 20, Sharma teaches The method as recited in claim 18 further comprising:
manufacturing the first integrated circuit die [fig. 10D, die 1072, para 67] and the second integrated circuit die [fig. 10D, die 1074, para 67] using a first semiconductor substrate [fig. 10D, package substrate 1062, para 67 & para 34 teaches dies being made within a wafer such as silicon wafer].
Sharma fails to explicitly disclose an image of a reticle,
wherein the scribe line is an intra-reticle scribe line and
the first integrated circuit die and the second integrated circuit die correspond to different locations within the image of the reticle.
However Mekking teaches an image of a reticle [fig. 2, reticle exposure fields 70, para 20],
wherein the scribe line [fig. 2, scribe lines 30, para 19] is an intra-reticle scribe line [fig. 2 ; wherein scribe lines are the intra-reticle] and
the first integrated circuit die and the second integrated circuit die correspond to different locations within the image of the reticle [fig. 2; wherein the dies 22 correspond to different locations within the reticle exposure field 70].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the scribe lines to serve as both inter-reticle scribe lines for seamless stitching and to enable a larger functional multi-chip assembly.
Claim(s) 5 & 7 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma.
Regarding claim 5, Sharma teaches The integrated circuit product as recited in claim 1
wherein the jumper die comprises:
a first jumper die interface corresponding to the first die interface [fig. 10D, interface where bridge die 1064 and die 1072 couple];
a second jumper die interface corresponding to the second die interface [fig. 10D; interface where bridge die 1064 and die 1074 couple];
Sharma fig 10 fails to explicitly disclose a lateral interconnect structure coupled between the first jumper die interface and the second jumper die interface.
However Sharma teaches in fig. 9 a lateral interconnect structure [ solder structures 924, para 59] coupled between the first jumper die interface [fig. 9, interface between bridge die 904 and die 930] and the second jumper die interface [fig. 9, interface between bridge die 904 and die 934].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for a lateral interconnect structure between the first jumper die interface and second jumper die interface to provide a sufficient connection between the integrated circuit dies and the jumper die for enhanced reliability.
Regarding claim 7, Sharma teaches The integrated circuit product as recited in claim 1.
Sharma fails to explicitly disclose in fig. 10D wherein the first integrated circuit die is disposed diagonally opposite to the second integrated circuit die.
However, Sharma teaches in fig. 10C wherein the first integrated circuit die [die 1048, para 66] is disposed diagonally opposite to the second integrated circuit die [die 1050, para 66].
Claim(s) 6 & 21 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma and further in view of Wang et al. (US 2014/0038360) [Hereinafter Wang].
Regarding claim 6, Sharma teaches The integrated circuit product as recited in claim 1.
Sharma fig. 10 fails to explicitly disclose wherein a first conductive pad of a front side of the jumper die is connected to a corresponding conductive pad of a front side of the first integrated circuit die vertically with respect the front side of the first integrated circuit die and the front side of the jumper die using a microbump or a hybrid bond.
However, Sharma fig. 9 teaches wherein a first conductive pad [bridge pad 922, para 59] of a front side of the jumper die [bridge die 904, para 59] is connected to a corresponding conductive pad of a front side of the first integrated circuit die [die pads 932B, para 59] vertically with respect the front side of the first integrated circuit die [die 930] and the front side of the jumper die [die 904] using a solder structure [solder structure 924].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the bridge die and IC dies to be coupled by bridge pads and solder structures to enable chips to communicate with high bandwidth while reducing manufacturing costs.
Sharma fails to explicitly to disclose the solder features as microbumps or a hybrid bond.
However Wang teaches para 26, “microbumps 17 may be formed of solder including lead based solder or lead free solder”.
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the microbumps to comprise solder structures to form highly dense interconnections ensuring reliable thermal and electrical performance.
Regarding claim 21, Sharma teaches The method as recited in claim 18 wherein vertically attaching comprises:
connecting vertically with respect a front side of the first integrated circuit die and a front side of the jumper die,
a first conductive pad [fig. 9, pad 922, para 59] of the front side of the jumper die to a corresponding conductive pad of the front side of the first integrated circuit die [fig. 9, pad 932B, para 59],
using a solder structure [solder structure 924].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the bridge die and IC dies to be coupled by bridge pads and solder structures to enable chips to communicate with high bandwidth while reducing manufacturing costs.
Sharma fails to explicitly to disclose the solder features as microbumps or a hybrid bond.
However Wang teaches para 26, “microbumps 17 may be formed of solder including lead based solder or lead free solder”.
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the microbumps to comprise solder structures to form highly dense interconnections ensuring reliable thermal and electrical performance.
Claim(s) 9-12 & 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma & Yu et al. (US 2022/0223530) [Hereinafter Yu].
Regarding claim 9, Sharma teaches An integrated circuit product comprising:
a jumper die [fig. 9, bridge die 904, para 59] comprising:
a first jumper die interface [fig. 9; interface between bridge die 904 and die 930];
a second jumper die interface [fig. 9; interface between bridge die 904 and die 934];
Sharma fails to explicitly disclose a lateral interconnect structure coupled between the first jumper die interface and the second jumper die interface.
However Yu teaches a lateral interconnect structure [fig. 25, electrical paths 36, para 32 coupled between the first jumper die interface and the second jumper die interface [wherein the interface between the bridge die BD and the logic dies LD equates to the first and second die interface].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for a lateral interconnect structure in a bridge die to enable high bandwidth die to die communication in a cost effective way.
Regarding claim 10, Sharma/Yu teaches The integrated circuit product as recited in claim 9
wherein the jumper die (fig. 9, 904) is configured to transmit a signal [fig. 9; wherein the jumper die is electrically coupled to each die and thereby enabled to transmit electrical signals] received from a first integrated circuit die [fig. 9, die 930, para 59] via the first jumper die interface [fig. 9; interface between bridge die 904 and die 930] to a second integrated circuit die [fig. 9, die 934, para 59] via the second jumper die interface [fig. 9; interface between bridge die 904 and die 934] across a scribe line [fig. 9, trench 942, para 60] of a semiconductor substrate used to form the first integrated circuit die (fig. 9, 930) and the second integrated circuit die (fig. 9, 934).
Regarding claim 11, Sharma/Yu teaches The integrated circuit product as recited in claim 9 further comprising:
a first integrated circuit die [fig. 10D, die 1072, para 67]; and
a second integrated circuit die [fig. 10D, die 1074, para 67],
the first integrated circuit die and the second integrated circuit die being formed using a semiconductor substrate [para 34 teaches dies being made within a wafer such as silicon wafer],
wherein the jumper die [fig. 10D, bridge die 1064, para 67] is stacked with a first corresponding die interface of the first integrated circuit die [annotated fig. 10D] and stacked with a second corresponding die interface of the second integrated circuit die [annotated fig. 10D] and
the jumper die (fig. 10D, 1064) spans a scribe line of a first surface of the semiconductor substrate [annotated fig. 10D].
Regarding claim 12, Sharma/Yu teaches The integrated circuit product as recited in claim 11 further comprising:
an additional die [fig. 10D, die 1068, para 67] stacked with the first integrated circuit die or the second integrated circuit die,
the additional die (fig. 10D, 1068) being laterally adjacent to the jumper die (fig. 10D, 1064) with respect to the first surface of the semiconductor substrate (fig. 10D, 1062),
wherein a space between the jumper die and the additional die has the same width as the scribe line [fig. 10D; wherein the space (scribe line) between each die and the bridge die are the same].
Regarding claim 15, Sharma/Yu teaches The integrated circuit product as recited in claim 9
wherein the lateral interconnect structure is passive interconnect [solder structures 924, para 59].
Regarding claim 16, Sharma/Yu teaches The integrated circuit product as recited in claim 9
wherein the first jumper die interface is disposed at a first edge of the jumper die [Sharma, annotated fig. 9] and
the second jumper die interface is disposed at a second edge of the jumper die [Sharma, annotated fig. 9].
Regarding claim 17, Sharma/Yu teaches The integrated circuit product as recited in claim 9
wherein the first jumper die interface is disposed at a first corner of the jumper die [Sharma, annotated fig. 9] and
the second jumper die interface is disposed at a second corner of the jumper die [Sharma, annotated fig. 9].
Claim(s) 13 is rejected under 35 U.S.C. 103 as being unpatentable over Sharma, Yu, & Wang.
Regarding claim 13, Sharma/Yu teaches The integrated circuit product as recited in claim 11.
Sharma fig. 10 fails to explicitly disclose wherein the first jumper die interface includes a first conductive pad of a front side of the jumper die,
the first conductive pad being connected to a corresponding conductive pad of a front side of the first integrated circuit die vertically with respect the front side of the first integrated circuit die using a microbump or a hybrid bond.
However, Sharma fig. 9 teaches wherein the first jumper die interface includes a first conductive pad of a front side of the jumper die [bridge pad 922, para 59],
the first conductive pad being connected to a corresponding conductive pad of a front side of the first integrated circuit die [die pads 932B, para 59] vertically with respect the front side of the first integrated circuit die using a solder structure [solder structure 924].
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the bridge die and IC dies to be coupled by bridge pads and solder structures to enable chips to communicate with high bandwidth while reducing manufacturing costs.
Sharma/Yu fails to explicitly to disclose the solder features as microbumps or a hybrid bond.
However Wang teaches para 26, “microbumps 17 may be formed of solder including lead based solder or lead free solder”.
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the microbumps to comprise solder structures to form highly dense interconnections ensuring reliable thermal and electrical performance.
Allowable Subject Matter
Claim 22 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 22, Sharma teaches The method as recited in claim 18 further comprising:
The prior art of record fails to explicitly disclose vertically attaching an additional die to an additional die interface of the first integrated circuit die,
the additional die being separated from the jumper die by a space having the same width as the scribe line and being laterally adjacent to the jumper die with respect to the first surface of the semiconductor substrate.
Thereby claim 22 contains allowable subject matter would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FELIX B ANDREWS whose telephone number is (703)756-1074. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FELIX B ANDREWS/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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