Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,038,463 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because
Claim 1 of Instant application
Claim 1 of US Patent 12,038,463 B2
A system for determining impedances of a plurality of devices under test (DUT), the system comprising:
A system for determining impedances of a plurality of devices under test (DUT), the system comprising:
a fast Fourier transform (FFT) processor configured to convert first voltage related data corresponding to a DUT into a second voltage related data using a fast Fourier transform; and
a fast Fourier transform (FFT) processor coupled to the plurality of measurement circuits, wherein the FFT processor is configured to convert each first voltage related data into a respective second voltage related data using a fast Fourier transform; and
a controller coupled to the FFT processor, wherein the controller is configured to calculate an impedance of each DUT using the respective second voltage related data
a controller coupled to the plurality of measurement circuits and the FFT processor, wherein the controller is configured to calculate an impedance of each DUT using the respective second voltage related data
Similarly Claims 8 and 15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8 and 15 of U.S. Patent No. 12,038,463 B2 respectively. Although the claims at issue are not identical, they are not patentably distinct from each other.
Similarly Claims 1, 8 and 15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 8 and 15 of U.S. Patent No. 11,740,272 B2. Although the claims at issue are not identical, they are not patentably distinct from each other.
Claim Rejections - 35 USC § 112
7. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites the limitation "the power mesh" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 101
9. 35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
10. Claims 1-2, 6, 8-9, 13, 15-16 and 19 are rejected under 35 U.S.C. 101 because the claimed invention s directed to an abstract idea without significantly more. The claim(s) recite(s):
As to claims 1, 8 and 15,
Claim 1 is rejected under 35 U.S.C. 101 because:
STEP 1: claim 1 is directed to system which is an apparatus and one of the 4 statutory categories.
STEP 2A: claim 1 is directed to the abstract idea as follows:
First Prong:
convert first voltage related data corresponding to a DUT into a second voltage related data using a fast Fourier transform; and calculate an impedance of each DUT using the respective second voltage related data (hereinafter mentioned as “Mathematical Calculations”).
(These limitations can be performed by mental steps using mathematical formulas that can also be performed using a general processor)
Second Prong:
The claimed mathematical concept/Calculations above is neither implemented into any practical application (device or thing), nor effect any transformation/reduction of a particular article to a different state or thing.
STEP 2B: The Additional elements “a controller coupled to the FFT processor” in the independent claim 1 could be consider as not significantly more than the abstract idea because such features were routine, conventional, as best understood, For example Pub NO. US 2010/0148751 A1 discloses a controller coupled to the FFT processor (controller 28 is coupled to FFT processor 30 in fig. 8) and US 2017/0254844 A1 discloses a controller coupled to the FFT processor. This claim is therefore directed towards an abstract idea without reciting significantly more, and therefore stands rejected as being directed towards a judicial exception.
13. In Claim 8, this claim recites the same claim features as already addressed in above Claim 1, and thus this claim also raises an issue under 35 U.S.C. 101 for the same reasons.
14. In Claim 15, while this claim is a method claim, this claim recites the same claim features as already addressed in above Claims 1 and 8, and thus this claim also raises an issue under 35 U.S.C. 101 for the same reasons.
15. Claims 2, 9, 16 is rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more. Claims 2, 9, 16 depends on claims 1, 8 and 15 respectively, therefore, it has the abstract idea and also has the routine and conventional structure above said claims.
Furthermore, Claims 2, 9 and 16 includes additional elements “further comprising a plurality of measurement circuits coupled to the plurality of DUTs and the controller, wherein each measurement circuit is configured to generate each first voltage related data” which are/is simply more mathematical calculations, value numbers, insufficient extra solution activity(s), routine and/or conventional structure(s) previously known to the pertinent industry. For example Pub NO. US 2010/0148751 A1 discloses further comprising a plurality of measurement circuits coupled to the plurality of DUTs and the controller, wherein each measurement circuit is configured to generate each first voltage related data.
16. Claim 6, 13, 19 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more. Claim 6, 13, 19 depend on claim 2, 9, 16 and respectively therefore, it has the abstract idea and also has the routine and conventional structure above said claims.
Furthermore, Claim 6, 13, 19 includes additional elements “wherein the controller is further configured to control the measurement circuit such that a frequency of a clock signal generated by each measurement circuit is equal to a first frequency value and a second frequency value at different times, the second frequency value being greater than the first frequency value” that are sufficient to amount to significantly more than the judicial exception because these/this limitation(s) are/is simply routine and conventional structures previously known to the pertinent industry that serve to generate the data to be processed by implementing the idea on a computer, and/or recitation of generic computer structure and also serve to perform generic computer functions that are well-understood routine, and conventional activities previously known to the pertinent industry. For example Pub NO. US 2010/0148751 A1 teaches wherein the controller is further configured to control the measurement circuit such that a frequency of a clock signal generated by each measurement circuit is equal to a first frequency value and a second frequency value at different times, the second frequency value being greater than the first frequency value.
Claim Rejections - 35 USC § 103
17. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
18. Claim(s) 1-2, 6, 8-9, 13, 15-16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over OKAYASU et al. (Pub NO. US 2010/0148751 A1; hereinafter Okayasu) in view of Sestok et al. (Pub NO. US 2017/0254844 A1; hereinafter Sestok).
Regarding Claim 1, Okayasu teaches a system for determining of a plurality of devices under test (DUT) (See the system of Fig. 1 and Fig. 5 and Fig. below), the system comprising:
a fast Fourier transform (FFT) processor (38 in Fig. 5 and Fig. below) configured to convert first voltage related data corresponding to a DUT into a second voltage related data using a fast Fourier transform (38 performs fast Fourier transform of voltage signal 34 and output of 38 is second voltage signal in Fig. 5 and Fig. below; See [0062]); and
a controller coupled to the FFT processor (controller 28 is coupled to 30 in Fig. 8; See [0070]-[0080]), wherein the controller is configured to calculate of each DUT using the respective second voltage related data (42 calculated of each DUT based on output of 38 in Fig. 5 and Fig. below; See [0062]-[0080]).
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Okayasu is silent about calculate an impedance of each DUT using the respective second voltage related data.
Sestok teaches calculate an impedance of each DUT using the respective second voltage related data (See [0009], [0016], [0026]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Okayasu by to calculate an impedance of each DUT using the respective second voltage related data, as taught by Sestok in order to measure the impedance of a circuit element (Sestok; [0003]).
Regarding Claim 2, Okayasu in view of Sestok teaches the system of claim 1. Okayasu further teaches further comprising a plurality of measurement circuits coupled to the plurality of DUTs and the controller (plurality of measurement circuits 24/30 are coupled to DUT’s 20 and controller 28 in Fig. 8), wherein each measurement circuit is configured to generate each first voltage related data (30 generates each voltage data in Fig. 8; See [0045], [0064], [0066]).
Regarding Claim 6, Okayasu in view of Sestok teaches the system of claim 2. Okayasu further teaches wherein the controller is further configured to control the measurement circuit (controller 28 is controlling clock signals and 30 in Fig. 8; See [0068]-[0075]) such that a frequency of a clock signal generated by each measurement circuit is equal to a first frequency value (clock signal frequency T is first frequency value in Fig. 2; See [0047]-[0048]) and a second frequency value at different times (second frequency 2T different from T in Fig. 2; See [0047]-[0048]), the second frequency value being greater than the first frequency value (2T is greater than T due to jitter in fig. 2; See [0047]-[0048]).
Regarding Claim 8, Okayasu teaches an impedance measurement device embedded within a chip (See the system of Fig. 1 and Fig. 5 and Fig. below), the impedance measurement device comprising:
a fast Fourier transform (FFT) processor (38 in Fig. 5 and Fig. below) configured to convert first voltage related data corresponding to a device under test (DUT) into second voltage related data using a fast Fourier transform (38 performs fast Fourier transform of voltage signal 34 and output of 38 is second voltage signal in Fig. 5 and Fig. below; See [0062]); and
a controller coupled to the FFT processor (controller 28 is coupled to 30 in Fig. 8; See [0070]-[0080]), wherein the controller is configured to calculate of the DUT using the second voltage related data (42 calculated of each DUT based on output of 38 in Fig. 5 and Fig. below; See [0062]-[0080]).
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Okayasu is silent about calculate an impedance of each DUT using the respective second voltage related data.
Sestok teaches calculate an impedance of each DUT using the respective second voltage related data (See [0009], [0016], [0026]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Okayasu by to calculate an impedance of each DUT using the respective second voltage related data, as taught by Sestok in order to measure the impedance of a circuit element (Sestok; [0003]).
Regarding Claim 9, Okayasu in view of Sestok teaches the impedance measurement device of claim 8. Okayasu further teaches (controller 28 is controlling clock signals and 30 in Fig. 8; See [0068]-[0075]) wherein the measurement device further comprises a plurality of measurement circuits coupled to the plurality of DUTs and the controller (plurality of measurement circuits 24/30 are coupled to DUT’s 20 and controller 28 in Fig. 8), wherein each measurement circuit is configured to generate each first voltage related data (30 generates each voltage data in Fig. 8; See [0045], [0064], [0066]).
Regarding Claim 13, Okayasu in view of Sestok teaches the impedance measurement device of claim 9. Okayasu further teaches wherein the controller is further configured to control the measurement circuit (controller 28 is controlling clock signals and 30 in Fig. 8; See [0068]-[0075]) such that a frequency of a clock signal generated by the measurement circuit is equal to a first frequency value (clock signal frequency T is first frequency value in Fig. 2; See [0047]-[0048]) and a second frequency value at different times (second frequency 2T different from T in Fig. 2; See [0047]-[0048]), the second frequency value being greater than the first frequency value (2T is greater than T due to jitter in fig. 2; See [0047]-[0048]).
Regarding Claim 15, Okayasu teaches a method for determining impedance of a device under test (DUT) using an impedance measurement device embedded within a chip (See the method of Fig. 1 and Fig. 5 and Fig. below), the method comprising:
converting, using a fast Fourier transform (FFT) processor (38 performs fast Fourier transform of voltage signal 34 and output of 38 is second voltage signal in Fig. 5 and Fig. below; See [0062]),
the first voltage related data corresponding to the DUT into second voltage related data using a fast Fourier transform (38 performs fast Fourier transform of voltage signal 34 and output of 38 is second voltage signal in Fig. 5 and Fig. below; See [0062]); and
calculating, using a controller coupled the FFT processor (controller 28 is coupled to 30 in Fig. 8; See [0070]-[0080]), of the DUT using the second voltage related data (42 calculated of each DUT based on output of 38 in Fig. 5 and Fig. below; See [0062]-[0080]).
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Okayasu is silent about calculate an impedance of each DUT using the respective second voltage related data.
Sestok teaches calculate an impedance of each DUT using the respective second voltage related data (See [0009], [0016], [0026]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Okayasu by to calculate an impedance of each DUT using the respective second voltage related data, as taught by Sestok in order to measure the impedance of a circuit element (Sestok; [0003]).
Regarding Claim 16, Okayasu in view of Sestok teaches the method of claim 15. Okayasu further teaches further comprising: generating, using a measurement circuit coupled to the DUT and the controller (plurality of measurement circuits 24/30 are coupled to DUT’s 20 and controller 28 in Fig. 8), first voltage related data for the DUT (30 generates each voltage data in Fig. 8; See [0045], [0064], [0066]).
Regarding Claim 19, Okayasu in view of Sestok teaches the method of claim 16. Okayasu further teaches further comprising controlling, by the controller, the measurement circuit (controller 28 is controlling clock signals and 30 in Fig. 8; See [0068]-[0075]) such that a frequency of a clock signal generated by each measurement circuit is equal to a first frequency value (clock signal frequency T is first frequency value in Fig. 2; See [0047]-[0048]) and a second frequency value at different times (second frequency 2T different from T in Fig. 2; See [0047]-[0048]), the second frequency value being greater than the first frequency value (2T is greater than T due to jitter in fig. 2; See [0047]-[0048]).
19. Claim(s) 10, 12 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Okayasu in view of Sestok further in view of DeLaCruz et al. (Pub NO. US 2018/0331095 A1; hereinafter DeLaCruz).
Regarding Claim 10, Okayasu in view of Sestok teaches the impedance measurement device of claim 9. Okayasu further teaches wherein the DUT configured to be controlled by the first voltage related data (30 generates each voltage data and plurality of measurement circuits 24/30 are coupled to DUT’s 20 and controller 28 in Fig. 8in Fig. 8; See [0045], [0064], [0066]) and a clock generator configured to be controlled by a frequency of a clock signal (controller 28 is controlling clock signals and clock signal is generated by clock generator in Fig. 8; See [0068]-[0075]) generated by the measurement circuit (clock signal frequency T is first frequency value in Fig. 2; See [0047]-[0048]).
Okayasu in view of Sestok is silent about clock tree; and DUT comprises a power mesh.
DeLaCruz teaches clock tree (See [0078]); and DUT comprises a power mesh (See [0078]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Okayasu and Sestok by using clock tree; and DUT comprises a power mesh, as taught by DeLaCruz in order to reduce the higher-level interconnect layers is beneficial as the wiring on these layers often consume more space due to their thicker, wider and coarser arrangements (DeLaCruz; [0013]).
Regarding Claim 12, Okayasu in view of Sestok teaches the impedance measurement device of claim 10. Okayasu in view of Sestok is silent about wherein the measurement circuit is configured to detect a voltage of the power mesh.
DeLaCruz teaches wherein the measurement circuit is configured to detect a voltage of the power mesh (See [0078]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Okayasu and Sestok by using measurement circuit is configured to detect a voltage of the power mesh, as taught by DeLaCruz in order to reduce the higher-level interconnect layers is beneficial as the wiring on these layers often consume more space due to their thicker, wider and coarser arrangements (DeLaCruz; [0013]).
Regarding Claim 17, Okayasu in view of Sestok teaches the method of claim 16. Okayasu further teaches further comprising: controlling, by the first voltage related data, of the DUT (30 generates each voltage data and plurality of measurement circuits 24/30 are coupled to DUT’s 20 and controller 28 in Fig. 8in Fig. 8; See [0045], [0064], [0066]); and controlling, by a frequency of a clock signal (controller 28 is controlling clock signals and clock signal is generated by clock generator in Fig. 8; See [0068]-[0075]) generated by each measurement circuit (clock signal frequency T is first frequency value in Fig. 2; See [0047]-[0048]).
Okayasu in view of Sestok is silent about DUT comprises a power mesh; and clock tree.
DeLaCruz teaches DUT comprises a power mesh (See [0078]); and clock tree (See [0078]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Okayasu and Sestok by using clock tree; and DUT comprises a power mesh, as taught by DeLaCruz in order to reduce the higher-level interconnect layers is beneficial as the wiring on these layers often consume more space due to their thicker, wider and coarser arrangements (DeLaCruz; [0013]).
Allowable Subject Matter
20. Claims 3-5, 7, 11, 14 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
21. Regarding Claim 3, none of the prior art fairly teaches or suggests the system of claim 2, wherein each DUT comprises a power mesh configured to be controlled by the first voltage related data and a clock tree configured to be controlled by a frequency of a clock signal generated by each measurement circuit.
Claims 4-5 depend on claim 3, therefore claims 4-5 also have allowable subject matter.
22. Regarding Claim 7, none of the prior art fairly teaches or suggests the system of claim 6, wherein the controller is further configured to control each measurement circuit such that the frequency of the clock signal switches between zero and the second frequency value at a switching frequency of a third frequency value, the third frequency value being greater than the first frequency value and smaller than the second frequency value.
23. Regarding Claim 11, none of the prior art fairly teaches or suggests the impedance measurement device of claim 10, wherein the FFT processor is further configured to convert first current related data that corresponds to current of the power mesh into second current related data, and the controller is further configured to calculate a current amplitude using the second current related data.
24. Regarding Claim 14, none of the prior art fairly teaches or suggests the impedance measurement device of claim 13, wherein the controller is further configured to control the measurement circuit such that the frequency of the clock signal switches between zero and the second frequency value at a switching frequency of a third frequency value, the third frequency value being greater than the first frequency value and smaller than the second frequency value.
25. Regarding Claim 20, none of the prior art fairly teaches or suggests the impedance measurement device of claim 19, further comprising controlling, by the controller, the measurement circuit such that the frequency of the clock signal switches between zero and the second frequency value at a switching frequency of a third frequency value, the third frequency value being greater than the first frequency value and smaller than the second frequency value.
26. Claim 18 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
27. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
a. NAKAMURA et al. (Pub NO. US 2020/0271717 A1) discloses Multiple Output Isolated Power Supply for Test Equipment.
b. YANG et al. (Pub NO. US 2018/0164349 A1) discloses Peak Current Evaluation System.
c. Peng et al. (Pub NO. US 2018/0031627 A1) discloses Time to Current Converter.
28. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZANNATUL FERDOUS whose telephone number is (571)270-0399. The examiner can normally be reached Monday through Friday 8am to 5pm (PST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rodak Lee can be reached at 571-270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZANNATUL FERDOUS/Examiner, Art Unit 2858
/LEE E RODAK/Supervisory Patent Examiner, Art Unit 2858