DETAILED ACTION
This Office Action is in response to an application that was filed on 06/25/2024. Claims 1-20 are presented for examination consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 5, and 10 are rejected under 35 U.S.C. 103 as b being unpatentable over Furutani (US20230171884A1 and Furutani hereinafter), in view of Datta et al. (US 5,486,282 and Datta hereinafter), and in further view of Sumino (US20150200033A1 and Sumino hereinafter) and Czubatyj et al. (US20080035907A1 and Czubatyj hereinafter).
Regarding claim 1, Furutani discloses a printed wiring board (item 1 of Fig. 1 and ¶[0020-0023_0033_0040-0042_0044_0046 & 0061] shows and indicates printed wiring board 1 {wiring substrate 1}) comprising: a first resin insulating layer (item 40 of Fig. 2B & item 401 of Fig. 2C & Fig. 1 and ¶[0022_0024_0034-0035_0052-0054 & 0061] shows and indicates first resin insulating layer 40_401 {resin insulating layer structure formed by interlayer insulating layer 40 and insulating layer 401}); a first conductor layer formed on the first resin insulating layer (item 41 of Fig. 2B & Fig. 1 and ¶[0021_0024_0027_0029_0031-0033 & 0051-0052] shows and indicates first conductor layer 41 {fourth conductor layer 41} formed on first resin insulating layer 40_401); a second resin insulating layer formed on the first conductor layer (item 23 of Fig. 2B & item 101 of Fig. 2C & Fig. 1 and ¶[0022_0024_0034-0035_0052-0056 & 0061] shows and indicates second resin insulating layer 23_101 {resin insulating layer structure formed by second interlayer insulating layer 23 and first insulating layer 101} formed on first conductor layer 41); a second conductor layer formed on the second resin insulating layer (item 31 of Fig. 2B & Fig. 1 and ¶[0021_0024_0027_0029_0031-0033 & 0051-0052] shows and indicates second conductor layer 31 {third conductor layer 31} formed on second resin insulating layer 23_101); and a via conductor formed in the second resin insulating layer such that the via conductor is connecting the first conductor layer and the second conductor layer (item 44 of Fig. 2B & Fig. 1 and ¶[0024_0027_0033_0043-0044 & 0052-0053] shows and indicates via conductor 44 {fourth via conductors 44} formed in second resin insulating layer 23_101 such that via conductor 44 is connecting first conductor layer 41 and t second conductor layer 31), wherein the second conductor layer includes a seed layer formed on the second resin insulating layer and an electrolytic plating film on the seed layer (items 111, 112 of Fig. 2G & Fig. 1 and ¶[0036 & 0056-0059] shows and indicates where second conductor layer 31 includes seed layer 111 {metal seed layer 111} formed on second resin insulating layer 23_101 and an electrolytic plating film 112 {electrolytic plating film layer 112} on seed layer 111).
Furutani discloses the claimed invention except to disclose wherein the seed layer includes a first film formed in connecting with the resin insulating layer and a second film formed on the first film, and the seed layer in the conductor layer is formed such that the first film includes an alloy comprising copper, titanium and impurities including carbon, oxygen, and silicon and that the second film includes copper.
Datta discloses wherein the seed layer includes a first film formed in connecting with the resin insulating layer and a second film formed on the first film, and the seed layer in the conductor layer is formed such that the first film includes an alloy comprising titanium and that the second film includes copper (items 2, 4, 6, S, 8 of Fig. 3 and 6:23-60 & 6:66-67 & 7:1-8 shown and indicates where seed layer 2_4_6 {seed layers 2, 4, 6} includes first film 2 formed in connecting with resin insulating layer S {wafer surface S formed of a substrate that is comprised of polyimide, silicon, quartz, or ceramic} and second film 4_6 formed on the first film 2; and where seed layer 2_4_6 in conductor layer 8 {solder ball 8 composed of lead and tin} is formed such that first film 2 includes an alloy comprising titanium and that second film 4_6 includes copper; therefore, Furutani will have a printed wiring board with seed layer that includes a first film formed in connecting with the second resin insulating layer and a second film formed on the first film, and the seed layer in the second conductor layer that is formed such that the first film includes an alloy comprising titanium and that the second film includes copper by incorporating the structure of Datta).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the seed layer includes a first film formed in connecting with the resin insulating layer and a second film formed on the first film, and the seed layer in the conductor layer is formed such that the first film includes an alloy comprising titanium and that the second film includes copper into the structure of Furutani. One would have been motivated in the printed wiring board of Furutani and have the seed layer include the first film formed connecting with the resin insulating layer and the second film formed on the first film, and where the seed layer in the conductor layer is formed such that the first film includes an alloy that is comprised of titanium and that the second film includes copper, in order to have the seed layer structure have a barrier/adhesion film and a conductive base film while distributing thermal and mechanical stresses over a wide area, as indicated by Datta in 1:66-67, 6:42-43, and 6:56-58, in the printed wiring board of Furutani.
However, Furutani and Datta do not disclose an alloy comprising copper, titanium and impurities including carbon, oxygen, and silicon.
Sumino discloses an alloy comprising copper, titanium and impurities including carbon and oxygen (abstract and ¶[0026] indicates an alloy comprising copper, titanium {Cu--Cr--Ti--Si alloy for electric and electronic parts} and impurities including carbon and oxygen {inevitable impurities such as S, O, and C that form compounds such as sulfides, oxides, carbides, and composite compound thereof}).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate an alloy comprising copper, titanium and impurities including carbon and oxygen into the structure of modified Furutani. One would have been motivated in the printed wiring board of modified Furutani and have the alloy be comprised of copper, titanium and impurities that include carbon and oxygen, in order to have the alloy that can improve stress relaxation resistance characteristic in the PCB, as indicated by Sumino in the abstract, in the printed wiring board of modified Furutani.
However, Furutani, Datta, and Sumino do not disclose a silicon in sulfides.
Czubatyj discloses a silicon in sulfides (¶[0057] indicates a silicon in sulfides {sulfides include silicon sulfide such as SiS2}; therefore, modified Furutani will have the seed layer such that the seed layer includes a first film formed in connecting with the second resin insulating layer and a second film formed on the first film, and the seed layer in the second conductor layer is formed such that the first film includes an alloy comprising copper, titanium and impurities including carbon, oxygen, and silicon and that the second film includes copper by incorporating the indicated structures of Datta, Sumino, and Czubatyj).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a silicon in sulfides into the structure of modified Furutani. One would have been motivated in the printed wiring board of modified Furutani and have the silicon in sulfides, in order to identified sulfur base compounds, as indicated by Czubatyj in ¶[0057], in the printed wiring board of modified Furutani.
Regarding claim 2, modified Furutani discloses a printed wiring board, wherein the seed layer in the second conductor layer is formed such that the first film and the second film are formed by sputtering (Datta: Fig. 3 and 6:38-40 shown indicates where seed layer 2_4_6 in conductor layer 8 is formed such that first film 2 and second film 4_6 are formed by sputtering; Furutani: Figs. 1_2B and ¶[0021_0024_0027_0029_0031-0033 & 0051-0052] shows and indicates second conductor layer 31).
Regarding claim 5, modified Furutani discloses a printed wiring board, wherein the second resin insulating layer includes glass particles (Furutani: Fig. 1_2B-2C and ¶[0035 & 0062-0063] is interpreted to indicate that second resin insulating layer 23_101 includes glass particles {fibers}).
Regarding claim 10, see the rejection of claim 5.
Allowable Subject Matter
Claims 3-4, 6-9, and 11-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 3 and 8, the primary reason for allowance is due to a printed wiring board, wherein the seed layer in the second conductor layer is formed such that the first film has a thickness in a range of 10 nm to 500 nm and that the second film has a thickness in a range of 100 nm to 500 nm.
Regarding claims 4 and 9, the primary reason for allowance is due to a printed wiring board, wherein the seed layer in the second conductor layer is formed such that the alloy of the first film has a content of the carbon is in a range of 0.05 at % to 25 at %, a content of the oxygen in a range of 0.05 at % to 25 at %, a content of the silicon in a range of 0.05 at % to 3 at %, a content of the copper in a range of 50 at % to 90 at %, and a content of the titanium in a range of 1 at % to 30 at %.
Regarding claims 6 and 11, the primary reason for allowance is due to a printed wiring board, wherein the second resin insulating layer includes carbon, oxygen and silicon.
Regarding claims 7, 12, and 20, the primary reason for allowance is due to a printed wiring board, wherein the second conductor layer includes a plurality of conductor circuits including a smallest conductor circuit having a smallest width in a range of 1.5 μm to 5 μm.
Regarding claims 13, 14, and 16, the primary reason for allowance is due to dependency on claim 3.
Regarding claim 15, the primary reason for allowance is due to dependency on claim 14.
Regarding claims 17 and 19, the primary reason for allowance is due to dependency on claim 4.
Regarding claim 18, the primary reason for allowance is due to dependency on claim 17.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUILLERMO J EGOAVIL whose telephone number is (571)270-1325. The examiner can normally be reached Mon-Fri 8:00-5:00.
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/GUILLERMO J EGOAVIL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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