Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Attorney Docket Number: 16RO0860US04/50649-02135
Filling Date: 06/25/24
Priority Date: 07/16/18
Inventor: Delalleau et al
Examiner: Bilkis Jahan
DETAILED ACTION
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chow et al (US 2005/0161748 A1).
Regarding claim 1, Chow discloses a method for forming a dummy contact for an integrated circuit (Fig. 3, Paras. 39-40), comprising: forming an insulating layer 28 (Para. 39) covering a top surface of a semiconductor substrate region 10 (Para. 40); forming a silicide layer 26-2 on top of the insulating layer 28 to mimic a silicided portion 26-2 of the semiconductor substrate region 10; and forming a dielectric layer 29 over the silicide layer 26-2; and forming an electrical contact 30, 31 passing through the dielectric layer 29 to make electrical contact with the silicide layer 26-2.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Chow et al (US 2005/0161748 A1) in view of Matsui (US 2007/0023832 A1).
Regarding claim 2, Chow does not explicitly disclose the method of claim 1, further comprising forming a transistor device including a source region provided by said semiconductor substrate region.
However, Matsui discloses forming a transistor device including a source region 114a (Fig. 2, Para. 77) provided by said semiconductor substrate region 160, 162 (Paras. 70, 71).
Matsui teaches the above modification is used to improve current leakage of the device (Para. 52). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to combine Chow structure with Matsui structure as suggested above to improve current leakage of the device (Para. 52).
Regarding claim 3, Matsui further discloses the method of claim 2, wherein the insulating layer 164 (Para. 76) is in direct contact with the source region 163a (Para. 75) and the silicide layer 163b is in direct contact with the insulating layer 164.
Regarding claim 4, Matsui discloses the method of claim 1, further comprising forming a transistor device including a drain region 163b, 114b (Para. 62) provided by said semiconductor substrate region 160, 162 (Paras. 70-71).
Regarding claim 5, Matsui discloses the method of claim 4, wherein the insulating layer 164 is in direct contact with the drain region 163b, 114b and the silicide layer 163b is in direct contact with the insulating layer 164.
Regarding claim 6, Matsui discloses the method of claim 1, wherein the silicide layer 163b completely covers the insulating layer 164 from being viewed through the dielectric layer 164 (Y-direction view).
Allowable Subject Matter
Claims 7-13 are allowed.
Conclusion
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BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817
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