Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Attorney Docket Number: 1145.272
Filling Date: 06/25/24
Priority Date: 02/26/24
Inventor: Song et al
Examiner: Bilkis Jahan
DETAILED ACTION
1. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
3. Claim(s) 1-3, 8 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Obradovic et al (US 2016/0163796 A1).
Regarding claim 1, Obradovic discloses a semiconductor device (Fig. 4) comprising: a 1st transistor 420 (Fig. 4, Para. 67, left) comprising a 1st channel structure extended in a 1st direction (Y-direction), and a 1st gate structure 460 (Para. 66) on the 1st channel structure 420; a 2nd transistor comprising a 2nd channel structure 420 (right) extended in the 1st direction (Y-direction), and a 2nd gate structure 460 (right) on the 2nd channel structure 420, the 2nd transistor 420 (right) being disposed adjacent to the 1s transistor 420 (left) in a 2nd direction (X-direction) that intersects the 1" direction (Y-direction); a 1" isolation wall 470 (Para. 67) between the 1" channel structure 420 (left) and the 2nd channel structure 420 (right); and a 1" gate cut structure 480 (Para. 86), between the 1" gate structure 460 (left) and the 2nd gate structure 460 (right), on the 1" isolation wall 470 in a 3rd direction (Z-direction) that intersects the 1" direction (Y-direction) and the 2nd direction (X-direction).
Regarding claim 2, Obradovic discloses the semiconductor device of claim 1, wherein a width of the 1" gate cut structure 480 is greater than a width of the 1" isolation wall 470 in the 2nd direction (X-direction).
Regarding claim 3, Obradovic discloses the semiconductor device of claim 2, wherein the 1st gate structure 420 (left) comprises a 1st work-function metal layer 460 (left) on the 1" channel structure 420 (left) and a 1" gate electrode 490 (Para. 89) on the 1" work-function metal layer 460, and the 2nd gate structure comprises a 2nd work-function metal layer 460 (right) on the 2nd channel structure 420 (right) and a 2nd gate electrode 490 on the 2nd work-function metal layer 460 (right), and wherein the 1" gate cut structure 480 contacts the 1" isolation wall 470 and at least one of the 1" work-function metal layer 460 (left) and the 2nd work-function metal layer 460 (right).
Regarding claim 8, Obradovic discloses the semiconductor device of claim 1, wherein each of the 1st channel structure 420 (left) and the 2nd channel structure 420 (right) comprises a plurality of channel layers 420 arranged on a substrate 410 (Para. 64) in the 3rd direction (Fig. 4).
Regarding claim 14, Obradovic discloses a semiconductor device (Fig. 4) comprising: a 1" transistor 420 (left) comprising a 1" channel structure 420 (left) extended in a 1" direction (Y-direction), and a 1" gate structure 490 on the 1" channel structure 420 (left); a 2nd transistor 420 (right) comprising a 2nd channel structure 420 extended in the 1" direction (Y-direction), and a 2nd gate structure 490 on the 2nd channel structure 420 (right), the 2nd transistor 420 (right) being disposed adjacent to the 1" transistor 420 (left) in a 2nd direction (X-direction) that intersects the 1" direction (Y-direction); a 1" isolation wall 470 between the 1" channel structure 420 (left) and the 2nd channel structure 420 (right); and a 1" gate cut structure 480 between the 1" gate structure 460 and the 2nd gate structure 460 (right) on the 1" isolation wall 470 in a 3rd direction (Z-direction) that intersects the 1" direction (Y-direction) and the 2nd direction (X-direction), wherein the 1" gate structure 490 comprises a 1" work-function metal layer 460 (left) on the 1" channel structure 420 (left) and a 1" gate electrode 490 on the 1" work-function metal layer 460, and the 2nd gate structure comprises a 2nd work-function metal layer 460 (right) on the 2nd channel structure 420 (right) and a 2nd gate electrode 490 (right portion) on the 2nd work-function metal layer 460 (right), and wherein the 1" gate cut structure 480 contacts the 1" isolation wall 470 and at least one of the 1" work-function metal layer 460 and the 2nd work-function metal layer.
Allowable Subject Matter
4. Claims 4-7, 9-13 and 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
5. Claims 17-19 and 20 are allowed.
6. The following is an examiner’s statement of reasons for allowance:
7. The applied prior arts neither anticipate nor render the claimed subject matter obvious because they fail to teach the claimed semiconductor device comprising: a 2nd gate cut structure between the 2nd gate structure and the 3rd gate structure, wherein the 2nd gate cut structure has a greater height than the 1" gate cut structure in a direction in which the Is isolation wall is connected to the 1s gate cut structure in combination with all other limitations as recited in claim 17.
8. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BILKIS JAHAN whose telephone number is (571)270-5022. The examiner can normally be reached Monday-Friday, 8:00 am-5 Pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon T Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817
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