DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 05/28/2025.
Claims 1-20 are pending in this application.
Acknowledges
2. Receipt is acknowledged of the following items from the Applicant.
Information Disclosure Statement (IDS) filed on 06/25/2024. The references cited on the PTOL 1449 form have been considered.
Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609.
Foreign Priority
3. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been placed of record in the file.
Specification
4. The specification has been checked to the extent necessary to determine the presence of possible minor errors. However, the applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1-5, 7-9, 13-14, and 17-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lin (US 2025/0132191)
Regarding claim 1, Lin discloses a semiconductor device, comprising:
a substrate 20 (see Figs. 21, 33A-B, and Fig. 4) including active regions 20’ extending in a first direction (Fig. 3, or in the X-direction, laterally extending from front to back in Fig. 21);
a device isolation layer 26 on the substrate 20 and defining the active regions 20’;
gate structures 70A on the substrate, the gate structures intersecting the active regions 20’ and extending in a second direction (Fig. 4, or Y-direction, extending left to right in Fig. 21);
a plurality of channel layers 22B on the active regions 22B and surrounded by the gate structures 70A, the plurality of channel layers 22B being spaced apart from each other in a third direction (Z-direction, extending vertically), the third direction perpendicular to an upper surface of the substrate 20; and
source/drain regions 48 in recessed regions 42 (Fig. 6B) of the active regions on both sides of the gate structures, the source/drain regions 42 being connected to the plurality of channel layers 22B, wherein
a first region of the substrate 20 (region of the substrate 20 directly and vertically underneath dielectric isolation layer 110B, Fig. 21) is spaced apart from first ends of the gate structures 70A in the second direction by a first length in the second direction,
a second region of the substrate (region of the substrate 20 directly underneath the right portion, with respect to isolation region 110, of the middle and wider device isolation layer 26 in Fig. 21) is spaced apart from the first ends of the gate structures by a second length in the second direction,
the second length is longer than the first length (the second region can be easily selected to be longer than the first region),
an upper surface of the device isolation layer 26 on the first region of the substrate has recessed portions (in which the isolation region 110 is formed), and
the device isolation layer 26 on the second region of the substrate has a flat upper surface (in contact to bottom surface of gate structures 70B). See also para. 0063.
Regarding claim 2, Lin discloses the semiconductor device of claim 1, wherein the upper surface of the device isolation layer 26 on the first region has protrusions 26 between the recessed portions (in which lower portions of isolation region 112 is located, Fig. 33A), and a number of the protrusions is identical to a number of gate structures.
Regarding claim 3, Lin discloses the semiconductor device of claim 2, wherein the protrusions extend from the first ends of the gate structures. See Fig. 33A.
Regarding claim 4, Lin discloses the semiconductor device of claim 3, wherein the protrusions extend from the first ends of the gate structures in a direction inclined with respect to the second direction. See Fig. 33A.
Regarding claim 5, Lin discloses the semiconductor device of claim 1, wherein the upper surface of the device isolation layer in the recessed portions on the first region is a same level as the upper surface of the device isolation layer on the second region. See Fig. 21, and Fig. 33A.
Regarding claim 7, Lin discloses the semiconductor device of claim 1, wherein a first active region among the active regions is closest to the first ends of the gate structures, an upper surface of the first active region has a step portion between the gate structures. See Fig. 7B: the step is formed between a topmost surface of the substrate 20 on which a bottom layer 22A is located and a bottom surface of the recess 42. Layer(s) 22A is/are later removed to form gate structure 68 shown in Figs. 13A, 13B.
Regarding claim 8, Lin discloses the semiconductor device of claim 7, wherein the upper surface of the first active region comprises an end region and an inner region sequentially disposed in the second direction from the first ends of the gate structures, the upper surface of the first active region is a second level in the end region and a third level in the inner region, and the third level is lower than the second level. See Figs. 7A/B, 13A/B.
Regarding claim 9, Lin discloses the semiconductor device of claim 7, wherein the first active region has a protruding region protruding upwardly by the step portion, and the protruding region of the first active region is spaced apart from an end of the first active region. See fig. 7B.
Regarding claim 13, Lin discloses a semiconductor device, comprising:
a substrate 20 (see Figs. 21, 33A-B, and Fig. 4) including active regions 20’ extending in a first direction (Fig. 3, or in the X-direction, laterally extending from front to back in Fig. 21);
a device isolation layer 26 defining the active region on the substrate;
a gate structure 70 on the substrate, the gate structure extending in a second direction (Fig. 4, or Y-direction, extending left to right in Fig. 21) and intersecting the active region 20’; and
a source/drain region 48 on at least one side of the gate structure, wherein
a first region of the substrate 20 (region of the substrate 20 proximate to active region 20’ and underneath gate structure 70; see Fig. 32A, Fig. 33A) and a second region of the substrate (on which the middle device isolation 26 having width W3 is located, Fig. 33A) are sequentially disposed in the second direction from a first end of the gate structure in the second direction, and
an upper surface of the device isolation layer 26 on the first region has a protrusion corresponding to the gate structure (underneath the gate structure 70, Fig. 33A), and the device isolation layer on the second region has a flat upper surface (in contact with a bottom surface of isolation region 112).
Regarding claim 14, Lin discloses the semiconductor device of claim 13, wherein a level of the protrusion of the device isolation layer 26 on the first region is higher than a level of the upper surface of the device isolation layer on the second region. See Fig. 33A.
Regarding claim 17, Lin discloses a semiconductor device, comprising:
a substrate 20 (see Figs. 21, 33A-B, and Fig. 4) including active regions 20’ extending in a first direction (Fig. 3, or in the X-direction, laterally extending from front to back in Fig. 21);
a device isolation layer 26 on the substrate 20 and defining the active regions 20’;
gate structures 70A on the substrate, the gate structures intersecting the active regions 20’ and extending in a second direction (Fig. 4, or Y-direction, extending left to right in Fig. 21);
a plurality of channel layers 22B on the active regions 22B and surrounded by the gate structures 70A, the plurality of channel layers 22B being spaced apart from each other in a third direction (Z-direction, extending vertically), the third direction perpendicular to an upper surface of the substrate 20; and
source/drain regions 48 in recessed regions 42 (Fig. 6B) of the active regions at both sides of the gate structures, and the source/drain regions 42 being connected to the plurality of channel layers 22B, wherein
among the active regions 20’, an upper surface of an active region closest to ends of the gate structures in the second direction has a step portion between the gate structures. See Fig. 7B: the step portion is formed between a topmost surface of the substrate 20 on which a bottom layer 22A is located and a bottom surface of the recess 42. Layer(s) 22A is/are later removed to form gate structure 68 shown in Figs. 13A, 13B.
Regarding claim 18, Lin discloses the semiconductor device of claim 17, wherein
a first region of the substrate (region of the substrate 20 proximate to active region 20’ and underneath gate structure 70; see Fig. 32A, Fig. 33A) is adjacent to the ends of the gate structures 70A in the second direction, and
a second region of the substrate (on which the middle device isolation 26 having width W3 is located, Fig. 33A) is spaced apart from the ends of the gate structures in the second direction, and
an upper surface of the device isolation layer 26 on the first region of the substrate has protrusions corresponding to the gate structures (underneath the gate structure 70, Fig. 33A) and recessed portions (filled by isolation region 112) between the protrusions.
Regarding claim 19, Lin discloses the semiconductor device of claim 18, wherein the protrusions in the upper surface of the device isolation layer 26 on the first region of the substrate are on a straight line with the gate structures 70 (fig. 32A) in the second direction, or the protrusions in the upper surface of the device isolation layer on the first region of the substrate are shifted from the straight line in the first direction.
Regarding claim 20, Lin discloses the semiconductor device of claim 18, wherein an upper surface of the device isolation layer 26 on the second region is flat (and in contact with a bottom surface of the isolation region 112). See Fig. 33A.
Claim Rejections - 35 U.S.C. § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claims 6, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2025/0132191)
Regarding claim 6, Lin discloses the semiconductor device of claim 1, comprising all claimed limitations, as discussed above, except for wherein a depth of the recessed portions ranges from 5 nm to 10 nm.
However, as in Fig. 19, and Fig. 27A, the trench 92 may or may not extend through STI region 26. Accordingly, the depth of the recess portions 120 (Fig. 27A) depends on the thickness of insulating layer 26. The thickness of the insulating layer 26 is obviously modifiable to any suitable value. It has been held that a change in the size/thickness generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP §2144.04).
It has been held that where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device, and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (MPEP §2144.04). It would have been obvious that a mere change in size/thickness of a component is generally recognized as being within the level of ordinary skill in the art, or that a change in size/thickness of a component would be an unpatentable modification.
Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art...such ranges are termed "critical ranges and the applicant has the burden of proving such criticality. See In re Aller, 220 F.2d 454, 105 USPQ 233,235 (CCPA 1955).
In addition, there is no persuasive evidence in the instant specification showing that the claimed depth of the recessed portions is significant or bear any critical point/value that would establish patentability. The claimed limitations relating to the depth of the recessed portions are not sufficient to patentable distinguish over the prior art.
See MPEP §2144.04).
Regarding claim 15, Lin discloses the semiconductor device of claim 13 comprising all claimed limitations, as discussed above, except for wherein a length of the first region is 800 nm to 2000 nm in the second direction from the first end of the gate structure.
However, it has been held that where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed element, and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (MPEP §2144.04). It would have been obvious that a mere change in size/length of a component is generally recognized as being within the level of ordinary skill in the art.
It is to be expected that a change in size, thickness would be an unpatentable modification.
Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art...such ranges are termed "critical ranges and the applicant has the burden of proving such criticality. See In re Aller, 220 F.2d 454, 105 USPQ 233,235 (CCPA 1955).
The instant specification contains no disclosure of either the critical nature of the claimed dimensions/length or of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. (.In re Woodruff, 919 F.2d 1575, 1578 (Fed. Cir. 1990).)
The claimed limitation regarding to the length of the first region do/does not bear any critical point that would establish patentability, and is/are not sufficient to patentable distinguish over the prior art, therefore being considered as unpatentable limitation(s) because it would have involve only a mere change in size/thickness of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP §2144.04).
Allowable Subject Matter
9. Claims 10-12, and 16 are allowable.
Claims 10-12, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed semiconductor device (in combination set forth in the claim) comprising:
Claims 10-12:
wherein a third region of the substrate is spaced apart from second ends of the active regions in the first direction by a third length in the first direction, a fourth region of the substrate is spaced apart from the second ends of the active region by a fourth length in the first direction, the fourth length is longer than the third length, and the substrate has recessed portions in an upper surface thereof in the third region, and the substrate has a flat upper surface in the fourth region.
Claim 16:
wherein a third region of the substrate and a fourth region of the substrate are sequentially disposed in the first direction from a second end of the active region in the first direction, and a protrusion in an upper surface of the substrate on the third region corresponds to the active region, and an upper surface of the substrate on the fourth region is flat.
Conclusion
10. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 September 5, 2026
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