DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 6, 13 and 20 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7-12, 14-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tomita (Patent 6324113), hereinafter as Tomita, in view of Sethi et al. (PGPUB 20240203476), hereinafter as Sethi.
Regarding claim 1, Tomita teaches a system for managing dynamic random-access memory (DRAM) self-refresh (col 7, line 2-3), comprising:
to prevent entry into DRAM self-refresh mode while the at least one register indicates DRAM subsystem write activity associated with the DRAM client subsystem (claim 19);
but not expressly polling circuitry configured to detect initiation of DRAM self-refresh mode entry, to poll the at least one register in response to detection of initiation of DRAM self-refresh mode entry, nor one register configured to store at least one indication of DRAM subsystem write activity associated with a DRAM client subsystem;
Sethi teaches polling circuitry configured to detect initiation of DRAM self-refresh mode entry, to poll the at least one register in response to detection of initiation of DRAM self-refresh mode entry, nor one register configured to store at least one indication of DRAM subsystem write activity associated with a DRAM client subsystem ([0031] “a mode register read (MRR) command to a particular mode register…control…the refresh operations, write operations”, and Fig 2, register 230);
Since Sethi and Tomita are both from the same field of semiconductor memory device, the purpose disclosed by Sethi would have been recognized in the pertinent art of Tomita.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use mode register as in Sethi into the device of Tomita for the purpose of managing the different operations of the memory device.
Regarding claim 2, Sethi teaches a register in a self-refresh control subsystem, and the register is configured to receive the indication from the DRAM client subsystem ([0031]).
The reason for combining the references used in rejection of claim 1 applies.
Regarding claim 3, Sethi teaches the register is configured to store a plurality of the indications received from a corresponding plurality of DRAM client subsystems ([0031]),
Tomita teaches to prevent entry into DRAM self-refresh mode while at least one of the plurality of indications indicates DRAM subsystem write activity associated with the DRAM client subsystem (claim 19).
The reason for combining the references used in rejection of claim 1 applies.
Regarding claim 4, Sethi teaches the at least one register comprises a register in the DRAM subsystem, and the register is configured to receive the indication from a DRAM controller of the DRAM subsystem (Fig 2).
The reason for combining the references used in rejection of claim 1 applies.
Regarding claim 5, Sethi teaches a first register in a self-refresh control subsystem, the first register configured to receive a first indication from the DRAM client subsystem; and a second register in the DRAM subsystem, the second register configured to receive a second indication from a DRAM controller of the DRAM subsystem (Fig 2);
Tomita teaches the polling circuitry is configured to prevent entry into DRAM self-refresh mode while at least one of the first register and the second register indicate DRAM subsystem write activity associated with the DRAM client subsystem (claim 19).
The reason for combining the references used in rejection of claim 1 applies.
Regarding claim 7, it is well known in the field that a DRAM subsystem write activity associated with the DRAM client subsystem comprises writing error-correcting code (ECC) metadata or writing data associated with the ECC metadata (e.g. 20240331794 by Suzuki para[0030]).
Regarding claim 8, Tomita teaches a method for managing dynamic random-access memory (DRAM) self-refresh, comprising:
preventing entry into DRAM self-refresh mode while the at least one register indicates DRAM subsystem write activity associated with the DRAM client subsystem (Claim 19);
Sethi teaches storing, by at least one register, at least one indication of DRAM subsystem write activity associated with a DRAM client subsystem (Fig 2); and
detecting, by polling circuitry, initiation of DRAM self-refresh mode entry ([0031]);
polling, by the polling circuitry, the at least one register in response to detection of initiation of DRAM self-refresh mode entry ([0031]).
The reason for combining the references used in rejection of claim 1 applies.
Regarding claim 9 or 16, Sethi argument used in rejection of claim 2 applies.
Regarding claim 10 or 17, Sethi argument used in rejection of claim 3 applies.
Regarding claim 11 or 18, Sethi argument used in rejection of claim 4 applies.
Regarding claim 12 or 19, Sethi argument used in rejection of claim 5 applies.
Regarding claim 14, Sethi argument used in rejection of claim 7 applies.
Regarding claim 15, Sethi teaches a system for managing dynamic random-access memory (DRAM) self-refresh, comprising: means for storing at least one indication of DRAM subsystem write activity associated with a DRAM client subsystem (Fig 2); and means for detecting initiation of DRAM self-refresh mode entry ([0031]); means for polling the means for storing in response to detection of initiation of DRAM self-refresh mode entry ([0031]);
Tomita teaches means for preventing entry into DRAM self-refresh mode while the means for storing indicates DRAM subsystem write activity associated with the DRAM client subsystem (claim 19).
The reason for combining the references used in rejection of claim 1 applies.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6.
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/MIN HUANG/ Primary Examiner, Art Unit 2827