DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 06/25/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Objections
Claim 2 is objected to because of the following informalities:
Claim 2, line 2: “further comprises a second ground patterns” should read --- further comprises second ground patterns ---
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 9-12 and 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mizunashi (U.S. PG Pub No US2002/0139571A1).
Regarding claim 9, Mizunashi teaches a wiring substrate (1A) fig. 8 [0065-0066], comprising:
a body layer (comprising 51, 10, 40) fig. 8 [0066];
a ground pad (surfaces of respective 52 connected with / acting as extensions of ground pattern(s) GP, GND [0067]) (see GND-P annotated fig. 8 below) and signal pads (surfaces of respective 52s connected with / acting as extensions of signal pattern(s) SP, S [0067]) (see SIG-P annotated fig. 8 below) on (directly on) a bottom surface of the body layer (comprising 51, 10, 40) fig. 8 [0066];
a first substrate wiring layer (51 of 50) fig. 8 [0069] in the body layer (comprising 51, 10, 40) fig. 8 [0066]; and
a second substrate wiring layer (40) fig. 8 [0073] in the body layer (comprising 51, 10, 40) and on (supported by) the first substrate wiring layer (51), wherein
the first substrate wiring layer (51) comprises first signal patterns (SP’s in 51) fig. 8 [0067] and a power pattern (13 in 51 connected to Vdd) fig. 8 [0069-0071] (see annotated fig. 8 below),
the power pattern (13 in 51) is placed between the first signal patterns (SP’s in 51), when viewed in a plan view (when the cross sectional view of Fig. 8 of Mizunashi is viewed from the top, i.e., in a plan view, the current limitation are disclosed/anticipated – the claimed components are placed as claimed in both a cross-sectional view, as is explicitly shown in Fig. 8, and what would be shown in corresponding top/plan view),
the power pattern (13 in 51 connected to Vdd) is placed on (supported by) the ground pad (GND-P),
the second substrate wiring layer (40) comprises (hosts) a second signal pattern (SP2 defined as 46 with respective 42 with 44) fig. 8 [0070] (see SP2 in annotated fig. 8 below) (SP2 components patterns electrically connected with / acting as extensions of signal line pattern(s) [0067, 0070]), and
the second signal pattern (SP2) is on (supported by) the power pattern (13 in 51 connected to Vdd) (see annotated fig. 8 below).
[AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: rect][AltContent: textbox (1st signal patterns)][AltContent: arrow][AltContent: textbox (Power pattern)][AltContent: arrow][AltContent: textbox (Ground pattern)][AltContent: textbox (SP2)][AltContent: rect][AltContent: rect][AltContent: arrow][AltContent: arrow][AltContent: textbox (GND-P)][AltContent: arrow][AltContent: textbox (SIG-P’s)][AltContent: arrow]
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Annotated fig. 8 of Mizunashi
Regarding claim 10, Mizunashi teaches the wiring substrate (1A) fig. 8 [0065-0066 of claim 9. Mizunashi also teaches further comprising:
a third substrate wiring layer (11 of 10) fig. 8 [0066] in the body layer (comprising 51, 10, 40) fig. 8 [0066] and (vertically) between the first substrate wiring layer (51) and the second substrate wiring layer (40), wherein
the third substrate wiring layer (11) comprises a first ground pattern (GP in 11) fig. 8 [0067], and
the first ground pattern (GP in 11) fig. 8 [0067] crosses a region (diagonally) between the power pattern (13 in 51 connected to Vdd) fig. 8 [0069-0071] and the second signal pattern (SP2) (see annotated fig. 8 above).
Regarding claim 11, Mizunashi teaches the wiring substrate (1A) fig. 8 [0065-0066 of claim 9. Mizunashi also teaches, wherein
side surfaces (sidewalls) of the power pattern (13 in 51 connected to Vdd) fig. 8 [0069-0071] in a width direction are on (supported by) the ground pad (surfaces of respective 52 connected with / acting as extensions of ground pattern(s) GP, GND [0067]) (see GND-P annotated fig. 8 above).
Regarding claim 12, Mizunashi teaches the wiring substrate (1A) fig. 8 [0065-0066] of claim 9. Mizunashi also teaches wherein
the first substrate wiring layer (51 of 50) fig. 8 [0069] further comprises ground patterns (GP in 51, 55 directly on GP in 51) fig. 8 [0069-0070],
the ground patterns (GP in 51, 55 directly on GP in 51) are (in the space diagonally between) between the power pattern (13 in 51 connected to Vdd) fig. 8 [0069-0071] and the first signal patterns (SP’s in 51 with respective 55’s) fig. 8 [0067, 0069].
Regarding claim 14, Mizunashi teaches the wiring substrate (1A) fig. 8 [0065-0066 of claim 9. Mizunashi also teaches, wherein
the ground pad (see GND-P annotated fig. 8 above) [0067] is (horizontally) between the signal pads (see SIG-P annotated fig. 8 above) [0067], when viewed in the plan view (when the cross sectional view of Fig. 8 of Mizunashi is viewed from the top, i.e., in a plan view, the current limitation are disclosed/anticipated – the claimed components are placed as claimed in both a cross-sectional view, as is explicitly shown in Fig. 8, and what would be shown in corresponding top/plan view).
Regarding claim 15, Mizunashi teaches the wiring substrate (1A) fig. 8 [0065-0066 of claim 9. Mizunashi also teaches wherein at least a portion of the second signal pattern (SP2 defined as 46 with respective 42 with 44) fig. 8 [0070] (see SP2 in annotated fig. 8 above) overlaps the power pattern (13 in 51 connected to Vdd) fig. 8 [0069-0071] (see annotated fig. 8 above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4 and 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Mizunashi (U.S. PG Pub No US2002/0139571A1) in view of Lee (U.S. PG Pub No US2007/0164429A1).
Regarding claim 1, Mizunashi teaches a wiring substrate (1A) fig. 8 [0065-0066], comprising:
a first substrate wiring layer (51 of 50) fig. 8 [0069] including a first insulating pattern (51) fig. 8 [0069] and a power pattern (13 in 51 connected to Vdd) fig. 8 [0069-0071] in the first insulating pattern (51);
a second substrate wiring layer (11 of 10) fig. 8 [0066] on the first substrate wiring layer (51), the second substrate wiring layer (10) including a second insulating pattern (11) fig. 8 [0066] and a first ground pattern (GP in 11) fig. 8 [0067] in the second insulating pattern (11);
a third substrate wiring layer (40) fig. 8 [0073] on the second substrate wiring layer, the third substrate wiring layer (40) including a third insulating pattern (43) fig. 8 [0073] and a first signal pattern (SP1 46 with respective 42) fig. 8 [0070] (see SP1 in annotated fig. 8 below) (SP1 components patterns electrically connected with / acting as extensions of signal line pattern(s) [0067, 0070]) in the third insulating pattern (43); and
a pad layer (53 with 52) fig. 8 [0069] covering a bottom surface of the first substrate wiring layer (51), the pad layer (53 with 52) including a protection layer (53 of 50) fig. 8 [0069] and the pad layer including signal pads (surfaces of respective 52s connected with / acting as extensions of signal pattern(s) SP, S [0067]) (see SIG-P annotated fig. 8 below) of and a ground pad (surfaces of respective 52 connected with / acting as extensions of ground pattern(s) GP, GND [0067]) (see GND-P annotated fig. 8 below) in the protection layer, wherein
the ground pad (GND-P) is (horizontally) between the signal pads (SIG-P’s) (see annotated fig. 8 below),
the first ground pattern (GP in 11) fig. 8 [0067] vertically overlaps the ground pad (GND-P) and the power pattern (13 in 51 connected to Vdd), and
the first signal pattern (SP1) is on (supported by) the first ground pattern (GP in 11).
[AltContent: arrow][AltContent: textbox (Power pattern)][AltContent: arrow][AltContent: textbox (Ground pattern)][AltContent: arrow][AltContent: textbox (SP1)][AltContent: rect][AltContent: rect][AltContent: arrow][AltContent: arrow][AltContent: textbox (GND-P)][AltContent: arrow][AltContent: textbox (SIG-P’s)][AltContent: arrow]
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Annotated fig. 8 of Mizunashi
However, Mizunashi does not explicitly disclose the power pattern (13 connected to Vdd) vertically overlaps the ground pad (GND-P).
Lee teaches a wiring substrate (100) fig. 2 [0041-0042] wherein the power pattern (87PP) fig. 2 [0049] vertically overlaps the ground pad (77GG) fig. 2 [0044].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have horizontally elongated both the power pattern [0049] and the ground pad [0044] of Mizunashi such that the power pattern vertically overlaps the underlying ground pad [0044, 0049] in order to increase the amount of both ground pad and power pattern material [0044-0049] so as to reduce the electrical resistance of internal interconnections formed therefrom [0048], as taught by Lee.
Regarding claim 2, Mizunashi in view of Lee teaches the wiring substrate (1A) fig. 8 [0065-0066] of claim 1. However, the embodiment of fig. 8 of Mizunashi does not explicitly disclose wherein
the first substrate wiring layer (51 of 50) fig. 8 [0069] further comprises second ground patterns,
the power pattern (13 in 51 connected to Vdd) fig. 8 [0069-0071] is between the second ground patterns, and
the second ground patterns are spaced apart from the power pattern (13 connected to Vdd) fig. 8 [0069-0071] with the first insulating pattern (51) fig. 8 [0069] in between (multiple second ground patterns in 51 not explicitly shown).
The embodiment of fig. 3 of Mizunashi discloses wherein:
the first substrate wiring layer (31 of 30) fig. 3 [0043] further comprises second ground patterns (left, right GP in 31) [0044] (see annotated fig. 3 below),
the power pattern (VP in 31) fig. 3 [0044] is between the second ground patterns (left/right GP in 31), and
the second ground patterns (left/right GP in 31) are spaced apart from the power pattern (VP in 31) with the first insulating pattern (31) fig. 3 [0043] in between.
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Annotated fig. 3 of Mizunashi
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the wiring substrate of the embodiment of fig. 8 of Mizunashi such that additional ground pattern(s) are disposed to the left/right of the power pattern [0043-0044], such that the power pattern is horizontally between multiple second ground patterns [0043-0044], in order to guarantee a sufficient number of ground patterns [0044-0045] in the package for high frequency signal transmission applications [0049], as taught by the embodiment of fig. 3 of Mizunashi.
Regarding claim 3, Mizunashi in view of Lee teaches the wiring substrate (1A) fig. 8 [0065-0066] of claim 2. Mizunashi (with reference to the embodiment of fig. 3 of Mizunashi) also teaches wherein
the first substrate wiring layer (31 of 30) fig. 3 [0043] further comprises a second signal pattern (left SP in 31) fig. 3 [0043-0044], and
at least one of the second ground patterns (left GP in 31) fig. 3 [0044] are (horizontally) between the power pattern (VP in 31) fig. 3 [0044] and the second signal pattern (left SP in 31) (see annotated fig. 3 above).
Regarding claim 4, Mizunashi in view of Lee teaches the wiring substrate (1A) fig. 8 [0065-0066] of claim 1. Mizunashi also teaches wherein
the power pattern (13 in 51 connected to Vdd) fig. 8 [0069-0071] (see annotated fig. 8 above) vertically overlaps the first signal pattern (SP1 with 44 physically adjoined/effectively extending first signal pattern SP1) fig. 8 [0070] (see SP1 with 44 in annotated fig. 8 above), and
the first ground pattern (GP in 11) fig. 8 [0067] crosses a region (diagonally) between the first signal pattern (SP1 with 44) and the power pattern (13 connected to Vdd).
Regarding claim 6, Mizunashi in view of Lee teaches the wiring substrate (1A) fig. 8 [0065-0066] of claim 1. Mizunashi also teaches wherein
the power pattern (13 in 51 connected to Vdd) fig. 8 [0069-0071] (see annotated fig. 8 above) is (horizontally) between the signal pads (see SIG-P [0067] annotated fig. 8 above), when viewed in a plan view (when the cross sectional view of Fig. 8 of Mizunashi is viewed from the top, i.e., in a plan view, the current limitation are disclosed/anticipated – the claimed components are placed in the horizontal space between as claimed in both a cross-sectional view, as is explicitly shown in Fig. 8, and what would be shown in corresponding top/plan view, wherein the power pattern (see annotated fig. 8 above) would appear horizontally between the signal pads SIG-P in a top/plan view displaying both of their positions).
[AltContent: arrow][AltContent: textbox (Center region (CR) )][AltContent: textbox (edge region (ER) )][AltContent: arrow][AltContent: arrow][AltContent: connector][AltContent: rect][AltContent: connector]
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Annotated fig. 8 of Mizunashi designating center and edge region(s)
Regarding claim 7, Mizunashi in view of Lee teaches the wiring substrate (1A) fig. 8 [0065-0066] of claim 1. Mizunashi also teaches wherein
the ground pad (see GND-P annotated fig. 8 above) [0067] is on a center region (CR) of the pad layer (53 with 52) fig. 8 [0069],
the signal pads (SIG-P) are on (supported over) an edge region (ER) of the pad layer (53 with 52), and
the edge region (ER) of the pad layer encloses (laterally encloses) the center region (CR) of the pad layer (53 with 52) (see annotated fig. 8 above).
Regarding claim 8, Mizunashi in view of Lee teaches the wiring substrate (1A) fig. 8 [0065-0066] of claim 1. Mizunashi in view of Lee (with reference to Lee) also teaches wherein
on the ground pad (77GG) fig. 2 [0044], side surfaces of the power pattern (87PP) fig. 2 [0049] in a width direction are on (supported by) the ground pad (77GG).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Mizunashi (U.S. PG Pub No US2002/0139571A1) modified by Lee (U.S. PG Pub No US2007/0164429A1), as applied in claim 1 above, and further in view of Lee-II (U.S. PG Pub No US2021/0327830A1).
Regarding claim 5, Mizunashi in view of Lee teaches the wiring substrate (1A) fig. 8 [0065-0066] of claim 1. However, Mizunashi does not explicitly disclose wherein
on the ground pad (see GND-P annotated fig. 8 above) [0067], a horizontal width of the power pattern (13 in 51 connected to Vdd) fig. 8 [0069-0071] is 0.8 to 1.2 times a horizontal width of the ground pad (GND-P) (widths not disclosed; not clearly addressed).
Lee-II teaches a wiring substrate [see fig. 6, 0020] wherein
on the ground pad (135B) fig. 6 [0074-0076], a horizontal width of the power pattern (135A) fig. 6 [0072] is 0.8 to 1.2 times (~1 time(s) – estimated to have substantially identical horizontal widths) a horizontal width of the ground pad (135B) (see annotated fig. 6 of Lee-II below for visual estimate that 135A, 135B have substantially identical horizontal widths)
[AltContent: arrow][AltContent: arrow][AltContent: textbox (Substantially identical horizontal widths)]
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Annotated fig. 6 of Lee-II
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the wiring substrate of Mizunashi such that the power pattern and ground pad are formed of substantially identically-shaped layers with substantially the same horizontal widths [0072, 0075-0076] in order to form the power patterns and ground pad of optimally-sized conductive layers [0072, 0075-0076] for properly-sized current paths [0071-0072, 0083] with device circuitry, as taught by Lee-II.
Claims 13 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Mizunashi (U.S. PG Pub No US2002/0139571A1) in view of Lee-II (U.S. PG Pub No US2021/0327830A1).
Regarding claim 13, Mizunashi teaches the wiring substrate (1A) fig. 8 [0065-0066] of claim 9. However, Mizunashi does not explicitly disclose wherein
a horizontal width of the power pattern (13 in 51 connected to Vdd) fig. 8 [0069-0071] on the ground pad (see GND-P annotated fig. 8 above) [0067] is 0.8 to 1.2 times a horizontal width of the ground pad (GND-P) (widths not disclosed; not clearly addressed).
Lee-II teaches a wiring substrate [see fig. 6, 0020] wherein
a horizontal width of the power pattern (135A) fig. 6 [0072] on the ground pad (135B) fig. 6 [0074-0076] is 0.8 to 1.2 times (1 times – estimated to have substantially identical horizontal widths) a horizontal width of the ground pad (135B) (see annotated fig. 6 of Lee-II below for visual estimate that 135A, 135B have substantially identical horizontal widths)
[AltContent: arrow][AltContent: arrow][AltContent: textbox (Substantially identical horizontal widths)]
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Annotated fig. 6 of Lee-II
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the wiring substrate of Mizunashi such that the power pattern and ground pad are formed of substantially identically-shaped layers with substantially the same horizontal widths [0072, 0075-0076] in order to form the power patterns and ground pad of optimally-sized conductive layers [0072, 0075-0076] for properly-sized current paths [0071-0072, 0083] with device circuitry, as taught by Lee-II.
Regarding claim 16, Mizunashi teaches a semiconductor package (1A) fig. 8 [0065-0066], comprising:
a substrate (comprising 50 with 10 with 40) fig. 8 [0066];
a semiconductor chip (3) fig. 8 [0040] on (supported by) the substrate (comprising 50 with 10 with 40); and
a mold layer (4) fig. 8 [0039] on (supported by) the substrate (comprising 50 with 10 with 40) and enclosing (at least corners of) the semiconductor chip (3) (see also fig. 1, [0026, 0035]), wherein
the substrate (comprising 50 with 10 with 40) includes a body layer (comprising 51, 10, 40) fig. 8 [0066], a ground pad (surfaces of respective 52 connected with / acting as extensions of ground pattern(s) GP, GND [0067]) (see GND-P annotated fig. 8 below) and signal pads (surfaces of respective 52s connected with / acting as extensions of signal pattern(s) SP, S [0067]) (see SIG-P annotated fig. 8 below) on (directly on) a bottom surface of the body layer (comprising 51, 10, 40) fig. 8 [0066], a first signal pattern (SP1) fig. 8 [0067] (SP1 = 42 connected to underlying SP patterns) fig. 8 [0070] (see SP1 in annotated fig. 8 below) (SP1 component(s) patterns electrically connected with / acting as extensions of signal line pattern(s) SP [0067, 0070]) in the body layer (comprising 51, 10, 40), and a power pattern (13 in 51 connected to Vdd) fig. 8 [0069-0071] (see annotated fig. 8 below) in the body layer (comprising 51),
the power pattern (13 in 51 connected to Vdd) is (diagonally) between the ground pad (GND-P) and the first signal pattern (SP1),
the power pattern (13 in 51 connected to Vdd) is on (supported by) the ground pad (GND-P),
the first signal pattern (SP1) is on (supported by) the power pattern (13 in 51 connected to Vdd).
[AltContent: arrow][AltContent: textbox (SP1)][AltContent: rect][AltContent: arrow][AltContent: arrow][AltContent: textbox (1st Ground pattern)][AltContent: textbox (2nd signal patterns)][AltContent: arrow][AltContent: textbox (Power pattern)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (GND-P)][AltContent: arrow][AltContent: textbox (SIG-P’s)][AltContent: arrow]
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Annotated fig. 8 of Mizunashi
However, Mizunashi does not explicitly disclose on the ground pad (GND-P), a horizontal width of the power pattern is 0.8 to 1.2 times a horizontal width of the ground pad (GND-P).
Lee-II teaches a wiring substrate [see fig. 6, 0020] wherein
on the ground pad (135B) fig. 6 [0074-0076], a horizontal width of the power pattern (135A) fig. 6 [0072] is 0.8 to 1.2 times (1 times – estimated to have substantially identical horizontal widths) a horizontal width of the ground pad (135B) (see annotated fig. 6 of Lee-II below for visual estimate that 135A, 135B have substantially identical horizontal widths)
[AltContent: arrow][AltContent: arrow][AltContent: textbox (Substantially identical horizontal widths)]
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Annotated fig. 6 of Lee-II
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the wiring substrate of Mizunashi such that the power pattern and ground pad are formed of substantially identically-shaped layers with substantially the same horizontal widths [0072, 0075-0076] in order to form the power patterns and ground pad of optimally-sized conductive layers [0072, 0075-0076] for properly-sized current paths [0071-0072, 0083] with device circuitry, as taught by Lee-II.
Regarding claim 17, Mizunashi in view of Lee-II teaches the semiconductor package (1A) fig. 8 [0065-0066] of claim 16. Mizunashi also teaches further comprising:
a first ground pattern (GP in 11) fig. 8 [0067] in the body layer (comprising 51, 10, 40) fig. 8 [0066] and crossing a region (diagonally) between the power pattern (13 in 51 connected to Vdd) fig. 8 [0067] and the first signal pattern (SP1) (see annotated fig. 8 above), wherein
a width of the power pattern (13 in 51 connected to Vdd) is smaller than a width of the first ground pattern (GP in 11) (clear from fig. 8 of Mizunashi that GP in 11 has greater horizontal width than 13 in 51 - labeled in annotated fig. 8 above – because right sidewalls are aligned and GP in 11 clearly stretches horizontally wider to the left than 13 in 51 connected to Vdd).
Regarding claim 18, Mizunashi in view of Lee-II teaches the semiconductor package (1A) fig. 8 [0065-0066] of claim 16. However, the embodiment of fig. 8 of Mizunashi does not explicitly disclose further comprising:
second ground patterns in the body layer (comprising 51) at the same vertical level as the power pattern (13 in 51 connected to Vdd) fig. 8 [0069-0071], wherein the power pattern is between the second ground patterns (multiple second ground patterns in 51 not explicitly shown).
The embodiment of fig. 3 of Mizunashi discloses further comprising:
second ground patterns (left, right GP in 31) [0044] (see annotated fig. 3 below) in the body layer (31) fig. 3 [0043] at the same vertical level as the power pattern (VP in 31) fig. 3 [0044], wherein the power pattern (VP in 31) is (horizontally) between the second ground patterns (left/right GP in 31).
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Annotated fig. 3 of Mizunashi
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the wiring substrate of the embodiment of fig. 8 of Mizunashi such that additional ground pattern(s) are disposed to the left/right of the power pattern [0043-0044], such that the power pattern is horizontally between multiple second ground patterns [0043-0044], in order to guarantee a sufficient number of ground patterns [0044-0045] in the package for high frequency signal transmission applications [0049], as taught by the embodiment of fig. 3 of Mizunashi.
Regarding claim 19, Mizunashi in view of Lee-II teaches the semiconductor package (1A) fig. 8 [0065-0066] of claim 16. Mizunashi also teaches wherein, on the ground pad (surfaces of respective 52 connected with / acting as extensions of ground pattern(s) GP, GND [0067]) (see GND-P annotated fig. 8 above), side surfaces (sidewalls) of the power pattern (13 in 51 connected to Vdd) fig. 8 [0069-0071] in a width direction are on (supported by) the ground pad (GND-P).
Regarding claim 20, Mizunashi in view of Lee-II teaches the semiconductor package (1A) fig. 8 [0065-0066] of claim 16. Mizunashi also teaches, further comprising:
second signal patterns (SP’s in 51) fig. 8 [0067] in the body layer (comprising 51, 10, 40) fig. 8 [0066] and at the same vertical level as the power pattern (13 in 51 connected to Vdd) fig. 8 [0069-0071], wherein
the power pattern (13 in 51 connected to Vdd) is placed (horizontally) between the second signal patterns (left/right SP’s in 51) (see annotated fig. 8 of Mizunashi above).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form are considered relevant to the present disclosure because they all feature wiring substrates with ground and power patterns/pads.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 06/25/2026
Prosecution Insights