DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the application filed on 6/25/24. Claims 1-15 are pending.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) were submitted on 6/025/24, 6/04/25, 7/14/25, and 11/12/25. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ando (US Patent 5/877,478, hereinafter referred to as “Ando”).
Ando discloses the semiconductor device as claimed. See figures 1-16 and corresponding text, where Ando teaches, in claim 1, a chip comprising:
at least one bump (2) arranged on an active surface and protruding from the active surface, the at least bump (2) is configured to bond with a lead (3) on a circuit board (1); and
at least one supportive element (6) arranged on the active surface, protruding from the active surface and located between the at least one bump (2) and a first side of the active surface, the at least one supportive element (6) is configured to support the lead (3), wherein a first height of the at least one bump is greater than or equal to a second height of the at least one supportive element (6) ( figures 6-8; col. 6, lines 55-60; col. 7, lines 1-7).
Ando teaches, in claim 2, wherein the first height is greater than the second height, and a difference between the first and second heights is less than or equal to 7 μm ( figures 6-8; col. 6, lines 55-60; col. 7, lines 1-7).
Ando teaches, in claim 3, wherein the second height is greater than or equal to 5 μm ( figures 6-8; col. 6, lines 55-60; col. 7, lines 1-7).
Ando teaches, in claim 4, wherein a first distance is defined from the at least one bump to the at least one supportive element, a second distance is defined from the at least one supportive element to an imaginary line extending from the first side of the active surface, and a quotient of the first and second distances is between 0.5 and 100 ( figures 6-8; col. 6, lines 55-60; col. 7, lines 1-7).
Ando teaches, in claim 5, wherein a width of the at least one supportive element in a direction of an axis line extending from the at least one supportive element toward the first side of the active surface is greater than or equal to 5 μm ( figures 6-8; col. 6, lines 55-60; col. 7, lines 1-7).
Ando teaches, in claim 6, further comprising a metal layer and a protective layer, wherein the metal layer includes a plurality of conductive pads and a seal ring, the plurality of conductive pads are surrounded by the seal ring, the seal ring is covered by the protective layer, the plurality of conductive pads are not covered by the protective layer, a surface of the protective layer is the active surface, the at least one bump is electrically connected to one of the plurality of conductive pads, the seal ring projects to the active surface to form a seal ring projection, and the at least one supportive element is located between the at least one bump and the seal ring projection ( figures 6-8; col. 6, lines 55-60; col. 7, lines 1-7).
Ando teaches, in claim 7, wherein an outer side wall of the at least one supportive element is adjacent to the first side of the active surface, a third distance between the outer side wall and the seal ring projection is greater than or equal to 1 μm ( figures 6-8; col. 6, lines 55-60; col. 7, lines 1-7).
Ando teaches, in claim 8, wherein an inner side wall of the at least one supportive element is adjacent to the at least one bump, a first distance between the inner side wall and the at least one bump is greater than or equal to 1 μm ( figures 6-8; col. 6, lines 55-60; col. 7, lines 1-7).
Ando teaches, in claim 9, comprising a plurality of supportive elements, wherein a gap located between the adjacent supportive elements communicates the first side of the active surface and a bump arrangement area defined on the active surface, the at least one bump is arranged on the bump arrangement area ( figures 6-8; col. 6, lines 55-60; col. 7, lines 1-7).
Ando teaches, in claim 10, further comprising a metal layer and a protective layer, wherein the metal layer includes at least one conductive pad and a seal ring, the at least one conductive pad is surrounded by the seal ring, the seal ring is covered by the protective layer, the at least one conductive pad is not covered by the protective layer, a surface of the protective layer is the active surface, the at least one bump is electrically connected to the at least one conductive pad, the seal ring projects to the active surface to form a seal ring projection, and the at least one supportive element is located between the seal ring projection and the first side of the active surface ( figures 6-8; col. 6, lines 55-60; col. 7, lines 1-7).
Ando teaches, in claim 11 comprising a plurality of supportive elements, wherein a gap located between the adjacent supportive elements communicates the first side of the active surface and a bump arrangement area defined on the active surface, the at least one bump is arranged on the bump arrangement area ( figures 6-8; col. 6, lines 55-60; col. 7, lines 1-7).
Ando teaches, in claim 12, wherein an outer side wall of each of the plurality of supportive elements and a side wall of the chip are flush ( figures 6-8; col. 6, lines 55-60; col. 7, lines 1-7).
Ando teaches, in claim 13, wherein an outer side wall of the at least one supportive element and a side wall of the chip are flush ( figures 6-8; col. 6, lines 55-60; col. 7, lines 1-7).
Ando teaches, in claim 14, wherein the at least one bump projects to the at least one supportive element in a direction of an axis line extending from the at least one supportive element toward the first side of the active surface, a first length of the at least one bump is less than or equal to a second length of the at least one supportive element in a direction vertical to the axis line ( figures 6-8; col. 6, lines 55-60; col. 7, lines 1-7).
Ando teaches, in claim 15, wherein the at least one bump projects to the at least one supportive element to form a bump projection, the at least one supportive element has a third side adjacent to a second side of the bump projection, a fourth distance between the second and third sides is greater than or equal to 1 μm in the direction vertical to the axis line ( figures 6-8; col. 6, lines 55-60; col. 7, lines 1-7).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6.
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/STANETTA D ISAAC/Examiner, Art Unit 2898 July 11, 2026
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