DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities: in paragraph [0035] lines 2, 4 and 8, “the bonded” should read --the bond--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanoue (US 2021/0242010) in view of Wu et al. (US 20210193453) and Nakamura et al. (US 20060079155).
With regard to claim 1, Tanoue discloses a wafer processing method comprising a bonded wafer forming step of forming a bonded wafer T by bonding one side of a first wafer W and one side of a second wafer S (figs. 2 and 3), a modified layer forming step of, after the bonded wafer forming step is performed, forming modified layers M (M1, M2) in an annular pattern and cracks C, which spread from the modified layers, inside the first wafer by irradiating an annular region on an inner side by a predetermined distance from an outer peripheral edge in the first wafer with a laser beam L of a wavelength having transmissivity for the first wafer (paragraphs [0057]-[0058] and figs. 5, 21B), an outer peripheral region removal step of, after the modified forming step is performed, removing an outer peripheral region of the first wafer, the outer peripheral region being on a side of the outer peripheral edge relative to the modified layers and cracks, by positioning a grinding tool 132 at the annular region of the first wafer, and causing the grinding tool to cut in from a side of the other side of the first wafer to a depth not reaching the second wafer, along the annular region (paragraphs [0067]-[0069] and [0076]-[0081]), and a grinding step of thinning the first wafer of the bonded wafer to a finish thickness by grinding the first wafer from the side of the other side (paragraph [0040]). Tanoue does not specifically disclose that the outer peripheral region removal step is performed by a cutting blade or that the thinning of the first wafer takes place after the removal step however, Wu et al. teaches using a cutting blade to remove an outer peripheral region of a wafer using a cutting blade 210 (Fig. 11B), therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have performed the outer peripheral region removing step by a cutting blade in the processing method of Tanoue, in light of the teaching of Wu et al. as is known in the art as an obvious matter of engineering design choice. Further, Nakamura teaches removing an outer peripheral region of a wafer before thinning a wafer by grinding, see abstract and figures 5-9. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have performed the grinding step of thinning the first wafer in the processing method of Tanoue/Wu et al. after the outer peripheral region removal step, in light of the teaching of Nakamura et al., as a matter of obvious engineering design choice as the order of the sequence of the steps does not solve any stated problem nor does it lead to unexpected results.
Regarding claim 2, see figure 16D of Tanoue.
Regarding claims 3 and 4, see figure 2 of Wu et al. Applicant should note that the relative positioning of the cutting blade in relation to the annular region in the first wafer is an obvious matter of engineering design choice as long as an effective an accurate cut is achieved.
Claim(s) 5-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanoue in view Wu et al., Nakamura et al. and Chen et al. (US 2024/0339326).
With regard to claim 1, Tanoue discloses a wafer processing method comprising a bonded wafer forming step of forming a bonded wafer T by bonding one side of a first wafer W and one side of a second wafer S (figs. 2 and 3), a modified layer forming step of, after the bonded wafer forming step is performed, forming modified layers M (M1, M2) in an annular pattern and cracks C, which spread from the modified layers, inside the first wafer by irradiating an annular region on an inner side by a predetermined distance from an outer peripheral edge in the first wafer with a laser beam L of a wavelength having transmissivity for the first wafer (paragraphs [0057]-[0058] and figs. 5, 21B), an outer peripheral region removal step of, after the modified forming step is performed, removing an outer peripheral region of the first wafer, the outer peripheral region being on a side of the outer peripheral edge relative to the modified layers and cracks, by positioning a grinding tool 132 at the annular region of the first wafer, and causing the grinding tool to cut in from a side of the other side of the first wafer to a depth not reaching the second wafer, along the annular region (paragraphs [0067]-[0069] and [0076]-[0081]), and a grinding step of thinning the first wafer of the bonded wafer to a finish thickness by grinding the first wafer from the side of the other side (paragraph [0040]). Tanoue does not specifically disclose that the outer peripheral region removal step is performed by a cutting blade or that the thinning of the first wafer takes place after the removal step however, Wu et al. teaches using a cutting blade to remove an outer peripheral region of a wafer using a cutting blade 210 (Fig. 11B), therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have performed the outer peripheral region removing step by a cutting blade in the processing method of Tanoue, in light of the teaching of Wu et al. as is known in the art as an obvious matter of engineering design choice. Further, Nakamura teaches removing an outer peripheral region of a wafer before thinning a wafer by grinding, see abstract and figures 5-9. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have performed the grinding step of thinning the first wafer in the processing method of Tanoue/Wu et al. after the outer peripheral region removal step, in light of the teaching of Nakamura et al., as a matter of obvious engineering design choice as the order of the sequence of the steps does not solve any stated problem nor does it lead to unexpected results.
Although Tanoue/Wu et al./Nakamura et al. does not disclose a provisional bonding step followed by a subsequent annealing step however, it is known to provisionally bond two wafers and followed by a subsequent annealing step in a wafer edge trimming process as attested Chen et al., see paragraph [0025]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied the two bonding process of Chen et al. in the wafer processing method of Tanoue/Wu et al./Nakamura et al., as is known in the art.
Regarding claim 6, Official Notice is taken in that it is known to cut such a wafer to a depth not reaching modified layers.
Regarding claim 7, see figure 2 of Wu et al.
Regarding claim 8, Applicant should note that the relative positioning of the cutting blade in relation to the annular region in the first wafer is an obvious matter of engineering design choice as long as an effective an accurate cut is achieved.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/ESSAMA OMGBA/Supervisory Patent Examiner, Art Unit 3746
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