Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-20 set forth in the amendment submitted 7/28/2026 form the basis of the present examination.
Response to Arguments
The objection to claims 2-7, 9-13 and 15-20, set forth to the Non-Final Office action mailed on 4/28/2026 has been withdrawn because of the amendment filed on 7/28/2026.
The interpretation of the claim limitation(s) under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, set forth to the Non-Final Office action mailed on 4/28/2026 has been withdrawn because of the amendment filed on 7/28/2026.
Applicant’s arguments, see remarks page 11, filed 7/28/2026, with respect to the rejection(s) of Claims 1-20 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention have been fully considered as follows:
Applicant’s Argument:
Applicant argues on page 11, of the remarks, filed on 7/28/2026, regarding the rejection(s) of Claims 1-20 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention, that “Amended claims 1 and 14 recite that the tap points are selected by a multiplexer circuit, that the frequency is produced by a ring oscillator comprising at least one passgate operatively coupled to receive respective signals from the plurality of selected tap points, and that the data is provided by control circuitry. These amendments identify the elements of the voltage drop detection circuitry and specify how the tap points are selected, how the frequency is determined, and how the data is provided. Claims 8 and 17 have been amended to specify that the first mode comprises a voltage drop mapping mode and that the second mode comprises a short circuit detection mode, and claim 8 further recites that the frequency is produced based on voltage levels of the respective signals received from the first and second outputs. Claim 15 has been amended to recite that the voltage map is generated by the control circuitry, and the remaining claims have been conformed and corrected.
Thus, Applicant respectfully asserts that claims 1-20 and new claim 21 are definite under 35 U.S.C. § 112(b). Withdrawal of these rejections is therefore respectfully requested.”
Examiner Response:
Applicant’s arguments, see remarks page 11 (stated above), filed 7/28/2026, with respect to the rejection(s) of Claims 1-20 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention, as applied to the Non-Final Office Action mailed on 4/28/2026 have been fully considered and is persuasive because applicant has amended claim 1, 8 and 14 which makes the claim language clear. Therefore, the rejection of Claims 1-20 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention, as applied to the Non-Final Office Action mailed on 4/28/2026 has been withdrawn, as set forth below.
Applicant’s arguments, see remarks page 12-14, filed 7/28/2026, with respect to the rejection(s) of Claim(s) 1 and 14 under 35 U.S.C. 102 (a) (1) as being anticipated by Narayanan et al. (Hereinafter, “Narayanan”) in the US Patent Application Publication Number US 20150276824 A1 and the rejection of Claim(s) 2 under 35 U.S.C. 103 as being unpatentable over Narayanan ‘824 A1 in view of Friend et al. (Hereinafter, “Friend”) in the US Patent Application Publication Number US 20100001804 A1 have been fully considered as follows:
Applicant’s Argument:
Applicant argues on page 12-14, of the remarks, filed on 7/28/2026, regarding the rejection(s) of Claim(s) 1 and 14 under 35 U.S.C. 102 (a) (1) as being anticipated by Narayanan et al. (Hereinafter, “Narayanan”) in the US Patent Application Publication Number US 20150276824 A1, that “However, Narayanan fails to disclose all of the features of any of the rejected claims. For example, Narayanan fails to describe or suggest "wherein the frequency is produced by a ring oscillator comprising at least one passgate operatively coupled to receive respective signals from the plurality of selected tap points," as recited in amended claim 1, and as similarly recited in amended claim 14, though each claim has its own scope (Remarks-Page 12)
……………….
Narayanan does not produce any frequency from signals received from selected tap points, and Narayanan does not provide data representing such a frequency. The same (Remarks-page 13) deficiency applies to amended claim 14, which recites producing the data by control circuitry, with the frequency produced by the ring oscillator.
Accordingly, Applicant respectfully asserts that Narayanan fails to disclose all of the features of any of amended claims 1 and 14. The withdrawal of this rejection is therefore respectfully requested (Remarks-page 14).”
Examiner Response:
Applicant’s arguments, see remarks page 12-14 (stated above), filed on 7/28/2026, regarding the rejection(s) of Claim(s) 1 and 14 under 35 U.S.C. 102 (a) (1) as being anticipated by Narayanan et al. (Hereinafter, “Narayanan”) in the US Patent Application Publication Number US 20150276824 A1, as applied to the Non-Final Office Action mailed on 4/28/2026 have been fully considered and is persuasive because applicant has amended the claim 1. Therefore, the rejection of independent claim 1 and 14 has been withdrawn. However, applicant has amended the claim 1, and added the limitation, “voltage drop detection circuitry, operative to select, by a multiplexer circuit, each of a plurality of tap points from the on-chip power conductor network and in response to a plurality of selected tap points, provide, by control circuitry, data representing a frequency corresponding to a voltage level of each of the plurality of selected tap points, wherein the frequency is produced by a ring oscillator comprising at least one passgate operatively coupled to receive respective signals from the plurality of selected tap points.” and similar amendment for claim 14, which necessitates a new ground of rejection. Friend et al. (Hereinafter, “Friend”) in the US Patent Application Publication Number US 20100001804 A1 is applied to meet at least the amended limitation of claim 1 and 14 as explained below. Therefore, the rejection of Claim(s) 1 and 14 under 35 U.S.C. 102 (a) (1) as being anticipated by Narayanan et al. (Hereinafter, “Narayanan”) in the US Patent Application Publication Number US 20150276824 A1, as applied to the Non-Final Office Action mailed on 4/28/2026 has been withdrawn. Claims 1 and 14 is now rejected under 35 U.S.C. 103 as being unpatentable over Narayanan et al. (Hereinafter, “Narayanan”) in the US Patent Application Publication Number US 20150276824 A1 in view of Friend et al. (Hereinafter, “Friend”) in the US Patent Application Publication Number US 20100001804 A1, as set forth below. Applicant’s argument is moot in view of newly applied combination of references. See the rejection set forth below.
Applicant’s arguments, see remarks page 14-15, filed 7/28/2026, with respect to the rejection of Claim(s) 2 under 35 U.S.C. 103 as being unpatentable over Narayanan ‘824 A1 in view of Friend et al. (Hereinafter, “Friend”) in the US Patent Application Publication Number US 20100001804 A1 have been fully considered as follows:
Applicant’s Argument:
Applicant argues on page 14-15, of the remarks, filed on 7/28/2026, regarding the rejection of Claim(s) 2 under 35 U.S.C. 103 as being unpatentable over Narayanan ‘824 A1 in view of Friend et al. (Hereinafter, “Friend”) in the US Patent Application Publication Number US 20100001804 A1, that “The deficiencies of Narayanan are described above, and the portions of Friend cited by the Office Action do not remedy the deficiencies of Narayanan. The Office Action cites Friend for a ring oscillator in which a filter voltage 110 is connected to passgates 130, 132, and 134 and controls the speed of the oscillation (Office Action, pages 17-18). The Office Action does not identify, and the cited combination does not disclose or suggest, at least one passgate operatively coupled to receive respective signals from a plurality of selected tap points of an on-chip power conductor network, such that a ring oscillator produces a frequency corresponding to a voltage level of each of the selected tap points.
Further, the Office Action states that the reason for the proposed combination is to use an improved voltage-controlled oscillator, to control a first voltage passing through the voltage-controlled oscillator based upon a digital tune bit used to control the oscillator's gain, and to provide new functionality with minimal overhead and less complexity (Office Action, page 18) (Remarks-Page 14).
The stated reason concerns improving the controllability of an oscillator, but the Office Action does not explain why a person of ordinary skill in the art would have coupled tap point signals selected from Narayanan's power grid to passgates of a ring oscillator so that the oscillator produces a measurement frequency in place of Narayanan's comparator based evaluation. The rejection therefore does not account for the claimed arrangement, in which the frequency itself is the measurement of the selected tap points.
Accordingly, Applicant respectfully asserts that the features of claim 2 are patentable over the applied references, for its dependency from amended claim 1 and the features recited therein. The withdrawal of this rejection is therefore respectfully requested (Remarks-page 15).”
Examiner Response:
Applicant’s arguments, see remarks page 14-15 (stated above), filed on 7/28/2026, regarding the rejection(s) of Claim(s) 2 under 35 U.S.C. 103 as being unpatentable over Narayanan ‘824 A1 in view of Friend et al. (Hereinafter, “Friend”) in the US Patent Application Publication Number US 20100001804 A1, as applied to the Non-Final Office Action mailed on 4/28/2026 have been fully considered and is not persuasive
Applicant argues that, “The Office Action does not identify, and the cited combination does not disclose or suggest, at least one passgate operatively coupled to receive respective signals from a plurality of selected tap points of an on-chip power conductor network, such that a ring oscillator produces a frequency corresponding to a voltage level of each of the selected tap points” which is not persuasive. Narayanan discloses, “In FIG. 3, replicating the shared circuitry of FIG. 2 once or just a few times reduces line lengths for routing tap lines 223.i.1 and 223.i.2 even further in some integrated circuits. Each mux 225.1, 225.2 serves a separate set of the taps 30.i so that a set of power grid point voltages VPGP_i.1 and another set of power grid point voltages VPGP_i.2 are fed to respective shared comparators 210.1 and 210.2; Paragraph [0068] Line 1-7”. Friend discloses, “In FIG. 1, a filter voltage 110 is connected to passgates 130, 132, and 134 and controls the speed of the oscillation of the three stage ring oscillator, composed of inverters 120, 122, and 124. An output voltage 112 will rise and fall from the power supply voltage to the ground voltage at a frequency determined by the gain of the oscillator multiplied by the value of the filter voltage. The gain will be a function of the transistor characteristics and therefore change when the transistor parameters change; Paragraph [0034] Line 1-9).” Therefore, the ring oscillator of Friend is placed to the output of the multiplexer to generate frequency dependent on the voltage level. Although Friend does not say anything about producing frequency. However, one of an ordinary skill will understand that a ring oscillator produces frequency (A ring oscillator is one of the simplest digital oscillator circuits, built from a loop of inverting logic gates. Despite its basic design, it is widely used in integrated circuits for timing and testing, as well as frequency generation; https://www.eleccircuit.com/ring-oscillator-circuit/). Claim does not recite that the frequency is used for doing something or any specific structural configuration or connection of multiplexer and passgate of the ring oscillator. It is not needed that both references will have the same motivation or purpose. Friend is introduced to Narayanan reference so that the ring oscillator can produce frequency.
In response to Applicant’s argument that there is no suggestion to combine the references, the Examiner recognizes that references cannot be arbitrarily combined and that there must be some reason why one skilled in the art would be motivated to make the proposed combination of primary and secondary references. In re Nomiya, 184 USP'Q 607 (CCPA 1975). However, there is no requirement that a motivation to make the modification be expressly articulated. The test for combining references is what the combination of disclosures taken as a whole would suggest to one of ordinary skill in the art. In re McLaughlin, 170 USPQ 209 (CCPA 1971). References are evaluated by what they suggest to one versed in the art, rather than by their specific disclosures. In re Bozek, 163 USPQ 945 (CCPA) 1969.
Therefore, for the broadest reasonable interpretation Fiend can still be applied to reject claim 2. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Narayanan et al. (Hereinafter, “Narayanan”) in the US Patent Application Publication Number US 20150276824 A1 in view of Friend et al. (Hereinafter, “Friend”) in the US Patent Application Publication Number US 20100001804 A1, as set forth below. See the rejection set forth below.
Regarding independent claim 8, applicant has amended the claim and made the limitation clear and therefore Claims 8-13 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention has been withdrawn and claims 8-13 are therefore allowed. The reason for allowance is explained below after the rejection.
Regarding dependent claims 3-7 and 15-20, applicant has amended the claim and made the limitation clear and therefore Claims 3-7 and 15-20 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention has been withdrawn and claims 3-7 and 15-20 are indicated as allowable subject matter as being dependent on reject claims 1 and 14, as set forth below.
Examiner Note: Applicant in the remarks page 9 filed on 7/28/2026 mentioned that a new claim 21 is added. However new claim 21 is not found in the amended claims section or in the remarks. Therefore claim 21 cannot be examined.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Narayanan et al. (Hereinafter, “Narayanan”) in the US Patent Application Publication Number US 20150276824 A1 in view of Friend et al. (Hereinafter, “Friend”) in the US Patent Application Publication Number US 20100001804 A1.
Regarding claim 1, Narayanan teaches an integrated circuit [10] (An integrated circuit includes a functional circuit (10) having a power grid (20) with a set of power grid points (30.i) for monitoring; Abstract; FIG. 1A is a simplified pictorial diagram of conductive lines of a power grid of an integrated circuit chip and having power grid points for electrical monitoring and testing; Paragraph [0020] Line 1-4) comprising:
at least one on-chip power conductor network [20] (power grid 20 as the on-chip power conductor network) (In FIG. 1A, an integrated circuit 10 has a power grid 20; Paragraph [0044] Line 1-2) configured to distribute electrical power to a plurality of electrical components on the integrated circuit (In FIG. 1A, an integrated circuit 10 has a power grid 20, which is a layout of a material in the integrated circuit 10 that extends to a power connection for the integrated circuit of either common (ground GND), or a positive or negative voltage connection VDD. The power grid 20 may include a portion of conductor having an intersection or tap going to circuitry to be powered; Paragraph [0044] Line 1-7); and
voltage drop detection circuitry [100.i] (In some embodiments a respective IR drop monitoring circuit 100.i, such as that of FIG. 1B; Paragraph [0045] Line 7-9), operative to select, by a multiplexing circuit [225.1, 225.2] in Figure 3 (In FIG. 3, replicating the shared circuitry of FIG. 2 once or just a few times reduces line lengths for routing tap lines 223.i.1 and 223.i.2 even further in some integrated circuits. Each mux 225.1, 225.2 serves a separate set of the taps 30.i so that a set of power grid point voltages VPGP_i.1 and another set of power grid point voltages VPGP_i.2 are fed to respective shared comparators 210.1 and 210.2; Paragraph [0068] Line 1-7) each of a plurality of tap points [30.i] (In FIG. 1A, the power grid 20 on integrated circuit 10 is tapped at various points 30.i as shown by enlarged dots. In cross-section (not shown) the integrated circuit 10 may have a layer of transistors and one or more elevated layers (e.g., metal or polysilicon, etc) overlying the transistor layer and coupled to the transistor layer by vias; Paragraph [0045] Line 1-6) from the on-chip power conductor network [20](In some embodiments a respective IR drop monitoring circuit 100.i, such as that of FIG. 1B, is physically associated with, at, or near each of the taps (dots) 30.i of power grid 20; Paragraph [0045] Line 7-10) and in response to a plurality of selected tap points [30.i] (In some embodiments a respective IR drop monitoring circuit 100.i, such as that of FIG. 1B, is physically associated with, at, or near each of the taps (dots) 30.i of power grid 20 and used to detect the IR drop (voltage drop) at its tap 30.i. In some other embodiments, one or more shared IR drop monitoring circuits such as any one, some or all of circuits in any of FIGS. 2-11 and 15A is electrically coupled with at least one group of the taps (dots) 30.i and used to detect the IR drops; Paragraph [0045] Line 7-15; In FIG. 1B, the circuit 100.i has a respective comparator 110.i that compares the voltage V.sub.PGP seen at a tap i, or particular location 30.i in the power grid 20, with an analog electrical reference V.sub.REF from an analog reference source circuit 150. The reference voltages for comparison with the voltage V.sub.PGP seen at the different points in the power grid are thus economically supplied from one same analog voltage reference circuit 150.
[0047] In FIG. 1B, the circuit 100.i has a respective comparator 110.i that compares the voltage V.sub.PGP seen at a tap i, or particular location 30.i in the power grid 20, with an analog electrical reference V.sub.REF from an analog reference source circuit 150. The reference voltages for comparison with the voltage V.sub.PGP seen at the different points in the power grid are thus economically supplied from one same analog voltage reference circuit 150; Paragraph [0047] Line 1-8).
Provide, by a control circuit data [190] representing a frequency corresponding to a voltage level of each of the plurality of selected tap points (In FIG. 1B, note also that some embodiments couple one or more of the IR drop monitoring scan registers 120.i to a power management circuit 190. In this way, instances of excessive IR drop can not only be detected during scan test, but also the power management circuit 190 can respond to such instances of excessive drop during regular functional operation of the integrated circuit 10. Such power management response may reduce functional operating frequency or increase supply voltage, or both, such as by transitioning to a different voltage/clock frequency DVFS Operating Performance Point (OPP) or doing automatic voltage scaling AVS; Paragraph [0059] Line 1-11; depending on the voltage level of different tap points frequency is reduced or controlled and therefore data represent frequency either reduced or increased).
Narayanan fails to teach that wherein the frequency is produced by a ring oscillator comprising at least one passgate operatively coupled to receive respective signals from the plurality of selected tap points.
Friend teaches electronic oscillators, and, more particularly, to voltage-controlled oscillators (Paragraph [0001] Line 1-3), wherein
wherein the frequency is produced by a ring oscillator comprising at least one passgate [130, 132, and 134], operatively coupled to receive respective signals from the plurality of selected tap points (In FIG. 1, a filter voltage 110 is connected to passgates 130, 132, and 134 and controls the speed of the oscillation of the three stage ring oscillator, composed of inverters 120, 122, and 124. An output voltage 112 will rise and fall from the power supply voltage to the ground voltage at a frequency determined by the gain of the oscillator multiplied by the value of the filter voltage. The gain will be a function of the transistor characteristics and therefore change when the transistor parameters change; Paragraph [0034] Line 1-9). The purpose of doing so is to use an improved voltage-controlled oscillator, to control a first voltage passing through the voltage-controlled oscillator based upon a digital tune bit used to control the voltage-controlled oscillator's gain, to provide new functionality and has minimal overhead and is less complex.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify Narayanan by introducing a ring oscillator as disclosed by Friend, because Friend teaches to include a ring oscillator controls a first voltage passing through the voltage-controlled oscillator based upon a digital tune bit used to control the voltage-controlled oscillator's gain (Paragraph [0015]), provides new functionality and has minimal overhead and is less complex (Paragraph [0043]).
Regarding claim 14, Narayanan teaches a method for detecting voltage drops (An integrated circuit includes a functional circuit (10) having a power grid (20) with a set of power grid points (30.i) for monitoring; Abstract; FIG. 1A is a simplified pictorial diagram of conductive lines of a power grid of an integrated circuit chip and having power grid points for electrical monitoring and testing; Paragraph [0020] Line 1-4) in an on-chip power conductor network [20] (power grid 20 as the on-chip power conductor network) (In FIG. 1A, an integrated circuit 10 has a power grid 20; Paragraph [0044] Line 1-2) comprising:
selecting, by a multiplexer circuit [225.1, 225.2] in Figure 3 (In FIG. 3, replicating the shared circuitry of FIG. 2 once or just a few times reduces line lengths for routing tap lines 223.i.1 and 223.i.2 even further in some integrated circuits. Each mux 225.1, 225.2 serves a separate set of the taps 30.i so that a set of power grid point voltages VPGP_i.1 and another set of power grid point voltages VPGP_i.2 are fed to respective shared comparators 210.1 and 210.2; Paragraph [0068] Line 1-7) each of a plurality of tap points [30.i] (In FIG. 1A, the power grid 20 on integrated circuit 10 is tapped at various points 30.i as shown by enlarged dots. In cross-section (not shown) the integrated circuit 10 may have a layer of transistors and one or more elevated layers (e.g., metal or polysilicon, etc) overlying the transistor layer and coupled to the transistor layer by vias; Paragraph [0045] Line 1-6) from the on-chip power conductor network [20](In some embodiments a respective IR drop monitoring circuit 100.i, such as that of FIG. 1B, is physically associated with, at, or near each of the taps (dots) 30.i of power grid 20; Paragraph [0045] Line 7-10); and
in response to a plurality of selected tap points [30.i] (In some embodiments a respective IR drop monitoring circuit 100.i, such as that of FIG. 1B, is physically associated with, at, or near each of the taps (dots) 30.i of power grid 20 and used to detect the IR drop (voltage drop) at its tap 30.i. In some other embodiments, one or more shared IR drop monitoring circuits such as any one, some or all of circuits in any of FIGS. 2-11 and 15A is electrically coupled with at least one group of the taps (dots) 30.i and used to detect the IR drops; Paragraph [0045] Line 7-15; In FIG. 1B, the circuit 100.i has a respective comparator 110.i that compares the voltage V.sub.PGP seen at a tap i, or particular location 30.i in the power grid 20, with an analog electrical reference V.sub.REF from an analog reference source circuit 150. The reference voltages for comparison with the voltage V.sub.PGP seen at the different points in the power grid are thus economically supplied from one same analog voltage reference circuit 150.
[0047] In FIG. 1B, the circuit 100.i has a respective comparator 110.i that compares the voltage V.sub.PGP seen at a tap i, or particular location 30.i in the power grid 20, with an analog electrical reference V.sub.REF from an analog reference source circuit 150. The reference voltages for comparison with the voltage V.sub.PGP seen at the different points in the power grid are thus economically supplied from one same analog voltage reference circuit 150; Paragraph [0047] Line 1-8),
Producing by control circuitry, data representing a frequency corresponding to a voltage level of each of the plurality of selected tap points (In FIG. 1B, note also that some embodiments couple one or more of the IR drop monitoring scan registers 120.i to a power management circuit 190. In this way, instances of excessive IR drop can not only be detected during scan test, but also the power management circuit 190 can respond to such instances of excessive drop during regular functional operation of the integrated circuit 10. Such power management response may reduce functional operating frequency or increase supply voltage, or both, such as by transitioning to a different voltage/clock frequency DVFS Operating Performance Point (OPP) or doing automatic voltage scaling AVS; Paragraph [0059] Line 1-11; depending on the voltage level of different tap points frequency is reduced or controlled and therefore data represent frequency either reduced or increased).
Narayanan fails to teach that wherein the frequency is produced by a ring oscillator comprising at least one passgate operatively coupled to receive respective signals from the plurality of selected tap points.
Friend teaches electronic oscillators, and, more particularly, to voltage-controlled oscillators (Paragraph [0001] Line 1-3), wherein
wherein the frequency is produced by a ring oscillator comprising at least one passgate [130, 132, and 134], operatively coupled to receive respective signals from the plurality of selected tap points (In FIG. 1, a filter voltage 110 is connected to passgates 130, 132, and 134 and controls the speed of the oscillation of the three stage ring oscillator, composed of inverters 120, 122, and 124. An output voltage 112 will rise and fall from the power supply voltage to the ground voltage at a frequency determined by the gain of the oscillator multiplied by the value of the filter voltage. The gain will be a function of the transistor characteristics and therefore change when the transistor parameters change; Paragraph [0034] Line 1-9). The purpose of doing so is to use an improved voltage-controlled oscillator, to control a first voltage passing through the voltage-controlled oscillator based upon a digital tune bit used to control the voltage-controlled oscillator's gain, to provide new functionality and has minimal overhead and is less complex.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify Narayanan by introducing a ring oscillator as disclosed by Friend, because Friend teaches to include a ring oscillator controls a first voltage passing through the voltage-controlled oscillator based upon a digital tune bit used to control the voltage-controlled oscillator's gain (Paragraph [0015]), provides new functionality and has minimal overhead and is less complex (Paragraph [0043]).
Regarding claim 2, Narayanan teaches an integrated circuit, wherein the voltage drop detection circuitry comprises:
the multiplexer circuit [225.1, 225.2] in Figure 3 comprising a first output (a first output to comparator 210.1) and a second output (a second output to comparator 210.2), each output providing a respective signal from a different selected tap point [223.i.1 and 223.i.2] from the plurality of tap points [30.i] in Figure 2 (In FIG. 3, replicating the shared circuitry of FIG. 2 once or just a few times reduces line lengths for routing tap lines 223.i.1 and 223.i.2 even further in some integrated circuits. Each mux 225.1, 225.2 serves a separate set of the taps 30.i so that a set of power grid point voltages VPGP_i.1 and another set of power grid point voltages VPGP_i.2 are fed to respective shared comparators 210.1 and 210.2; Paragraph [0068] Line 1-7).
Narayanan fails to teach that the voltage detection circuitry comprises: a ring oscillator comprising an odd number of serially coupled inverters and at least one passgate interposed between each respective serially coupled inverter, each passgate operatively coupled to receive the respective signals from the first and second outputs from the multiplexer circuit.
Friend teaches electronic oscillators, and, more particularly, to voltage-controlled oscillators (Paragraph [0001] Line 1-3), wherein
the ring oscillator comprising an odd number of serially coupled inverters [120, 122, and 124] (3 inverters) wherein the at least one passgate [130, 132, and 134] is interposed between each respective serially coupled inverter [120, 122, and 124], each passgate operatively coupled to receive the respective signals from the first and second outputs from the multiplexer circuit (In FIG. 1, a filter voltage 110 is connected to passgates 130, 132, and 134 and controls the speed of the oscillation of the three stage ring oscillator, composed of inverters 120, 122, and 124. An output voltage 112 will rise and fall from the power supply voltage to the ground voltage at a frequency determined by the gain of the oscillator multiplied by the value of the filter voltage. The gain will be a function of the transistor characteristics and therefore change when the transistor parameters change; Paragraph [0034] Line 1-9). The purpose of doing so is to use an improved voltage-controlled oscillator, to control a first voltage passing through the voltage-controlled oscillator based upon a digital tune bit used to control the voltage-controlled oscillator's gain, to provide new functionality and has minimal overhead and is less complex.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify Narayanan by introducing a ring oscillator comprising an odd number of serially coupled inverters as disclosed by Friend, because Friend teaches to include a ring oscillator comprising an odd number of serially coupled inverters uses an improved voltage-controlled oscillator, controls a first voltage passing through the voltage-controlled oscillator based upon a digital tune bit used to control the voltage-controlled oscillator's gain (Paragraph [0015]), provides new functionality and has minimal overhead and is less complex (Paragraph [0043]).
Allowable Subject Matter
Claims 8-13 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 8, the prior art of record as considered and understood by the examiner fails to teach or fairly suggest:
in a first mode comprising a voltage drop mapping mode, select the first input corresponding to the power voltage of the oscillator and select in sequential combination, each of a plurality of tap point inputs corresponding to ground tap inputs from the on-chip power conductor network; and
in the first mode, select the second input corresponding to the ground voltage of the oscillator and select in sequential combination, each of a plurality of tap points corresponding to power voltage tap inputs from the on-chip power conductor network; and
in a second mode comprising a short circuit detection mode, the control circuitry is operative to control the multiplexer circuit to output respective signals corresponding to a selected corresponding power voltage tap and ground tap pair, from the plurality of tap points, on the first and second outputs.
Narayanan (US 20150276824 A1) and Friend et al. (US 20100001804 A1), are regarded as the closest prior art to the invention of claim 8. Narayanan discloses, “An integrated circuit includes a functional circuit (10) having a power grid (20) with a set of power grid points (30.i) for monitoring (Abstract). FIG. 1A is a simplified pictorial diagram of conductive lines of a power grid of an integrated circuit chip and having power grid points for electrical monitoring and testing (Paragraph [0020] Line 1-4). In FIG. 1A, an integrated circuit 10 has a power grid 20, which is a layout of a material in the integrated circuit 10 that extends to a power connection for the integrated circuit of either common (ground GND), or a positive or negative voltage connection VDD. The power grid 20 may include a portion of conductor having an intersection or tap going to circuitry to be powered (Paragraph [0044] Line 1-7). In FIG. 1A, the power grid 20 on integrated circuit 10 is tapped at various points 30.i as shown by enlarged dots. In cross-section (not shown) the integrated circuit 10 may have a layer of transistors and one or more elevated layers (e.g., metal or polysilicon, etc) overlying the transistor layer and coupled to the transistor layer by vias (Paragraph [0045] Line 1-6). In some embodiments a respective IR drop monitoring circuit 100.i, such as that of FIG. 1B, is physically associated with, at, or near each of the taps (dots) 30.i of power grid 20 and used to detect the IR drop (voltage drop) at its tap 30.i. In some other embodiments, one or more shared IR drop monitoring circuits such as any one, some or all of circuits in any of FIGS. 2-11 and 15A is electrically coupled with at least one group of the taps (dots) 30.i and used to detect the IR drops (Paragraph [0045] Line 7-15). In FIG. 1B, note also that some embodiments couple one or more of the IR drop monitoring scan registers 120.i to a power management circuit 190. In this way, instances of excessive IR drop can not only be detected during scan test, but also the power management circuit 190 can respond to such instances of excessive drop during regular functional operation of the integrated circuit 10. Such power management response may reduce functional operating frequency or increase supply voltage, or both, such as by transitioning to a different voltage/clock frequency DVFS Operating Performance Point (OPP) or doing automatic voltage scaling AVS (Paragraph [0059] Line 1-11). In FIG. 3, replicating the shared circuitry of FIG. 2 once or just a few times reduces line lengths for routing tap lines 223.i.1 and 223.i.2 even further in some integrated circuits. Each mux 225.1, 225.2 serves a separate set of the taps 30.i so that a set of power grid point voltages VPGP_i.1 and another set of power grid point voltages VPGP_i.2 are fed to respective shared comparators 210.1 and 210.2 (Paragraph [0068] Line 1-7).” However, Narayanan does not disclose in a first mode comprising a voltage drop mapping mode, select the first input corresponding to the power voltage of the oscillator and select in sequential combination, each of a plurality of tap point inputs corresponding to ground tap inputs from the on-chip power conductor network; and in the first mode, select the second input corresponding to the ground voltage of the oscillator and select in sequential combination, each of a plurality of tap points corresponding to power voltage tap inputs from the on-chip power conductor network; and in a second mode comprising a short circuit detection mode, the control circuitry is operative to control the multiplexer circuit to output respective signals corresponding to a selected corresponding power voltage tap and ground tap pair, from the plurality of tap points, on the first and second outputs. Friend discloses, “electronic oscillators, and, more particularly, to voltage-controlled oscillators (Paragraph [0001] Line 1-3). In FIG. 1, a filter voltage 110 is connected to passgates 130, 132, and 134 and controls the speed of the oscillation of the three stage ring oscillator, composed of inverters 120, 122, and 124. An output voltage 112 will rise and fall from the power supply voltage to the ground voltage at a frequency determined by the gain of the oscillator multiplied by the value of the filter voltage. The gain will be a function of the transistor characteristics and therefore change when the transistor parameters change (Paragraph [0034] Line 1-9).” However Friend does not disclose in a first mode comprising a voltage drop mapping mode, select the first input corresponding to the power voltage of the oscillator and select in sequential combination, each of a plurality of tap point inputs corresponding to ground tap inputs from the on-chip power conductor network; and in the first mode, select the second input corresponding to the ground voltage of the oscillator and select in sequential combination, each of a plurality of tap points corresponding to power voltage tap inputs from the on-chip power conductor network; and in a second mode comprising a short circuit detection mode, the control circuitry is operative to control the multiplexer circuit to output respective signals corresponding to a selected corresponding power voltage tap and ground tap pair, from the plurality of tap points, on the first and second outputs. Therefore, the invention of Narayanan and Friend, even if modified, does not alone or in combination with the other art of record, teach or fairly suggest “in a first mode comprising a voltage drop mapping mode, select the first input corresponding to the power voltage of the oscillator and select in sequential combination, each of a plurality of tap point inputs corresponding to ground tap inputs from the on-chip power conductor network; and in the first mode, select the second input corresponding to the ground voltage of the oscillator and select in sequential combination, each of a plurality of tap points corresponding to power voltage tap inputs from the on-chip power conductor network; and in a second mode comprising a short circuit detection mode, the control circuitry is operative to control the multiplexer circuit to output respective signals corresponding to a selected corresponding power voltage tap and ground tap pair, from the plurality of tap points, on the first and second outputs.” and also in combination with all other elements in claim 8 distinguish the present invention from the prior art references.
Claims 9-13 are allowed by virtue of their dependence from claim 8.
Claims 3-7 and 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kernahan et al. (US 20040095164 A1) discloses, “POWER CONVERTER CIRCUITRY AND METHOD- [0001] This invention relates to switching power supplies or converters. In particular, this invention relates to a simple, robust switching power supply which is capable of providing power to a number of different regulated power sources within a given circuit. [0178] FIG. 3 shows a supply management controller of a type in accordance with this invention. As shown in FIG. 3, a ring oscillator includes inverters 301-1 through 301-15 connected in series. In an actual embodiment of this invention, the ring oscillator may include a larger number of series-connected inverters. [0179] In the structure of FIG. 3 a crystal 302 capable of oscillating at 32.768 KHz is connected by leads 303a and 303b to an inverting amplifier 304. Amplifier 304 provides a voltage across the crystal to cause the crystal to oscillate at 32.768 KHz, thereby causing the output signal from inverting amplifier 304 to oscillate at the frequency of crystal 302. The output signal of the ring oscillator is divided by eight in divided-by-eight circuit 305 and then sent to phase comparator 306, which receives also the output signal from oscillator 302. Thus the control frequency of the ring oscillator is 262.144 KHz, eight times the normal frequency of crystal 302. [0180] The normal operating frequency of the ring oscillator is generally selected to be approximately the 262 Khz. The phase comparator 306 senses the phase difference between the phase of the divided-by-eight output signal from the ring oscillator and the phase of the signal from crystal oscillator 302. Phase comparator 306 provides this phase difference in an output signal on lead 306a to Vcc control circuit 307 to correct any deviation in the frequency of the ring oscillator's divided-by-eight output signal from the control frequency 32.768 Khz associated with crystal oscillator 302-However Kernahan does not disclose voltage drop detection circuitry, operative to select, by a multiplexer circuit, each of a plurality of tap points from the on-chip power conductor network and in response to a plurality of selected tap points, provide, by control circuitry, data representing a frequency corresponding to a voltage level of each of the plurality of selected tap points[ 1], wherein the frequency is produced by a ring oscillator comprising at least one passgate operatively coupled to receive respective signals from the plurality of selected tap points.”
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NASIMA MONSUR whose telephone number is (571)272-8497. The examiner can normally be reached 10:00 am-6:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eman Alkafawi can be reached at (571) 272-4448. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NASIMA MONSUR/Primary Examiner, Art Unit 2858
