DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claims 1, 3, 8, 10, 15, and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Manganelli, et al (US 20210335432 A1), hereinafter Manganelli.
Regarding independent claim 1, Manganelli teaches a system (FIG. 1) comprising:
a memory device (FIG. 1, 110); and
a processing device (FIG. 1, 105), operatively coupled with the memory device, to perform operations (¶ [0039]) comprising:
performing a first programming operation (FIG. 11, 1102; ¶ [0071] teaches “A first portion may be programmed at a first location in the NAND, a second portion at a second location, a third portion at a third location, and a fourth portion at a fourth location. The first location, second location, third location, and fourth location may be selected such that the first portion, second portion, third portion, and fourth portion are stored in memory cells that are on different page lines and different planes with respect to each other.”) on a first set of cells (FIG. 7, 710) addressable by a first wordline (FIG. 7, Page Line (PL) 0; see ¶ [0069] related PLs to WLs) of a first plane (FIG. 7, Plane 0) of the memory device;
identifying a predefined index shift value (shift value of 1 is illustrated in FIGS. 7-8) associated with the first wordline;
determining, by applying the predefined index shift value to a first index value of the first wordline (FIG. 7, index 0 (of PL0)), a second index value of a second wordline (FIG. 7, index 1 (of PL1)) of a second plane (FIG. 7, Plane 1) of the memory device (see FIG. 7, in which a predefined index shift value of 1 is used and the first index value of 0 (WL/PL index 0 used to program “FIRST P1”) is “shifted” by the index shift value of 1 to create the second index value of 1 (WL/PL index 1 used to program “SECOND P1”); ¶ [0073]); and
performing a second programming operation (FIG. 11, 1104; ¶ [0071]) on a second set of cells (FIG. 7, 715) addressable by the second wordline of the second plane.
Regarding independent claim 8, Manganelli teaches a method (FIG. 11) comprising:
performing a first programming operation (FIG. 11, 1102; ¶ [0071]) on a first set of cells (FIG. 7, 710) addressable by a first wordline (FIG. 7, Page Line (PL) 0; see ¶ [0069] related PLs to WLs) of a first plane (FIG. 7, Plane 0) of a memory device (FIG. 1, 110);
identifying a predefined index shift value (shift value of 1 is illustrated in FIGS. 7-8) associated with the first wordline;
determining, by applying the predefined index shift value to a first index value of the first wordline (FIG. 7, index 0 (of PL0)), a second index value of a second wordline (FIG. 7, index 1 (of PL1)) of a second plane (FIG. 7, Plane 1) of the memory device (see FIG. 7, in which a predefined index shift value of 1 is used and the first index value of 0 (WL/PL index 0 used to program “FIRST P1”) is “shifted” by the index shift value of 1 to create the second index value of 1 (WL/PL index 1 used to program “SECOND P1”); ¶ [0073]); and
performing a second programming operation (FIG. 11, 1104; ¶ [0071]) on a second set of cells (FIG. 7, 715) addressable by the second wordline of the second plane.
Regarding independent claim 15, Manganelli teaches a non-transitory computer-readable storage medium (FIG. 17, 1704, 1706, 1721; ¶ [0029]) comprising instructions (FIG. 17, 1724) that, when executed by a processing device (FIG. 17, 1702; FIG. 1, 105), cause the processing device to perform operations (¶ [0039]) comprising:
performing a first programming operation (FIG. 11, 1102; ¶ [0071]) on a first set of cells (FIG. 7, 710) addressable by a first wordline (FIG. 7, Page Line (PL) 0; see ¶ [0069] related PLs to WLs) of a first plane (FIG. 7, Plane 0) of a memory device (FIG. 1, 110);
identifying a predefined index shift value (shift value of 1 is illustrated in FIGS. 7-8) associated with the first wordline;
determining, by applying the predefined index shift value to a first index of the first wordline value (FIG. 7, index 0 (of PL0)), a second index value of a second wordline (FIG. 7, index 1 (of PL1)) of a second plane (FIG. 7, Plane 1) of the memory device (see FIG. 7, in which a predefined index shift value of 1 is used and the first index value of 0 (WL/PL index 0 used to program “FIRST P1”) is “shifted” by the index shift value of 1 to create the second index value of 1 (WL/PL index 1 used to program “SECOND P1”); ¶ [0073]); and
performing a second programming operation (FIG. 11, 1104; ¶ [0071]) on a second set of cells (FIG. 7, 715) addressable by the second wordline of the second plane.
Regarding claim 3, Manganelli teaches the limitations of claim 1.
Manganelli further teaches each of the first index value and the second index value corresponds to an identifier of a physical location of the first wordline and the second wordline, respectively (¶ [0069] teaches “a page line is a logical construct that identifies a group of pages comprising pages at a same position in each plane in a group of planes. Thus, for example, the first page in planes 0-3 is identified by page line 0. A page is made up of memory cells belonging to the same word line.” Therefore, Page Line index 0 identifies the first page in planes 0..3 and corresponds to WL index 0 in each of planes 0..3.).
Regarding claim 10, Manganelli teaches the limitations of claim 8.
Manganelli further teaches each of the first index value and the second index value corresponds to an identifier of a physical location of the first wordline and the second wordline, respectively (¶ [0069] teaches “a page line is a logical construct that identifies a group of pages comprising pages at a same position in each plane in a group of planes. Thus, for example, the first page in planes 0-3 is identified by page line 0. A page is made up of memory cells belonging to the same word line.” Therefore, Page Line index 0 identifies the first page in planes 0..3 and corresponds to WL index 0 in each of planes 0..3.).
Regarding claim 17, Manganelli teaches the limitations of claim 15.
Manganelli further teaches each of the first index value and the second index value corresponds to an identifier of a physical location of the first wordline and the second wordline, respectively (¶ [0069] teaches “a page line is a logical construct that identifies a group of pages comprising pages at a same position in each plane in a group of planes. Thus, for example, the first page in planes 0-3 is identified by page line 0. A page is made up of memory cells belonging to the same word line.” Therefore, Page Line index 0 identifies the first page in planes 0..3 and corresponds to WL index 0 in each of planes 0..3.).
Regarding claim 18, Manganelli teaches the limitations of claim 15.
Manganelli further teaches to determine the second index value of the second wordline, the processing device is to perform operations further comprising:
shifting the first index value of the first wordline by the predefined index shift value associated with the first wordline (see FIG. 7, in which a predefined index shift value of 1 is used and the first index value of 0 (WL/PL index 0 used to program “FIRST P1”) is “shifted” by the index shift value of 1 to create the second index value of 1 (WL/PL index 1 used to program “SECOND P1”); ¶ [0073]).
Allowable Subject Matter
5. Claims 2, 4-7, 9, 11-14, 16, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
6. The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 2, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of identifying the predefined index shift value associated with the first wordline comprises:
retrieving, from an entry of a metadata structure, the predefined index shift value associated with the first wordline, wherein the metadata structure comprises a plurality of entries, each entry associating an index value of a wordline of the memory device with a predefined index shift value. Claim 4 depends on claim 2.
Regarding claim 5, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein the metadata structure comprises a plurality of entries, each entry associating an index value of a wordline of the memory device with a predefined index shift value.
Regarding claim 6, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of the predefined index shift value associated with the first wordline is computed based on an error count associated with a plane of the memory device.
Regarding claim 7, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of the predefined index shift value associated with the first wordline is computed based on an error count associated with a die of the memory device.
Regarding claim 9, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of identifying the predefined index shift value associated with the first wordline comprises:
retrieving, from an entry of a metadata structure, the predefined index shift value associated with the first wordline, wherein the metadata structure comprises a plurality of entries, each entry associating an index value of a wordline of the memory device with a predefined index shift value. Claim 11 depends on claim 9.
Regarding claim 12, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein the metadata structure comprises a plurality of entries, each entry associating an index value of a wordline of the memory device with a predefined index shift value.
Regarding claim 13, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of the predefined index shift value associated with the first wordline is computed based on an error count associated with a plane of the memory device.
Regarding claim 14, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of the predefined index shift value associated with the first wordline is computed based on an error count associated with a die of the memory device.
Regarding claim 16, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of identify the predefined index shift value associated with the first wordline, the processing device is to perform operations further comprising:
retrieving, from an entry of a metadata structure, the predefined index shift value associated with the first wordline, wherein the metadata structure comprises a plurality of entries, each entry associating an index value of a wordline of the memory device with a predefined index shift value.
Regarding claim 19, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein the metadata structure comprises a plurality of entries, each entry associating an index value of a wordline of the memory device with a predefined index shift value.
Regarding claim 20, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of the predefined index shift value associated with the first wordline is computed based on an error count associated with a plane of the memory device.
Citation of Relevant Art
7. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Karakulak (US 20160147582 A1) teaches generating offset wordline groups based on a table of error counts. The offset is determined from error counts for each word line, and it varies from WL to WL; however, the read voltage is adjusted as a result rather than the index shift value to the next WL to be programmed.
Helmick (US 20210334203 A1) teaches an L2P table to locate the first WL, but offsets to subsequent WLs are calculated rather than determined from a lookup table associating WLs with offsets. Note the calculation is not based on an error count.
Balakrishnan (US 20220129388 A1) teaches in Figures 25 and 26 accessing a memory location based on metadata (L2P table) indicating an offset to the page within the metablock, but does not teach an “index shift value” in the metadata.
Chen (US 20200073794 A1) teaches in ¶ [0014] “each of the L2P mapping tables comprises a plurality of consecutive logical addresses and/or corresponding physical addresses, and each physical address is an index of a block and a page index of the block,” but does not teach an “index shift value” in the metadata.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMIR ZARABIAN can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827