DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 1/21/2026 have been fully considered but they are not persuasive.
Regarding the rejections under §112, Applicant’s arguments are persuasive and the rejection has been withdrawn.
Regarding the rejections under §102, Applicant argues that:
“… Palmer does not disclose a circuit "wherein the track path includes components that are substantially similar to those of the data path, and a phase delay between the signals travelling in the track path and the data path is within a predetermined range based on structural configuration of the substantially similar components." (Claim 1).
With respect to these features, the Office Action cited to paragraph [0055] of Palmer, which describes that "forwarded clock has nominally the same propagation time as the data across a wire, and is used to re-time the data into receiving flip-flops." (Office Action, page 4).
In Palmer, "the calibration system 300 measures the delay offsets of the clock and data wires using phase detection techniques, and corrects the delays, as needed to meet timing constraints, using the configurable delay circuits 100 that are placed in series with the wires of the on-chip interconnect." (Palmer, paragraph [0059]).
However, the cited circuit does not operate such that "a phase delay between the signals travelling in the track path and the data path is within a predetermined range based on structural configuration of the substantially similar components." (Claim 1)… The delay reduction in Palmer appears to be based on receiving input signals and generating output signals, which is not "based on structural configuration of the substantially similar components." (Claim 1, emphasis added).
Palmer teaches:
“The forwarded clock has nominally the same propagation time as the data across a wire…” [55]. Hence the clock wire and the data wire are substantially similar.
The configurable delay stages 100 in the clock path 302 and data path 301 of Figure 3A are structurally identical (Figures 1 and 2) and capable of providing different delay amounts based on 320 ([36]-[51]).
A “predetermined acceptable delay variation and clock to data delay offsets before, during, and after calibration” via configurable delay circuit 100 ([20], [51], [68]-[69] and Figure 3D). Hence, Palmer teaches the predetermined range as claimed.
Therefore, the recited claim limitations are considered met since 1) the clock wire and data wire have the same propagation time and 2) the configurable delay stages corresponding to the clock wire and the data wire are structurally identical, wherein said configurable delay stages provide different delay times (via a plurality of structural configurations) in order to maintain an acceptable delay variation or clock to data delay offset.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 9-14 and 17-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Palmer et al (US 2014/0070862).
For claim 1, Palmer teaches a circuit (Figure 3A), comprising:
a first clock path (from top output of 305 to the output of 100 in path 304) configured to receive a first clock signal (ClkQ_clk), and provide an adjusted version of the first clock signal (output of 100 within 304) with a first clock phase (as understood by examination of Figure 3A);
a second clock path (either the path from the top output of 325 to CLKQ_data or the path from the output of the leftmost inverter in 304 to the output of 100 within 304, see claim 3 below) configured to receive a second clock signal (top output of 325 or output of leftmost inverter, respectively), and provide an adjusted version of the second clock signal with a second clock phase related to the first clock phase (as understood by Figures 3-4 and [0075]);
a data path (301) configured to receive a data signal (output of multiplexer within 312), and provide an adjusted version of the data signal (deserialized data generated by 314) having a third clock phase (phase of clkQ_CLK, [0057]); and
a track path (302) configured to receive a third clock signal (ClkI_clk or CLKQ_clk based upon selection by 305, [0058]), and provide an adjusted version of the third clock signal with the first clock phase (output of 100 within path 302);
wherein the track path includes components that are substantially similar to those of the data path (see Response to Arguments section above), and a phase delay between the signals travelling in the track path and the data path is within a predetermined range based on structural configuration of the substantially similar components. (see Response to Arguments section above).
For claim 2, Palmer further teaches:
the substantially similar components are configured such that the track path is a structural replica of the data path (see Response to Arguments section above)
For claim 3, Palmer further teaches:
a difference between the first clock phase and the second clock phase is 90 degrees or 180 degrees (when the second path of claim 1 is the path from the output of the leftmost inverter in 304 to the output of 100 within 304, as understood by examination of Figure 3A and 4A).
For claim 4, Palmer further teaches:
a phase detector (although not illustrated, required to perform 505 of Figure 5) configured to receive the adjusted version of the first clock signal through the first clock path, and the adjusted version of the third clock signal through the track path ([0059]-[0060] and [0081]-[0082]).
For claim 5, Palmer further teaches:
the phase detector is further configured to determine whether the first clock phase and the third clock phase are in phase ([0059]-[0060] and [0081]-[0082]).
For claim 9, Palmer further teaches:
a first duty cycle corrector/quadrature error corrector (DCC/QEC) operatively coupled to the first clock path (305), and a second DCC/QEC operatively coupled to the second clock path (CDC 100 in path 304).
For claim 10, Palmer further teaches:
at least one de-serializer (within 314, [0057]) configured to receive the adjusted version of the data signal and the adjusted version of the first clock signal (as understood by examination of Figure 3A).
For claim 11, Palmer teaches a circuit (Figure 3A), comprising:
a receiver (all of Figure 3A except for 312, the connection between ClkI_data and 312, the connection between the input to 301 and the output of 312 and the deserializer, see rejection of claim 18 below) coupled to a transmitter (312) through a plurality of connection structures (connection between ClkI_data and 312, connection between the input to 301 and the output of 312);
wherein the receiver includes:
a first clock path (from top output of 305 to the output of 100 in path 304) configured to receive a first clock signal (ClkQ_clk), and provide an adjusted version of the first clock signal (output of 100 within 304) with a first clock phase (as understood by examination of Figure 3A);
a second clock path (either the path from the top output of 325 to CLKQ_data or the path from the output of the leftmost inverter in 304 to the output of 100 within 304, see claim 12 below) configured to receive a second clock signal (top output of 325 or output of leftmost inverter, respectively), and provide an adjusted version of the second clock signal with a second clock phase related to the first clock phase (as understood by Figures 3-4 and [0075]);
a data path (301) configured to receive a data signal (output of multiplexer within 312), and provide an adjusted version of the data signal (deserialized data generated by 314) having a third clock phase (phase of clkQ_CLK, [0057]); and
a track path (302) configured to receive a third clock signal (ClkI_clk or CLKQ_clk based upon selection by 305, [0058]), and provide an adjusted version of the third clock signal with the first clock phase (output of CDC 100 within path 302);
wherein the track path includes components substantially similar to those of the data path and configured to cause a phase delay between the signals travelling in the track path and the data path to be within a predetermined range (see Response to Arguments section above)
For claim 12, Palmer further teaches:
a difference between the first clock phase and the second clock phase is 90 degrees, or the difference between the first clock phase and the second clock phase is 180 degrees (as understood by the rejection of claim 11 and by examination of Figure 3A and 4A).
For claim 13, Palmer further teaches:
a phase detector (although not illustrated, required to perform 505 of Figure 5) configured to receive the adjusted version of the first clock signal through the first clock path, and the adjusted version of the third clock signal through the track path ([0059]-[0060] and [0081]-[0082]).
For claim 14, Palmer further teaches:
the phase detector is further configured to determine whether the first clock phase and the third clock phase are in phase ([0059]-[0060] and [0081]-[0082]).
For claim 17, Palmer further teaches:
a first duty cycle corrector/quadrature error corrector (DCC/QEC) operatively coupled to the first clock path (305), and a second DCC/QEC operatively coupled to the second clock path (CDC 100 in path 304).
For claim 18, Palmer further teaches:
at least one de-serializer (within 314, [0057]) configured to receive the adjusted version of the data signal and the adjusted version of the first clock signal (as understood by examination of Figure 3A).
For claim 19, Palmer teaches a method, comprising:
receiving a first clock signal (ClkQ_clk) and providing an adjusted version of the first clock signal with a first clock phase (output of 100 within 304), through a first clock path (from top output of 305 to the output of 100 in path 304);
receiving a second clock signal (top output of 325) and providing an adjusted version of the second clock signal with a second clock phase related to the first clock phase (CLKQ_data), through a second clock path (from the top output of 325 to CLKQ_data);
receiving a data signal (output of 312) and providing an adjusted version of the data signal having a third clock phase (output of CDC 100 of path 301), through a data path (301); and
receiving a third clock signal (ClkI_clk or CLKQ_clk based upon selection by 305, [0058]) and providing an adjusted version of the third clock signal with the first clock phase (output of CDC 100 within path 302), through a track path (302);
wherein the track path includes components that are substantially similar to those of the data path, and a phase delay between the signals travelling in the track path and the data path is within a predetermined range based on structural configuration of the substantially similar components (see Response to Arguments section above).
For claim 20, Palmer further teaches:
providing the adjusted version of the first clock signal through the first clock path, and the adjusted version of the third clock signal through the track path (as understood by the rejection of claim 19 above); and
determining whether the first clock phase and the third clock phase are in phase (Figure 5, ([0059]-[0060] and [0081]-[0082]).
Allowable Subject Matter
Claims 6-8 and 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL CALRISSIAN PUENTES whose telephone number is (571)270-5070. The examiner can normally be reached M-F 9-6:30 (flex).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL C PUENTES/Primary Examiner, Art Unit 2849