DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 and 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 (and for similar reasons, claim 19) recites “a data path configured to…provide an adjusted version of the data signal having a third clock phase; and a track path configured to…provide an adjusted version of the third clock signal with the first clock phase to calibrate skew between the track path and the data path…the third clock phase mimics the first clock phase to compensate for mismatch between the track path and the data path”. It is unclear what the scope of “mimics” and “mismatch” are in this context. For example, whether “mismatch” strictly refers to phase and if “mimics” is identical in scope with “is equal to”.
Furthermore, it is unclear whether mismatch compensation is required to be performed in either one or both of the data path and the track path such that:
the phase of the data path is adjusted to match the phase of the track path (“adjusted version of the data signal having a third clock phase…the third clock phase mimics the first clock phase to compensate for mismatch”); and
the phase of the track path is adjusted to match the phase of the data path (“a track path configured to…provide an adjusted version of the third clock signal with the first clock phase to calibrate skew between the track path and the data path”).
For the purposes of examination, Examiner will interpret this limitation as requiring the third clock phase is equal to the first clock phase by phase adjustments to both the data path and track path in accordance with conditions a and b above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 11-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Palmer et al (US 2014/0070862) in view of Leung et al (US 5,485,490).
For claim 11, Palmer teaches a circuit (Figure 3A), comprising:
a receiver (all of Figure 3A except for Half-rate “I” data within 312, the flip-flops within 312 and the deserializer within 314, see rejection of claim 18 below) coupled to a transmitter (Half-rate “I” data within 312 and the flip-flops within 312) through a plurality of connection structures (two input lines to the multiplexer within 312);
wherein the receiver includes:
a first clock path (305 to the output of 100 in path 304) configured to receive a first clock signal (ClkQ_clk or Clkl_clk based upon selection by 305, [0058]), and provide an adjusted version of the first clock signal (output of 100 within 304) with a first clock phase (as understood by examination of Figure 3A);
a second clock path (either the path from the top output of 325 to CLKQ_data or the path from the output of the leftmost inverter in 304 to the output of 100 within 304, see claim 12 below) configured to receive a second clock signal (top output of 325 or output of leftmost inverter, respectively), and provide an adjusted version of the second clock signal with a second clock phase related to the first clock phase (as understood by Figures 3-4 and [0075]);
a data path (from the input of the multiplexer within 312 to the deserialized data generated by 314) configured to receive a data signal (corresponding to one of the input signals of the multiplexer within 312), and provide an adjusted version of the data signal (deserialized data generated by 314) having a third clock phase (phase of clkQ_CLK, [0057]); and
a track path (302) configured to receive a third clock signal (ClkI_clk or CLKQ_clk based upon selection by 305, [0058]), and provide an adjusted version of the third clock signal with the first clock phase (output of CDC 100 within path 302);
wherein the track path includes components substantially similar to those of the data path and configured to cause a phase delay between the signals travelling in the track path and the data path to be within a predetermined range (as explained below).
Palmer fails to teach:
a similarity between a first amplifier in the data path and a second amplifier in the track path.
It is noted that Palmer’s track path 302 has nominally the same propagation time as the data path 301 since they are structurally identical ([55] and Figure 3) and capable of providing configurable delay amounts based on 320 ([36]-[51]).
However, Leung teaches (Figure 2) using amplifiers (124a, 124b, 124c) respectively within a plurality of clock paths (from 120 to 60, from 121 to 62, from 121 to 63) to amplify clock signals (outputs of 122a, 122b and 122c).
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to include an amplifier in each of Palmer’s clock paths and data path in order to compensate for signal loss across the clock and data paths.
For claim 12, Palmer in view of Leung as cited above teaches the limitations of claim 11 and Palmer further teaches:
a difference between the first clock phase and the second clock phase is 90 degrees, or the difference between the first clock phase and the second clock phase is 180 degrees (as understood by the rejection of claim 11 and by examination of Figure 3A and 4A).
For claim 13, Palmer in view of Leung as cited above teaches the limitations of claim 11 and Palmer further teaches:
a phase detector (although not illustrated, required to perform 505 of Figure 5) configured to receive the adjusted version of the first clock signal through the first clock path, and the adjusted version of the third clock signal through the track path ([0059]-[0060] and [0081]-[0082]).
For claim 14, Palmer in view of Leung as cited above teaches the limitations of claim 13 and Palmer further teaches:
the phase detector is further configured to determine whether the first clock phase and the third clock phase are in phase ([0059]-[0060] and [0081]-[0082]).
For claim 15, Palmer in view of Leung as cited above teaches the limitations of claim 11 and further teaches:
the data path includes a first amplifier (see rejection of claim 11 above), a first multiplexer (within 312), one or more first de-skew stages (100), a first delay line circuit (signal line causing propagation delay), and one or more first buffers (as illustrated in Figure 3A), and wherein the track path includes a second amplifier (see rejection of claim 11 above), a second multiplexer (305), one or more second de-skew stages (100), a second delay line circuit (signal line causing propagation delay), and one or more second buffers (as illustrated in Figure 3A).
For claim 16, Palmer in view of Leung as cited above teaches the limitations of claim 15 and further teaches:
the first amplifier is identical to the second amplifier, the first multiplexer is identical to the second multiplexer, the one or more first de-skew stages are identical to the one or more second de-skew stages, respectively, the first delay line circuit is identical to the second delay line circuit, and the one or more first buffers are identical to the one or more second buffers, respectively (as discussed in the rejections of claims 11 and 15 above).
For claim 17, Palmer in view of Leung as cited above teaches the limitations of claim 11 and Palmer further teaches:
a first duty cycle corrector/quadrature error corrector (DCC/QEC) operatively coupled to the first clock path (one or more buffers within 304), and a second DCC/QEC operatively coupled to the second clock path (CDC 100 in path 304).
For claim 18, Palmer in view of Leung as cited above teaches the limitations of claim 11 and Palmer further teaches:
at least one de-serializer (within 314, [0057]) configured to receive the adjusted version of the data signal and the adjusted version of the first clock signal (as understood by examination of Figure 3A).
Allowable Subject Matter
Claims 1-10 and 19-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. The prior art fails to teach the limitations discussed in the 112 rejection above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Hsu (US 2022/0294435) teaches deskewing signals in a multi-die system.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL CALRISSIAN PUENTES whose telephone number is (571)270-5070. The examiner can normally be reached M-F 9-6:30 (flex).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached at (571) 270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL C PUENTES/Primary Examiner, Art Unit 2836
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