DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No.12,021,019. Although the claims at issue are not identical, they are not patentably distinct from each other because regarding claim 1, U.S. Patent No.12,021,019 discloses a small outline transistor (SOT) package comprising: a package substrate having a die pad and leads spaced from the die pad arranged along two opposite sides of the die pad; die pad straps extending from two opposing ends of the die pad, the leads lying in a first plane, first portions of the die pad straps lying in a second plane that is spaced from and parallel to the first plane, and the die pad straps having angled portions extending from the first portions to the die pad that lies in a third plane that is spaced from and parallel to the second plane in a direction away from the first plane; a semiconductor die mounted to the die pad and electrically connected to the leads via electrical connections; and mold compound covering the semiconductor die, the electrical connections, a portion of the leads, wherein a portion of the die pad and ends of the first portions of the die pad straps are exposed from the mold compound, and wherein a portion of the die pad straps that lie in the third plane is exposed from the mold compound.
Regarding claims 2-8, U.S. Patent No.12,021,019 discloses in claims 2-11, a package wherein the leads include portions extending from the mold compound that forms terminals of the SOT package; wherein the leads are shaped outside the mold compound to extend alongside a package body formed by the mold compound to form the terminals, the terminals having feet portions configured for surface mounting to a circuit board; wherein the semiconductor die is electrically connected to the leads via wire bonds or ribbon bonds; wherein the package substrate is a metal lead frame; wherein the metal lead frame comprises copper, stainless steel, steel, alloy 42, or alloys thereof; wherein the mold compound forms a package body with a width less than 2 millimeters; wherein the die pad has a width less than 1 millimeter.
Regarding claim 9, U.S. Patent No.12,021,019 discloses in claim 12, a small outline transistor (SOT) package comprising: a package substrate having a die pad and leads spaced from the die pad arranged along two opposite sides of the die pad; die pad straps extending from two opposing ends of the die pad, the leads lying in a first plane, first portions of the die pad straps lying in a second plane that is spaced from and parallel to the first plane, and the die pad straps having angled portions extending from the first portions to the die pad that lies in a third plane that is spaced from and parallel to the second plane in a direction away from the first plane; a semiconductor die mounted to the die pad and electrically connected to the leads via electrical connections; and mold compound covering the semiconductor die, the electrical connections, a portion of the leads, wherein a portion of the die pad straps that lie in the third plane is exposed from the mold compound.
Regarding claims 10-13, U.S. Patent No.12,021,019 discloses in claims 13-16,
a package wherein a portion of the die pad and ends of the first portions of the die pad straps are exposed from the mold compound; wherein the leads include portions extending from the mold compound that forms terminals of the SOT package; wherein the leads are shaped outside the mold compound to extend alongside a package body formed by the mold compound to form the terminals, the terminals having feet portions configured for surface mounting to a circuit board; wherein the portion of the die pad exposed from the mold compound functions as a heat dissipation path from the package.
Regarding claim 14, U.S. Patent No.12,021,019 discloses in claim 17, a method, comprising: mounting a semiconductor die to a die side surface of a die pad of a package substrate, the package substrate having leads arranged on opposite sides of the die pad and having die pad straps coupled to opposing ends of the die pad, the leads in a first plane, the die pad straps having first portions in a second plane that is spaced from and parallel to the first plane in a direction towards the die pad, and having angled portions extending from the first portion to the die pad, and the die pad in a third plane that is spaced from and parallel to the second plane and in a direction away from the first plane, the die pad having a backside surface opposite the die side surface; forming electrical connections coupling bond pads on a device side surface of the semiconductor die to the leads; covering the semiconductor die, the die side surface of the die pad, and the electrical connections with mold compound to form a packaged semiconductor device, the leads having portions extending from the mold compound to form terminals, the backside surface of the die pad exposed from the mold compound; separating the packaged semiconductor device from the remaining portions of the package substrate; and forming the leads outside the mold compound to shape the terminals for surface mounting the packaged semiconductor device.
Regarding claims 15-17, U.S. Patent No.12,021,019 discloses in claims 18-20,
A method further comprising: using the terminals, mounting the packaged semiconductor device to a circuit board, and thermally coupling the backside surface of the die pad to the circuit board; wherein mounting the packaged semiconductor device comprises soldering the terminals to conductive lands on the circuit board, and thermally coupling the backside surface of the die pad to a thermal pad on the circuit board; wherein thermally coupling the backside surface of the die pad to a thermal pad on the circuit board further comprises soldering the backside surface of the die pad to the thermal pad on the circuit board.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARC-ANTHONY ARMAND whose telephone number is (571)272-5178. The examiner can normally be reached 8am-5pm.
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MARC - ANTHONY ARMAND
Primary Examiner
Art Unit 2813
/MARC-ANTHONY ARMAND/Primary Examiner, Art Unit 2813
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