Attorney’s Docket Number: 083710-4275
Filing Date: 6/26/2024
Claimed Foreign Priority Date: 1/11/2022 (JP2022-002621)
Inventor: Noda
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the application filed 6/26/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first
inventor to file provisions of the AIA . In the event the determination of the status of the application as
subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing
from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art
relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites the limitation "…the group consisting of carbon, nitrogen…" in lines 6-7. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, this line will be construed to recite “…a group consisting of carbon, nitrogen…”.
Claim 16 recites the limitation "…the at least one selected from the group consisting of the first source…" in lines 5-6. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, this line will be construed to recite "…at least one selected from the first source…”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-7, 11-12, 21-23, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto (US 20100025569 A1) in view of Miyagawa (US 20060192234 A1) further in view of Tamura (US 20090267119 A1).
Regarding claim 1, Matsumoto (see, e.g., figs. 1-2) shows most aspects of the instant invention, including an imaging device comprising:
a pixel region (e.g., pixel portion 12) including a pixel substrate portion (e.g., substrate 11 region within pixel portion 12) and a pixel transistor (e.g., amplification transistor Amp in pixel portion 12) located in the pixel substrate portion (e.g., substrate 11 region within pixel portion 12, see fig. 1); and
a first peripheral region (e.g., peripheral circuit portion 13) including a first peripheral substrate portion (e.g., substrate 11 region within peripheral circuit portion 13 comprising N channel low-breakdown voltage transistor, see fig. 2) and at least one first peripheral transistor (e.g., collection of transistors in the peripheral circuit portion 13, e.g., at least the N channel low-breakdown voltage transistor in peripheral circuit portion 13) located in the first peripheral substrate portion (e.g., substrate 11 region within peripheral circuit portion 13 comprising N channel low-breakdown voltage transistor, see fig. 2), wherein signals are transmitted (see, e.g., paragraphs 20 or 124) between the first peripheral region (e.g., peripheral circuit portion 13) and the pixel region (e.g., pixel portion 12);
the pixel transistor (e.g., amplification transistor Amp in pixel portion 12) and the at least one first peripheral transistor (e.g., N channel low-breakdown voltage transistor in peripheral circuit portion 13) each include a gate (e.g., gate electrode 32 + gate oxide of amplification transistor Amp, see fig. 1, and gate electrode 52 + gate oxide of N channel low-breakdown voltage transistor);
the at least one first peripheral transistor (e.g., N channel low-breakdown voltage transistor in peripheral circuit portion 13) includes, in the first peripheral substrate portion (e.g., substrate 11 region within peripheral circuit portion 13 comprising N channel low-breakdown voltage transistor, see fig. 2), a first source (e.g., source region 54), a first drain (e.g., drain region 55), and a first channel region (e.g., channel region between source region 54 and drain region 55) located between the first source (e.g., source region 54) and the first drain (e.g., drain region 55);
Matsumoto (see, e.g., figs. 1-2), however, fails to explicitly show a gate length of the at least one first peripheral transistor is less than a gate length of the pixel transistor, and a first strain-introducing layer that brings a strain to the first channel region.
Miyagawa (see, e.g., fig. fig. 4 and paragraphs 44-45), in a similar device to Matsumoto, teaches a gate length of a peripheral transistor is less than a gate length of a pixel transistor (see, e.g., paragraph 45 “…thereby enabling a gate length of the transistor in the peripheral circuitry reason to be shortened. In such a case, a gate length of the amplification transistor in pixels is likely to be longer than that of the transistor in the peripheral circuitry region”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the gate difference configuration of Miyagawa within the setup of Matsumoto, in order to manipulate the driving voltage relationship between the pixel and peripheral region of the device as desired (also see paragraph 44 of Miyagawa).
Matsumoto in view of Miyagawa, however, fails to teach a first strain-introducing layer that brings a strain to the first channel region.
Tamura (see, e.g., figs. 3-5), in a similar device to Matsumoto in view of Miyagawa, teaches a first strain-introducing layer (e.g., SiGe films 102 + paragraphs 41-43) that brings a strain (e.g., strain magnitudes of paragraphs 42-43) to a first channel region.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the strain-introducing layer and strain engineering of Tamura within the at least one peripheral transistor of Matsumoto in view of Miyagawa, in order to enhance the mobility and operation speed of the transistor within the device (also see paragraphs 3 and 42-43 of Tamura).
Regarding claim 3, Tamura (see, e.g., figs. 3) teaches wherein the first strain-introducing layer (e.g., SiGe film 102) is an epitaxial layer (see, e.g., paragraph 170 “Semiconductor materials to be buried in the source/drain regions of the p-channel transistor have larger lattice constant than silicon forming the substrate and can be grown epitaxially with respect to the substrate”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the epitaxial formation of Tamura within the first strain-introducing layer of Matsumoto in view of Miyagawa further in view of Tamura, as epitaxial growth was a well-known technique at the time of filing the invention to form a strain-introducing layer, as taught by Tamura.
Regarding claim 4, Tamura (see, e.g., figs. 3-5) teaches wherein the first strain-introducing layer (e.g., SiGe film 102) is a crystal layer of silicon germanium.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the silicon germanium of Tamura within the first strain-introducing layer of Matsumoto in view of Miyagawa further in view of Tamura, as silicon germanium was a well-known material at the time of filing the invention to use as a strain introducing layer, as taught by Tamura.
Regarding claim 5, Tamura (see, e.g., figs. 3-5) teaches the first strain-introducing layer is a crystal layer of Si1-X-GeX, and X is greater than 0 and less than 1 (e.g., note that since the ratio is 80% silicon and 20% Germanium, X is .2).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the silicon-germanium composition ratio of Tamura within the first strain-introducing layer of Matsumoto in view of Miyagawa further in view of Tamura, in order to manipulate the exact lattice constant and strain profile within the device as desired.
Regarding claim 6, Tamura (see, e.g., figs. 3-5) teaches the first strain-introducing layer is a crystal layer of Si1-X-GeX, and X is greater than or equal to 0.1 and less than or equal to .8 (e.g., note that since the ratio is 80% silicon and 20% Germanium, X is .2).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the silicon-germanium composition ratio of Tamura within the first strain-introducing layer of Matsumoto in view of Miyagawa further in view of Tamura, in order to manipulate the exact lattice constant and strain profile within the device as desired.
Regarding claim 7, Matsumoto (see, e.g., figs. 1-2) shows the first peripheral substrate portion (e.g., substrate 11 region within peripheral circuit portion 13 comprising N channel low-breakdown voltage transistor, see fig. 2) includes a first foundation layer (e.g., substrate region beneath N channel low-breakdown voltage transistor).
Tamura (see, e.g., figs. 3-5) teaches a first foundation layer (e.g., silicon substrate 100) is adjacent to the first strain-introducing layer (e.g., SiGe film 102 + paragraphs 41-43) includes a first foundation layer (e.g., silicon substrate 100) adjacent to the first strain-introducing layer (e.g., SiGe film 102 + paragraphs 41-43), and a lattice constant of a crystal lattice of the first strain-introducing layer (e.g., SiGe film 102 + paragraphs 41-43) is different (see, e.g., paragraphs 42-45 or paragraph 97) from a lattice constant of the first foundation layer (e.g., silicon substrate 100).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the lattice mismatch of Tamura between the relationship of the first foundation layer and first strain-introducing layer of Matsumoto in view of Miyagawa further in view of Tamura, in order to achieve the expected result of providing a strain within the device due to the lattice mismatch, enhancing electron mobility within the transistor region.
Regarding claim 11, Tamura (see, e.g., figs. 2-5) teaches wherein the first channel region (e.g., channel region of paragraphs 39-45) includes (see, e.g., paragraphs 39-42) the first strain-introducing layer (e.g., SiGe film 102).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the channel-strain configuration of Tamura within the configuration of Matsumoto in view of Miyagawa further in view of Tamura, in order to achieve the expected result of enhancing the mobility and operation speed of the transistor within the device. Also see the rejection with respect to claim 1, as the comments are considered to be relevant here.
Regarding claim 12, Tamura (see, e.g., figs. 2-5) teaches wherein a first source and a first drain include (see, e.g., paragraph 39 “…SiGe films 102 buried in the source/drain regions…”) the first strain-introducing layer (e.g., SiGe film 102).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the source/drain-strain configuration of Tamura within the configuration of Matsumoto in view of Miyagawa further in view of Tamura, in order to achieve the expected result of enhancing the mobility and operation speed of the transistor within the device. Also see the rejection with respect to claim 1, as the comments are considered to be relevant here.
Regarding claim 21, Matsumoto (see, e.g., figs. 1-2) shows a second peripheral region (e.g., substrate 11 region within peripheral circuit portion 13 comprising N channel high-breakdown voltage transistor, see fig. 2) including a second peripheral substrate portion (e.g., substrate 11 region within peripheral circuit portion 13 comprising N channel high-breakdown voltage transistor, see fig. 2) and a second peripheral transistor (e.g., N channel high-breakdown voltage transistor of fig. 2) located in the second peripheral substrate portion (e.g., substrate 11 region within peripheral circuit portion 13 comprising N channel high-breakdown voltage transistor, see fig. 2), wherein the signals are transmitted (see, e.g., paragraphs 20 or 124) between the first peripheral region (e.g., peripheral circuit portion 13) and the pixel region (e.g., pixel portion 12) via the second peripheral region (e.g., substrate 11 region within peripheral circuit portion 13 comprising N channel high-breakdown voltage transistor, see fig. 2), the second peripheral transistor (e.g., N channel high-breakdown voltage transistor of fig. 2) includes a gate (e.g., gate electrode 52), the second peripheral transistor (e.g., N channel high-breakdown voltage transistor of fig. 2) further includes, in the second peripheral substrate portion (e.g., substrate 11 region within peripheral circuit portion 13 comprising N channel high-breakdown voltage transistor, see fig. 2), a second source (e.g., source region 54 of left-side transistor in fig. 2), a second drain (e.g., drain region 55 of left-side transistor in fig. 2), a second channel region (e.g., channel region between left-side source and drain regions) located between the second source (e.g., source region 54 of left-side transistor in fig. 2) and the second drain (e.g., drain region 55 of left-side transistor in fig. 2).
Miyagawa (see, e.g., fig. fig. 4 and paragraphs 44-45), in a similar device to Matsumoto, teaches a gate length of a peripheral transistor is less than a gate length of a pixel transistor (see, e.g., paragraph 45 “…thereby enabling a gate length of the transistor in the peripheral circuitry reason to be shortened. In such a case, a gate length of the amplification transistor in pixels is likely to be longer than that of the transistor in the peripheral circuitry region”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the gate difference configuration of Miyagawa within the relationship between the pixel transistor and peripheral transistor of Matsumoto, in order to manipulate the driving voltage relationship between the pixel and peripheral region of the device as desired (also see paragraph 44 of Miyagawa). It also would have been obvious to one of ordinary skill in the art to include the differing gate length between the first and second peripheral transistor in order to diversify and fluctuate the driving voltage and transistor profile within the peripheral region as desired.
Tamura (see, e.g., figs. 3-5) teaches a strain-introducing layer (e.g., SiGe films 102 + paragraphs 41-43) that brings a strain (e.g., strain magnitudes of paragraphs 42-43) to a first channel region.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the strain-introducing layer and strain engineering of Tamura within the second peripheral transistor of Matsumoto in view of Miyagawa further in view of Tamura, in order to enhance the mobility and operation speed of the second transistor and second channel region within the device (also see paragraphs 3 and 42-43 of Tamura).
Regarding claim 22, Matsumoto (see, e.g., figs. 1-2) shows the second peripheral substrate portion (e.g., substrate 11 region within peripheral circuit portion 13 comprising N channel high-breakdown voltage transistor, see fig. 2) includes a second foundation layer (e.g., substrate region beneath N channel high-breakdown voltage transistor).
Tamura (see, e.g., figs. 3-5) teaches a first foundation layer (e.g., silicon substrate 100) is adjacent to the first strain-introducing layer (e.g., SiGe film 102 + paragraphs 41-43) includes a first foundation layer (e.g., silicon substrate 100) adjacent to the first strain-introducing layer (e.g., SiGe film 102 + paragraphs 41-43), and a lattice constant of a crystal lattice of the first strain-introducing layer (e.g., SiGe film 102 + paragraphs 41-43) is different (see, e.g., paragraphs 42-45 or paragraph 97) from a lattice constant of the first foundation layer (e.g., silicon substrate 100).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the lattice mismatch of Tamura between the relationship of the second foundation layer and second strain-introducing layer of Matsumoto in view of Miyagawa further in view of Tamura, in order to achieve the expected result of providing a strain within the device due to the lattice mismatch, enhancing electron mobility within the transistor region.
Regarding claim 23, Tamura (see, e.g., figs. 2-5) teaches wherein a first source and a first drain include (see, e.g., paragraph 39 “…SiGe films 102 buried in the source/drain regions…”) the first strain-introducing layer (e.g., SiGe film 102).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the source/drain-strain configuration of Tamura within the second source/second drain of Matsumoto in view of Miyagawa further in view of Tamura, in order to achieve the expected result of enhancing the mobility and operation speed of the transistor within the device. Also see the rejection with respect to claim 1, as the comments are considered to be relevant here.
Regarding claim 25, Matsumoto (see, e.g., figs. 1-2) shows wherein the first peripheral region (e.g., peripheral circuit portion 13) is located outside the pixel region (e.g., pixel portion 12), and the pixel substrate portion (e.g., substrate 11 region within pixel portion 12) and the first peripheral substrate portion (e.g., substrate 11 region within peripheral circuit portion 13 comprising N channel low-breakdown voltage transistor, see fig. 2) are included in a single semiconductor substrate (e.g., semiconductor substrate 11).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto in view of Miyagawa further in view of Tamura and Lo (US 20060226483 A1).
Regarding claim 2, Matsumoto in view of Miyagawa further in view of Tamura fails to explicitly teach wherein the first strain-introducing layer is a single-crystal layer.
Lo (see, e.g., paragraph 29), in a similar device to Matsumoto in view of Miyagawa further in view of Tamura, teaches a first-strain inducing layer (e.g., single crystalline silicon-germanium layer 12a/12b + paragraph 29) is a single-crystal layer.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the single crystalline arrangement of Lo within the first strain-introducing layer of Matsumoto in view of Miyagawa further in view of Tamura, in order to enhance the uniformity of the strain profile within the device due to the continuous grain-free lattice (also see paragraph 29 of Lo).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto in view of Miyagawa further in view of Tamura and Baars (US 20190051565 A1).
Regarding claim 8, Matsumoto in view of Miyagawa further in view of Tamura fails to explicitly teach wherein the first foundation layer is a single-crystal layer of silicon.
Baars (see, e.g., fig. 1B), in a similar device to Matsumoto in view of Miyagawa further in view of Tamura, teaches a first foundation layer (e.g., semiconductor substrate 112) is a single-crystal layer of silicon (see, e.g., paragraph 35 “…silicon, in particular, single crystal silicon…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the single-crystal layer of silicon of Baars within the first foundation layer of Matsumoto in view of Miyagawa further in view of Tamura, as single-crystal silicon was a well-known setup at the time of filing the invention to include within a foundation/substrate, as taught by Baars.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto in view of Miyagawa further in view of Tamura and Kub (US 9275998 A1).
Regarding claim 9, Matsumoto in view of Miyagawa further in view of Tamura teaches wherein the first peripheral substrate portion (e.g., substrate 11 region within peripheral circuit portion 13 comprising N channel low-breakdown voltage transistor, see fig. 2) includes a supporting substrate (e.g., bottom N-doped layer of substrate 11), the supporting substrate (e.g., bottom N-doped layer of substrate 11) and the first strain-introducing layer (e.g., SiGe film 102 of Tamura) are arranged in order from lower to upper parts of the imaging device (e.g., note that the SiGe film 102 of Tamura is configured with the channel/source/drain of the at least one peripheral transistor of Matsumoto).
Matsumoto in view of Miyagawa further in view of Tamura, however, fails to teach the at least one first peripheral transistor includes a first cap layer in the first peripheral substrate portion, the supporting substrate, the first strain-introducing layer, and the first cap layer are arranged in an order from lower to upper parts of the imaging device, and a concentration of a conductive impurity of the first cap layer is less than a concentration of a conductive impurity of the supporting substrate.
Kub (see, e.g., fig. 3), in a similar device to Matsumoto in view of Miyagawa further in view of Tamura, teaches a first cap layer (e.g., III-nitride cap layer, see fig. 3 “optional cap layer”) in a first substrate portion (e.g., note the optional cap layer is between the source/drain over the substrate) and a concentration of a conductive impurity of the first cap layer (e.g., III-nitride cap layer, see fig. 1 “optional cap layer”) is less than a concentration of a conductive impurity of a supporting substrate (see, e.g., fig. 3, note the buried p-type dopant within the optional back barrier and buffer layer).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the optional cap layer and impurity within the at least one peripheral transistor of Matsumoto in view of Miyagawa further in view of Tamura, in order to provide additional protection/surface passivation properties as desired within the peripheral transistor (also see, e.g., paragraph 88 of Kub). Note that the cap layer is placed above the channel region, hence the order from lower parts to top parts is supporting substrate, then first-strain introducing layer, then the first cap layer.
Regarding claim 10, Kub (see, e.g., fig. 3) teaches wherein the first cap layer (e.g., III-nitride cap layer, see fig. 1 “optional cap layer”) is a non-doped epitaxial layer.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the non-doped configuration of Kub within the first cap layer of Matsumoto in view of Miyagawa further in view of Tamura, in order to achieve the expected result of providing a simpler interface with the substrate, avoiding any unintentional doping effects while simultaneously providing the aforementioned protective/passivation purposes.
Claims 14-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto in view of Miyagawa further in view of Tamura and Noda (US 20090278209 A1).
Regarding claim 14, Matsumoto (see, e.g., figs. 1-2) shows when at least one type of impurity (e.g., germanium of paragraph 154) that suppresses enhanced diffusion of a conductive impurity (e.g., impurities of the pocket diffusion layers 65 and 66) is defined as a diffusion-suppressing species (e.g., germanium of paragraph 154), the at least one peripheral transistor (e.g., substrate 11 region within peripheral circuit portion 13 comprising N channel low-breakdown voltage transistor, see fig. 2) further includes a first specific layer (e.g., pocket diffusion layer 65) that is located in the first peripheral substrate portion (e.g., substrate 11 region within peripheral circuit portion 13 comprising N channel low-breakdown voltage transistor, see fig. 2) and that contains the diffusion-suppressing species (e.g., germanium of paragraph 154).
Matsumoto in view of Miyagawa further in view of Tamura, however, fails to teach the diffusion-suppressing species contains at least one selected from a group consisting of carbon, nitrogen, and fluorine.
Noda (see, e.g., fig. 1), in a similar device to Matsumoto in view of Miyagawa further in view of Tamura, teaches a diffusion-suppressing species (e.g., species of P-type extension high concentration diffusion layer 106) contains carbon (see, e.g., paragraph 65 “The P-type extension high-concentration diffusion layer 106 contains carbon (C)”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the carbon of Noda within the diffusion-suppressing species of Noda, in order to remove excess point defects within the transistor during the annealing process (see, e.g., paragraph 23 of Noda).
Regarding claim 15, Matsumoto (see, e.g., figs. 1-2) shows the at least one peripheral transistor (e.g., N channel low-breakdown voltage transistor in peripheral circuit portion 13) further includes a first pocket diffusion layer (e.g., pocket diffusion layers 65 + 66), the first pocket diffusion layer (e.g., pocket diffusion layers 65 + 66) is adjacent to the first source (e.g., source region 54) or the first drain (e.g., drain region 55), the first specific layer (e.g., pocket diffusion layer 65) is included in at least one selected from the group consisting of the first pocket diffusion layer (e.g., pocket diffusion layers 65 + 66).
Tamura (see, e.g., figs. 2-5) teaches wherein the first channel region (e.g., channel region of paragraphs 39-45) includes (see, e.g., paragraphs 39-42) the first strain-introducing layer (e.g., SiGe film 102 + paragraph 41-43).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the channel-strain configuration of Tamura within the configuration of Matsumoto in view of Miyagawa further in view of Tamura and Noda, in order to achieve the expected result of enhancing the mobility and operation speed of the transistor within the device. Also see the rejection with respect to claim 1, as the comments are considered to be relevant here.
Regarding claim 16, Matsumoto (see, e.g., figs. 1-2) shows the first peripheral substrate portion (e.g., substrate 11 region within peripheral circuit portion 13 comprising N channel low-breakdown voltage transistor, see fig. 2) includes a first foundation layer (e.g., substrate 11)
Tamura (see, e.g., figs. 2-5) teaches wherein a first source and a first drain include (see, e.g., paragraph 39 “…SiGe films 102 buried in the source/drain regions…”) the first strain-introducing layer (e.g., SiGe film 102), and a conductive impurity in at least one selected from the first source (e.g., source of paragraphs 45-46) and the first drain (e.g., drain of paragraphs 45-46) spreads in a first region of a first foundation layer (e.g., silicon substrate 100) astride an interface between the first foundation layer (e.g., silicon substrate 100) and the first strain introducing layer (e.g., SiGe film 102 + paragraphs 41-43) included in the at least one of the first source (e.g., source of paragraphs 45-46) or drain (e.g., drain of paragraphs 45-46).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the source/drain-strain configuration of Tamura within the configuration of Matsumoto in view of Miyagawa further in view of Tamura and Noda, in order to achieve the expected result of enhancing the mobility and operation speed of the transistor within the device. It also would have been obvious include the source/drain-strain configuration of Tamura within the configuration of Matsumoto in view of Miyagawa further in view of Tamura and Noda, in order to achieve the expected result of enhancing the mobility and operation speed of the transistor within the device. It also would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the spreading source/drain interface configuration of Tamura between the first foundation layer and first strain-introducing layer of Matsumoto in view of Miyagawa further in view of Tamura and Noda, in order to expand the strain interface within the device and increase the span of enhanced mobility within the transistor. Also see the rejection with respect to claim 1, as the comments are considered to be relevant here. Note that the first specific layer of Noda was configured within/on the ends of the channel of Matsumoto, so the spread/interface configuration also takes place within this region comprising the first specific layer.
Regarding claim 17, Matsumoto (see, e.g., figs. 1-2) shows when at least one type of impurity that induces amorphization (see, e.g., paragraph 154 “…pre-amorphization may be performed by conducting ion implantation of germanium (Ge)…”) of a region into which the at least one type of impurity has been implanted is defined as an amorphizing species (e.g., germanium of paragraph 154), and the first specific layer (e.g., pocket diffusion layer 65) contains (e.g., note the ion implantation species germanium is the species implanted into the ion implantation area) the amorphizing species (e.g., germanium of paragraph 154), the amorphizing species (e.g., germanium of paragraph 154) contains at least one of a group consisting of germanium (see, e.g., 154), silicon, and argon.
Regarding claim 19, Matsumoto (see, e.g., figs. 1-2) shows the pixel transistor (e.g., amplification transistor Amp in pixel portion 12) further includes a source (e.g., source region 34), a drain (e.g., drain region 35), and a channel region (e.g., channel region between the source and drain) located between the source (e.g., source region 34) and the drain (e.g., drain region 35).
Noda (see, e.g., fig. 1) teaches a concentration of carbon (see, e.g., paragraph 65 “The P-type extension high-concentration diffusion layer 106 contains carbon (C)”) in the first specific layer (e.g., P-type extension high-concentration diffusion layer 106).
Accordingly, it would have been obvious to one of ordinary skill in the invention to include the carbon of Noda within the first specific layer of Matsumoto in view of Miyagawa further in view of Tamura and Noda, in order to remove excess point defects within the transistor during the annealing process (see, e.g., paragraph 23 of Noda and also the comments with respect to the rejection of claim 14). Note that since the channel region of the pixel transistor comprises no carbon, the concentration of carbon in the first specific layer is thus greater than a concentration of carbon in the channel region of the pixel transistor.
Regarding claim 20, Matsumoto (see, e.g., figs. 1-2) shows when at least one type of impurity (e.g., germanium of paragraph 154) that suppresses enhanced diffusion of a conductive impurity (e.g., impurities of the pocket diffusion layers 65 and 66) is defined as a diffusion-suppressing species (e.g., germanium of paragraph 154), the at least one peripheral transistor (e.g., substrate 11 region within peripheral circuit portion 13 comprising N channel low-breakdown voltage transistor, see fig. 2) further includes a first specific layer (e.g., pocket diffusion layer 65) that is located in the first peripheral substrate portion (e.g., substrate 11 region within peripheral circuit portion 13 comprising N channel low-breakdown voltage transistor, see fig. 2) and that contains the diffusion-suppressing species (e.g., germanium of paragraph 154), the at least one peripheral transistor (e.g., collection of transistors in the peripheral circuit portion 13, e.g., at least the N channel low-breakdown voltage transistor in peripheral circuit portion 13) comprises two first peripheral transistors (e.g., N channel low-breakdown voltage transistor, see fig. 2, + P channel high-breakdown voltage transistor), the first peripheral region (e.g., peripheral circuit portion 13) further includes a shallow trench isolation structure (e.g., second isolation regions 15 + paragraph 127), the shallow trench isolation structure (e.g., second isolation regions 15 + paragraph 127) provides device isolation of the two first peripheral transistors (e.g., N channel low-breakdown voltage transistor, see fig. 2, + P channel high-breakdown voltage transistor, see fig. 2) from each other, the shallow trench isolation structure (e.g., second isolation regions 15 + paragraph 127) includes a trench (see, e.g., trench in fig. 2, or note the isolation region 15 is a shallow trench isolation structure), a range of distribution of the diffusion-suppressing species (e.g., germanium of paragraph 154) in the first specific layer (e.g., pocket diffusion layer 65) of at least either of the two first peripheral transistors (e.g., N channel low-breakdown voltage transistor, see fig. 2, + P channel high-breakdown voltage transistor, see fig. 2) is shallower than a bottom of the trench (see, e.g., trench in fig. 2, or note the isolation region 15 is a shallow trench isolation structure).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto in view of Miyagawa further in view of Tamura and Miyazawa (US 20190043910 A1)
Regarding claim 26, Matsumoto in view of Miyagawa further in view of Tamura fails to teach wherein the pixel substrate portion and the first peripheral substrate portion are stacked on top of each other.
Miyazawa (see, e.g., fig. 6), in a similar device to Matsumoto in view of Miyagawa further in view of Tamara teaches a pixel substrate portion (e.g., upper structural body 11 + paragraphs 123-124) and a first peripheral substrate portion (e.g., lower structural body 12) are stacked on top of each other.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the stack configuration of Miyazawa within the layout of Matsumoto in view of Miyagawa further in view of Tamara, in order to achieve the expected result of reducing the horizontal space required for the device’s boundary, fulfilling a vertically extending configuration as an alternative.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto in view of Miyagawa further in view of Tamura, Noda, and Noda (WO 2021152943 A1) (hereinafter Noda2).
Regarding claim 18, Matsumoto in view of Miyagawa further in view of Tamura and Noda fails to explicitly teach wherein the pixel region further includes a charge accumulation region in which a charge generated by photoelectric conversion is accumulated and that is an impurity region, and a concentration of carbon in the first specific layer is greater than a concentration of carbon in the charge accumulation region.
Noda2 (see, e.g., fig. paragraph text), in a similar device to Matsumoto in view of Miyagawa further in view of Tamura in view of Noda, teaches wherein the pixel region includes a charge accumulation region in which a charge generated by photoelectric conversion is accumulated and that is an impurity region (see, e.g., paragraph text “The pixel region may include a charge storage region, which is an impurity region in which charges generated by photoelectric conversion are accumulated.”), and a concentration of carbon in the first specific layer is greater than a concentration of carbon in the charge accumulation region (see, e.g., paragraph text “The concentration of carbon in the first specific layer may be higher than the concentration of carbon in the charge storage region.”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the charge accumulation and carbon concentration of Noda2 within the device of Matsumoto in view of Miyagawa further in view of Tamura and Noda, as it was a well-known methodology of providing signal charge to a transistor setup at the time of filing the invention, as well as including a superior carbon concentration within the first specific layer as opposed to the charge accumulation region, as carbon was a well-known material at the time of filing the invention to include within the first specific layer, whereas the charge storage region doesn’t require the higher concentration to satisfy the charge accumulation requirements, as taught by Noda2.
Claims 13 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Matsumoto in view of Miyagawa further in view of Tamura and Noda2.
Regarding claim 13, Matsumoto (see, e.g., figs. 1-2) shows the pixel transistor (e.g., amplification transistor Amp in pixel portion 12) further includes a pixel gate insulator film (see, e.g., gate insulating film of amplification transistor Amp in pixel portion 12), the at least one peripheral transistor (e.g., N channel low-breakdown voltage transistor of fig. 2) further includes a first peripheral gate insulator film (e.g., gate insulating film of N channel low-breakdown voltage transistor of fig. 2).
Matsumoto in view of Miyagawa further in view of Tamura fails to teach the first peripheral gate insulator film is thinner than the pixel gate insulator film.
Noda2 (see, e.g., paragraph text), in a similar device to Matsumoto in view of Miyagawa further in view of Tamura, teaches a first peripheral gate insulator film (e.g., gate insulating film 301) is thinner (see, e.g., paragraph text “The ratio…of the gate insulating film 301…to the thickness…of the gate insulating film 401…is, for example, .7 or less…” + “…the gate insulating film 69 of the amplification transistor 22 is thicker than the gate insulating film 401…”) than a pixel gate insulator film (gate insulating film 69).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the thickness configuration dynamic of Noda2 within the first peripheral gate insulator film and the pixel gate insulator film of Matsumoto in view of Miyagawa further in view of Tamura, in order to improve the insulation properties within the pixel transistor while simultaneously reducing the cost and material required within the peripheral transistor of the device.
Regarding claim 24, Matsumoto (see, e.g., figs. 1-2) shows the pixel transistor (e.g., amplification transistor Amp in pixel portion 12) further includes a pixel gate insulator film (see, e.g., gate insulating film of amplification transistor Amp in pixel portion 12), the at least one peripheral transistor (e.g., N channel low-breakdown voltage transistor of fig. 2) further includes a first peripheral gate insulator film (e.g., gate insulating film of N channel low-breakdown voltage transistor of fig. 2), the second peripheral transistor (e.g., N channel high-breakdown voltage transistor of fig. 2) further includes a second peripheral gate insulator film (e.g., gate insulating film of N channel high-breakdown voltage transistor of fig. 2).
Matsumoto in view of Miyagawa further in view of Tamura fails to teach the first peripheral gate insulator film is thinner than the second peripheral gate insulator film, and the pixel gate insulator film is thicker than the second peripheral gate insulator film.
Noda2 (see, e.g., paragraph text), in a similar device to Matsumoto in view of Miyagawa further in view of Tamura, teaches a first peripheral gate insulator film (e.g., gate insulating film 301) is thinner (e.g., paragraph text “The ratio…of the gate insulating film 301…to the thickness…of the gate insulating film 401…is, for example, .7 or less…”) than a second peripheral gate insulating film (e.g., gate insulating film 401), and a pixel gate insulator film (gate insulating film 69) is thicker (see, e.g., paragraph text “…the gate insulating film 69 of the amplification transistor 22 is thicker than the gate insulating film 401…”) than the second peripheral gate insulator film (e.g., gate insulating film 401).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the thickness configuration dynamic of Noda2 within the first peripheral gate insulator film, the second peripheral gate insulating film, and the pixel gate insulator film of Matsumoto in view of Miyagawa further in view of Tamura, in order to improve the insulation properties within the pixel transistor while simultaneously reducing the cost and material required within the peripheral transistors of the device.
Conclusion
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/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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