DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this office action and presented for examination. Claims 2-3, 6, 14, 17, and 20 are newly amended by the response received March 3, 2026.
Specification
The disclosure is objected to because of the following informalities. Appropriate correction is required.
In amended paragraph [0021], line 4, “and an instruction 234” should be “an instruction 234” in view of the recitation of “and” preceding “a fused instruction 236” later in the sentence.
Drawings
The drawings are objected to because:
All drawings must be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. However, all drawings in the file wrapper do not meet this requirement — see, for example, the array of white dots that causes the lines, text, and numbers to appear fuzzy and blurry. As one example, see the white dots inside each of FIG. 1, FIG. 2, FIG. 3, and FIG. 4. This may be caused by dithering being applied when a conversion from greyscale to black has taken place; if so, Examiner recommends ensuring that any drawings to be filed do not contain any grey elements.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 17 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 17 recites the limitation “the control circuit is configured to perform the first instruction in response to at least one of a context switch, an error exception corresponding to the fused instruction, a pipeline flush event after the fused instruction, or performing a reference to the first instruction” in lines 1-4. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraphs [0062] and [0065]) does not appear to provide support for performing the first instruction in response to at least one of a context switch, an error exception corresponding to the fused instruction, a pipeline flush event after the fused instruction, or “a reference to the first instruction”.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 20 recites the limitation “an output register for the first instruction” in lines 2-3. However, it is indefinite as to whether the output register of this limitation is the same as, or different from, the destination register of the limitation “destination operand of the first instruction … a destination register corresponding to the destination operand” in claim 19, lines 3-5. If the same, consistent language with antecedent basis language should be used for clarity.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-3, 5-7, 13-14, 16, and 19-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. See MPEP 2106.
Regarding Eligibility Step 1, each of the claims is directed to a process, machine, manufacture, or composition of matter.
Regarding Eligibility Step 2A, Prong One, each of the claims recites abstract ideas. Specifically, each of the claims recites mental processes that can be performed in the human mind, or by a human using a pen and paper. For example, independent claim 1 recites fus[ing], into a fused instruction, a first instruction with a second instruction that depends on the first instruction; and perform[ing] the fused instruction instead of the first and second instructions.
Regarding the recited “device” and “control circuit” in claim 1, Examiner notes that performing a mental process on a generic computer, performing a mental process in a computer environment, and using a computer as a tool to perform a mental process is still an abstract idea.
Regarding Eligibility Step 2A, Prong Two, the claim as a whole does not integrate the judicial exception into a practical application. In other words, the claim does not recite additional elements that integrate the judicial exception into a practical application. Regarding the recited “device” and “control circuit” in claim 1, Examiner notes that merely reciting the words "apply it" (or an equivalent) with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using a computer as a tool to perform an abstract idea, or generally linking the use of a judicial exception to a particular technological environment or field of use, does not integrate a judicial exception into a practical application. Therefore, the claim is directed to the judicial exception. Regarding the recited “sav[ing] metadata corresponding to the first instruction”, Examiner submits that this represents insignificant extra-solution activity (i.e. data outputting).
Regarding Eligibility Step 2B, the claim does not recite additional elements that amount to an inventive concept. In other words, the claim does not recite additional elements that, individually or in combination, amount to significantly more than the judicial exception itself. Regarding the recited “device”, “control circuit”, and “sav[ing] metadata corresponding to the first instruction” in claim 1, Examiner notes that merely adding the words "apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception, e.g., a claim to an abstract idea requiring no more than a generic computer to perform generic computer functions that are well-understood, routine and conventional activities previously known to the industry, or generally linking the use of a judicial exception to a particular technological environment or field of use, are not enough to qualify as "significantly more" when recited in a claim with a judicial exception. Regarding the recited “sav[ing] metadata corresponding to the first instruction”, Examiner also notes that the courts have recognized receiving or transmitting data over a network, performing repetitive calculations, and storing and retrieving information in memory, as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity.
Claims 2-3 and 5 limits the insignificant extra-solution activity of saving metadata in claim 1 to a specific type of metadata, and thus does not recite additional elements which could integrate the abstract idea into a practical application or provide significantly more than the abstract idea itself.
Claim 6 merely reflects a generic computer perform generic computer functions (e.g., use of a register), and further abstract ideas including mental processes (e.g., performing the first instruction) in an analogous manner as claim 1 above, and thus does not recite additional elements which could integrate the abstract idea into a practical application or provide significantly more than the abstract idea itself.
Claim 7, in reciting performing of the first instruction, merely reflects further abstract ideas including mental processes in an analogous manner as claim 1 above.
Independent claim 13 is rejected for analogous reasons as claims 1 and 5 above. While claim 13 further recites a memory, a processor, and a physical register, these elements are likewise components of a generic computer to perform generic computer functions.
Claim 14 is rejected for analogous reasons as claim 3 above.
Claim 16 is rejected for analogous reasons as claims 6 and 7 above.
Independent claim 19 is rejected for analogous reasons as claim 1.
Claim 20 is rejected for analogous reasons as claim 7 above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-6, 13-14, and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pusdesris et al. (Pusdesris) (US 20220156078 A1).
Consider claim 1, Pusdesris discloses a device ([0075], line 1, data processing apparatus 100) comprising: a control circuit ([0075], lines 2-3, the apparatus comprises a pipelined structure) configured to: fuse, into a fused instruction ([0080], line 26, fused into a 3-operand ADD), a first instruction with a second instruction ([0080], lines 25-26, two 2-operand ADDs) that depends on the first instruction ([0079], lines 19-22, the two instructions shown in FIG. 3A have a clear dependency, i.e. that the result of the first is required as an input of the second); save metadata corresponding to the first instruction (FIG. 3B; [0078], lines 31-33, the destination physical register (this being indicated by the preceding entry showing that this is mapped to physical register R10); [0078], lines 22-26, an additional entry for the architectural register x3 has been created in the mapping table. The creation of this “supplementary” entry has been triggered by the fact that x3 in the first instruction of FIG. 3A is a destination register); and perform the fused instruction instead of the first and second instructions (FIG. 3A and FIG. 3C, the fused instruction corresponding to ADD R11 R8 R9 R7 is performed rather than the unfused instruction corresponding to ADD x5 x3 x4).
Consider claim 2, Pusdesris discloses the device of claim 1 (see above), wherein the control circuit is further configured to preserve the metadata, and the metadata maps a physical register holding a destination operand of the first instruction ([0078], lines 31-33, the destination physical register (this being indicated by the preceding entry showing that this is mapped to physical register R10)).
Consider claim 3, Pusdesris discloses the device of claim 2 (see above), wherein the metadata includes a reference to an output register of the first instruction ([0078], lines 31-33, the destination physical register (this being indicated by the preceding entry showing that this is mapped to physical register R10)), and a reference to an operation of the first instruction ([0078], line 37, operation in the mapping table).
Consider claim 5, Pusdesris discloses the device of claim 1 (see above), wherein the control circuit is configured to save the metadata in a register map ([0078], lines 23-24, mapping table).
Consider claim 6, Pusdesris discloses the device of claim 1 (see above), wherein the control circuit is further configured to perform the first instruction to produce an intermediate value for an output register of the first instruction ([0079], lines 24-26, the first instruction is nonetheless carried out as the first operation shown in FIG. 3C).
Consider claim 13, Pusdesris discloses a system comprising: a memory (FIG. 1, data cache hierarchy/memory); and a processor ([0075], line 1, data processing apparatus 100) comprising: a physical register ([0075], lines 35-36, physical registers which are illustrated in FIG. 1 as the set of registers 110); and a control circuit ([0075], lines 2-3, the apparatus comprises a pipelined structure) configured to: fuse, into a fused instruction [0080], line 26, fused into a 3-operand ADD), a first instruction that has a destination operand with a second instruction that depends on the first instruction ([0080], lines 25-26, two 2-operand ADDs; [0079], lines 19-22, the two instructions shown in FIG. 3A have a clear dependency, i.e. that the result of the first is required as an input of the second); save, in a register map associated with the physical register, metadata corresponding to the first instruction and the destination operand (FIG. 3B; [0078], lines 31-33, the destination physical register (this being indicated by the preceding entry showing that this is mapped to physical register R10); [0078], lines 22-26, an additional entry for the architectural register x3 has been created in the mapping table. The creation of this “supplementary” entry has been triggered by the fact that x3 in the first instruction of FIG. 3A is a destination register); and perform the fused instruction instead of the first and second instructions (FIG. 3A and FIG. 3C, the fused instruction corresponding to ADD R11 R8 R9 R7 is performed rather than the unfused instruction corresponding to ADD x5 x3 x4).
Consider claim 14, Pusdesris discloses the system of claim 13 (see above), wherein the metadata includes a reference to an output register of the first instruction ([0078], lines 31-33, the destination physical register (this being indicated by the preceding entry showing that this is mapped to physical register R10)), and a reference to an operation of the first instruction ([0078], line 37, operation in the mapping table).
Consider claim 19, Pusdesris discloses a method comprising: detecting a first instruction that has a destination operand and a second instruction that consumes the destination operand of the first instruction ([0080], lines 25-26, two 2-operand ADDs; [0079], lines 19-22, the two instructions shown in FIG. 3A have a clear dependency, i.e. that the result of the first is required as an input of the second); saving metadata corresponding to the first instruction and a destination register corresponding to the destination operand (FIG. 3B; [0078], lines 31-33, the destination physical register (this being indicated by the preceding entry showing that this is mapped to physical register R10); [0078], lines 22-26, an additional entry for the architectural register x3 has been created in the mapping table. The creation of this “supplementary” entry has been triggered by the fact that x3 in the first instruction of FIG. 3A is a destination register); fusing the first instruction and the second instruction ([0080], lines 25-26, two 2-operand ADDs) into a fused instruction ([0080], line 26, fused into a 3-operand ADD); and performing the fused instruction instead of the first and second instructions (FIG. 3A and FIG. 3C, the fused instruction corresponding to ADD R11 R8 R9 R7 is performed rather than the unfused instruction corresponding to ADD x5 x3 x4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pusdesris as applied to claims 3 and 13 above, and further in view of Kountanis et al. (Kountanis) (US 10691457 B1).
Consider claim 4, Pusdesris discloses the device of claim 3 (see above), but does not explicitly disclose that the control circuit is further configured to free the metadata in response to the output register of the first instruction having no additional references outside of the fused instruction.
On the other hand, Kountanis discloses that a control circuit is further configured to free metadata in response to an output register of a first instruction having no additional references outside of a second instruction (col. 11, lines 2-10, the early release indicator signals to Scheduling Circuit 504 that once the content of register P45 has been received by another instruction (511 in this example), this content will not be used again. Rather than waiting for a subsequent instruction of the group to reassign register P45, register P45 is released after use and is made available for a different allocation. Similarly, registers P46 and P47 may be released after instructions 512 and 513, respectively, are performed).
Kountanis’s teaching results in quick and efficient resource allocation (Kountanis, col. 3, lines 28-29).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Kountanis with the invention of Pusdesris in order to result in quick and efficient resource allocation. Note that the aforementioned teaching of Kountanis, when applied to the invention of Pusdesris which entails a fused instruction in particular, results in the overall claimed limitation.
Consider claim 15, Pusdesris discloses the system of claim 13 (see above), but does not explicitly disclose that the control circuit is further configured to free the metadata in response to an output register of the first instruction having no additional references outside of the fused instruction.
On the other hand, Kountanis discloses that a control circuit is further configured to free metadata in response to an output register of a first instruction having no additional references outside of a second instruction (col. 11, lines 2-10, the early release indicator signals to Scheduling Circuit 504 that once the content of register P45 has been received by another instruction (511 in this example), this content will not be used again. Rather than waiting for a subsequent instruction of the group to reassign register P45, register P45 is released after use and is made available for a different allocation. Similarly, registers P46 and P47 may be released after instructions 512 and 513, respectively, are performed).
Kountanis’s teaching results in quick and efficient resource allocation (Kountanis, col. 3, lines 28-29).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Kountanis with the invention of Pusdesris in order to result in quick and efficient resource allocation. Note that the aforementioned teaching of Kountanis, when applied to the invention of Pusdesris which entails a fused instruction in particular, results in the overall claimed limitation.
Claim(s) 7, 9, 11, and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pusdesris as applied to claims 6 and 13 above, and further in view of Sperber et al. (Sperber) (US 20040199755 A1).
Consider claim 7, Pusdesris discloses the device of claim 6 (see above), and a third instruction depending on the first instruction (FIG. 4A, which shows ADD x7 x5 x6 being dependent on ADD x5 x3 x4, which is dependent on ADD x3 x1 x2), but does not disclose the control circuit is configured to perform the first instruction in response to a third instruction depending on the first instruction.
On the other hand, Sperber discloses a control circuit is configured to perform a first instruction in response to a fused instruction ([0026], line 7, unfused decoding mode may be dynamically used in some cases of exception resolving, as will be described hereinbelow; [0051], lines 5-10, when the simple u-ops are dispatched (-228-), the same exception that arose during execution of the fused u-op will arise in the execution of one or more of these simple u-ops, and in the flow of FIG. 3, reorder buffer 28 may call unfused exception handler 50 to resolve this exception (-326-). The flow of unfused exception handler 50 is shown in FIG. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Sperber with the invention of Pusdesris in order to save power via executing the first instruction only when necessary due to an exception. Alternatively, this modification merely entails simple substitution of one known element (Pusdesris’s teaching of executing a first instruction upon which a fused instruction is based) for another (Sperber’s teaching of executing a first instruction upon which a fused instruction is based in response to an exception) to obtain predictable results (the invention of Pusdesris, wherein executing a first instruction upon which a fused instruction is based is in response to an exception), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143. Note that the aforementioned teaching of Sperber, when applied to the invention of Pusdesris wherein a fused instruction is based on a first instruction, a second instruction, and a third instruction that depends on the first instruction, results in the overall claimed limitation.
Consider claim 9, Pusdesris discloses the device of claim 6 (see above), but does not disclose the control circuit is configured to perform the first instruction in response to an error exception corresponding to the fused instruction.
On the other hand, Sperber discloses a control circuit is configured to perform a first instruction in response to an error exception corresponding to a fused instruction ([0026], line 7, unfused decoding mode may be dynamically used in some cases of exception resolving, as will be described hereinbelow; [0051], lines 5-10, when the simple u-ops are dispatched (-228-), the same exception that arose during execution of the fused u-op will arise in the execution of one or more of these simple u-ops, and in the flow of FIG. 3, reorder buffer 28 may call unfused exception handler 50 to resolve this exception (-326-). The flow of unfused exception handler 50 is shown in FIG. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Sperber with the invention of Pusdesris in order to save power via executing the first instruction only when necessary due to an exception. Alternatively, this modification merely entails simple substitution of one known element (Pusdesris’s teaching of executing a first instruction upon which a fused instruction is based) for another (Sperber’s teaching of executing a first instruction upon which a fused instruction is based in response to an exception) to obtain predictable results (the invention of Pusdesris, wherein executing a first instruction upon which a fused instruction is based is in response to an exception), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
Consider claim 11, Pusdesris discloses the device of claim 6 (see above), but does not disclose the control circuit is configured to perform the first instruction as a result of a pipeline flush after the fused instruction.
On the other hand, Sperber discloses a control circuit is configured to perform a first instruction as a result of a pipeline flush after a fused instruction ([0026], line 7, unfused decoding mode may be dynamically used in some cases of exception resolving, as will be described hereinbelow; [0051], lines 5-10, when the simple u-ops are dispatched (-228-), the same exception that arose during execution of the fused u-op will arise in the execution of one or more of these simple u-ops, and in the flow of FIG. 3, reorder buffer 28 may call unfused exception handler 50 to resolve this exception (-326-). The flow of unfused exception handler 50 is shown in FIG. 4; note that an exception that arises during execution of the fused uop and causes the fused uop to instead be executed via simple uops results in the pipeline being flushed of that fused uop).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Sperber with the invention of Pusdesris in order to save power via executing the first instruction only when necessary due to an exception. Alternatively, this modification merely entails simple substitution of one known element (Pusdesris’s teaching of executing a first instruction upon which a fused instruction is based) for another (Sperber’s teaching of executing a first instruction upon which a fused instruction is based in response to an exception) to obtain predictable results (the invention of Pusdesris, wherein executing a first instruction upon which a fused instruction is based is in response to an exception), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
Consider claim 16, Pusdesris discloses the system of claim 13 (see above), wherein the control circuit is further configured to perform the first instruction to produce an intermediate value for an output register of the first instruction ([0079], lines 24-26, the first instruction is nonetheless carried out as the first operation shown in FIG. 3C) and a third instruction depending on the first instruction (FIG. 4A, which shows ADD x7 x5 x6 being dependent on ADD x5 x3 x4, which is dependent on ADD x3 x1 x2), but does not disclose the control circuit is configured to perform the first instruction in response to a third instruction depending on the first instruction.
On the other hand, Sperber discloses a control circuit is configured to perform a first instruction in response to a fused instruction ([0026], line 7, unfused decoding mode may be dynamically used in some cases of exception resolving, as will be described hereinbelow; [0051], lines 5-10, when the simple u-ops are dispatched (-228-), the same exception that arose during execution of the fused u-op will arise in the execution of one or more of these simple u-ops, and in the flow of FIG. 3, reorder buffer 28 may call unfused exception handler 50 to resolve this exception (-326-). The flow of unfused exception handler 50 is shown in FIG. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Sperber with the invention of Pusdesris in order to save power via executing the first instruction only when necessary due to an exception. Alternatively, this modification merely entails simple substitution of one known element (Pusdesris’s teaching of executing a first instruction upon which a fused instruction is based) for another (Sperber’s teaching of executing a first instruction upon which a fused instruction is based in response to an exception) to obtain predictable results (the invention of Pusdesris, wherein executing a first instruction upon which a fused instruction is based is in response to an exception), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143. Note that the aforementioned teaching of Sperber, when applied to the invention of Pusdesris wherein a fused instruction is based on a first instruction, a second instruction, and a third instruction that depends on the first instruction, and the first instruction produce an intermediate value for an output register of the first instruction, results in the overall claimed limitation.
Consider claim 17, the overall combination entails the system of claim 16 (see above), wherein the control circuit is configured to perform the first instruction in response to at least one of a context switch, an error exception corresponding to the fused instruction, a pipeline flush event after the fused instruction, or a reference to the first instruction (Sperber, [0026], line 7, unfused decoding mode may be dynamically used in some cases of exception resolving, as will be described hereinbelow; [0051], lines 5-10, when the simple u-ops are dispatched (-228-), the same exception that arose during execution of the fused u-op will arise in the execution of one or more of these simple u-ops, and in the flow of FIG. 3, reorder buffer 28 may call unfused exception handler 50 to resolve this exception (-326-). The flow of unfused exception handler 50 is shown in FIG. 4; Pusdesris, [0079], lines 24-26, the first instruction is nonetheless carried out as the first operation shown in FIG. 3C).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pusdesris as applied to claim 6 above, and further in view of Anderson et al. (Anderson) (US 5613114).
Consider claim 8, Pusdesris discloses the device of claim 6 (see above), but does not disclose the control circuit is configured to perform the first instruction in response to a context switch.
On the other hand, Anderson discloses a control circuit is configured to perform a first instruction in response to a context switch (col. 1, lines 44-52, large number of threads may be present in a multithreaded execution environment. A given thread executes for a limited amount of time, after which a conventional context switch is performed, after which another thread executes for a limited amount of time, after which a conventional context switch is performed, after which yet another thread executes for a limited amount of time, after which a conventional context switch is performed, and so on).
Anderson’s teaching enables concurrent processing and gives the appearance of continuous execution to a computer user (Anderson, col. 1, line 9; col. 1, lines 20-21).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Anderson with the invention of Pusdesris in order to enable concurrent processing and give the appearance of continuous execution to a computer user.
Claim(s) 10, 12, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pusdesris as applied to claims 1, 6, and 13 above, and further in view of Chou et al. (Chou) (US 20040230778 A1).
Consider claim 10, Pusdesris discloses the device of claim 6 (see above), but does not disclose that the control circuit is configured to discard the metadata in response to retiring the first instruction.
On the other hand, Chou discloses a control circuit is configured to discard metadata in response to retiring a first instruction ([0050], lines 8-12, when this instruction retires, the previous physical register assigned to the same destination register is returned to the free list, because at this point, it can be guaranteed that there will be no more uses of that physical register).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Chou with the invention of Pusdesris to facilitate efficient but program-correct use of physical registers.
Consider claim 12, Pusdesris discloses the device of claim 1 (see above), but does not disclose the control circuit is configured to discard metadata in response to a producer, that outputs to a register that is referenced in the metadata, retiring.
On the other hand, Chou discloses a control circuit is configured to discard metadata in response to a producer, that outputs to a register that is referenced by metadata, retiring ([0050], lines 8-12, when this instruction retires, the previous physical register assigned to the same destination register is returned to the free list, because at this point, it can be guaranteed that there will be no more uses of that physical register).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Chou with the invention of Pusdesris to facilitate efficient but program-correct use of physical registers.
Consider claim 18, Pusdesris discloses the system of claim 13 (see above), but does not disclose the control circuit is configured to discard the metadata in response to a producer, that outputs to a register that is referenced in the metadata, retiring.
On the other hand, Chou discloses a control circuit is configured to discard metadata in response to a producer, that outputs to a register that is referenced in metadata, retiring ([0050], lines 8-12, when this instruction retires, the previous physical register assigned to the same destination register is returned to the free list, because at this point, it can be guaranteed that there will be no more uses of that physical register).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Chou with the invention of Pusdesris to facilitate efficient but program-correct use of physical registers.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pusdesris as applied to claim 19 above, and further in view of Sperber et al. (Sperber) (US 20040199755 A1) and Chou et al. (Chou) (US 20040230778 A1).
Consider claim 20, Pusdesris discloses the method of claim 19 (see above), further comprising: performing the first instruction to produce an intermediate value in an output register for the first instruction ([0079], lines 24-26, the first instruction is nonetheless carried out as the first operation shown in FIG. 3C) and a third instruction depending on the first instruction (FIG. 4A, which shows ADD x7 x5 x6 being dependent on ADD x5 x3 x4, which is dependent on ADD x3 x1 x2), but does not disclose performing the first instruction in response to a third instruction depending on the first instruction; and discarding the metadata.
On the other hand, Sperber discloses performing a first instruction in response to a fused instruction ([0026], line 7, unfused decoding mode may be dynamically used in some cases of exception resolving, as will be described hereinbelow; [0051], lines 5-10, when the simple u-ops are dispatched (-228-), the same exception that arose during execution of the fused u-op will arise in the execution of one or more of these simple u-ops, and in the flow of FIG. 3, reorder buffer 28 may call unfused exception handler 50 to resolve this exception (-326-). The flow of unfused exception handler 50 is shown in FIG. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Sperber with the invention of Pusdesris in order to save power via executing the first instruction only when necessary due to an exception. Alternatively, this modification merely entails simple substitution of one known element (Pusdesris’s teaching of executing a first instruction upon which a fused instruction is based) for another (Sperber’s teaching of executing a first instruction upon which a fused instruction is based in response to an exception) to obtain predictable results (the invention of Pusdesris, wherein executing a first instruction upon which a fused instruction is based is in response to an exception), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143. Note that the aforementioned teaching of Sperber, when applied to the invention of Pusdesris wherein a fused instruction is based on a first instruction, a second instruction, and a third instruction that depends on the first instruction, and the first instruction is performed to produce an intermediate value for an output register for the first instruction, results in the overall claimed limitation of performing the first instruction in response to a third instruction depending on the first instruction.
However, the combination thus far does not disclose discarding the metadata.
On the other hand, Chou discloses discarding metadata ([0050], lines 8-12, when this instruction retires, the previous physical register assigned to the same destination register is returned to the free list, because at this point, it can be guaranteed that there will be no more uses of that physical register).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Chou with the combination of Pusdesris and Sperber to facilitate efficient but program-correct use of physical registers.
Response to Arguments
Applicant on page 10 argues: “The Office Action objected to the specification for containing informalities. Applicant has amended the specification and title herein. Withdrawal of the objections to the specification is respectfully requested.”
In view of the aforementioned amendments, most previously presented objections to the specification are withdrawn — see the specification section above for the remaining objection.
Applicant on page 10 argues: “The Office Action objected to the drawings. Although the Office Action has not specified which figure, Applicant has amended figure 3 herein. Withdrawal of the objections to the drawings is respectfully requested.”
Examiner notes that no specific figure was given in view of the rationale for objection being applicable to all Figures. Examiner also notes that Figure 3 as amended does not appear to wholly overcome the objection — see the array of white dots across portions of Figure 3 as amended in the file wrapper, such as within the FIG. 3 label and the other numbers and letters of the Figure.
Applicant on page 10 argues: “The Office Action objected to claims 6-11 for containing informalities. Applicant has amended claim 6 herein. Withdrawal of the objections to the claims is respectfully requested.”
In view of the aforementioned amendment, the previously presented objections of the claims are withdrawn.
Applicant on page 10 argues: “Claims 2-4, 14, 17, and 20 were rejected under 35 U.S.C. § 112(b) as allegedly being indefinite. Applicant respectfully disagrees that any terminology in any claim is indefinite. However, for the purposes of compact prosecution, Applicant has amended the claims herein to clarify any alleged indefiniteness. Withdrawal of the rejections to the claims is respectfully requested.”
Most previously presented rejections of the claims under 35 U.S.C. §112(b) are withdrawn in view of the amendments to the claims. However, one previously presented rejection of the claims under 35 U.S.C. §112(b) remains applicable, and in one case an amendment to the claims introduces an additional issue under 35 U.S.C. §112(a) — see the Claim Rejections - 35 USC § 112 section above.
Applicant on page 11 argues: ‘Claims 1-3, 5-7, 13-14, 16, and 19-20 were rejected under 35 U.S.C. § 101 for allegedly reciting ineligible subject matter. Applicant respectfully disagrees, as all claims are directed to subject matter that is eligible for patenting. As described in the originally filed specification, "two instructions, which can each correspond to (e.g., be assigned to) respective execution units, can be fused into a single instruction that occupies only one scheduler entry and is assigned to its own respective execution unit such that performance is improved (e.g., reduced power consumption, lower execution latency, more efficient utilization of computing resources such as schedulers, etc.) from using a single execution unit rather two execution units." See paragraph [0019] of the originally filed specification. In other words, the claims are directed to improvements to the functioning of a computer (e.g., processor) itself. Accordingly, all claims are directed to subject matter that is eligible for patenting.’
However, as noted in MPEP 2106.05(a), “[i]t is important to note, the judicial exception alone cannot provide the improvement.”
Applicant on page 12 conveys: “The foregoing discussion is provided solely for the convenience of the Examiner in preparing to review the arguments below and is not intended to characterize any claim in any way.”
Examiner appreciates the aforementioned discussion provided solely for the convenience of the Examiner in preparing to review the arguments. Examiner further appreciates the discussion of Pusdesris across pages 12-13 of the arguments.
Applicant on page 13 argues: ‘Independent claim 1 recites, inter alia, "perform the fused instruction instead of the first and second instructions." Even if, ad arguendo, Pusdesris suggests "fuse, into a fused instruction, a first instruction with a second instruction that depends on the first instruction" as recited in claim 1, Pusdesris fails to disclose or suggest "perform the fused instruction instead of the first and second instructions" as recited in claim 1. As detailed above, Pusdesris explicitly requires all instructions to be carried out to ensure that the processor state remains consistent.’
With respect to FIG. 3A and FIG. 3C, Examiner submits that, because the three-operand instruction “ADD x5 x3 x4”—which is mapped to the second instruction—is not executed, Pusdesris consequently teaches performing the four-operand fused instruction “ADD R11 R8 R9 R7” instead of the first and second instructions. While Pusdesris may still entail performing the first instruction “ADD x3 x1 x2”, this behavior does not preclude Pusdesris from teaching the relevant limitation under the broadest reasonable interpretation, because the fused instruction of Pusdesris is performed instead of performing “the first and second instructions” (emphasis added). In other words, given that the second instruction is not performed, “the first and second instructions” collectively are necessarily not performed either. In other words, in order to obtain the appropriate result that will be stored in architectural register x5 (physical register R11), the fused instruction “ADD R11 R8 R9 R7” is performed instead of performing both “ADD x3 x1 x2” and “ADD x5 x3 x4”.
Regarding Applicant’s citation of paragraph [0082] in the first indented paragraph of page 13 of the remarks, Examiner notes that the “all three instructions [that] are nonetheless correctly carried out” (in FIG. 4C) do not include the three-operand instructions “ADD x5 x3 x4” and “ADD x7 x5 x6” in FIG. 4A. Regarding Applicant’s argument reproduced above that “Pusdesris explicitly requires all instructions to be carried out to ensure that the processor state remains consistent”, Examiner submits that these “all instructions” are particularly the instructions in FIG. 3C or FIG. 4C, which do not include the instruction that was mapped to the recited “second instruction”.
Consequently, while the overall inventive concept of Pusdesris may differ from the inventive concept of the instant application, Examiner submits that Pusdesris nevertheless still teaches the current claim language under the broadest reasonable interpretation.
Applicant on page 14 argues: ‘For reasons that should be appreciated from the foregoing, Pusdesris does not disclose: - "perform the fused instruction instead of the first and second instructions" recited in claim 13; or - "performing the fused instruction instead of the first and second instructions" recited in claim 19. For at least these reasons, claims 13 and 19 patentably distinguish Pusdesris. Withdrawal of the rejections of claims 13 and 19 and of each claim that depends therefrom under § 102 is respectfully requested.’
Examiner’s response to arguments with respect to claim 1 above is likewise applicable to Applicant’s arguments directed to the aforementioned further claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KEITH E VICARY/ Primary Examiner, Art Unit 2183