DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1 and 9, the claims recite “…measurement of the specific resistance is continuously performed at measurement intervals…”. Additionally, the claims are drawn to a product, namely “A Group-III element nitride semiconductor substrate”. The aforementioned limitation on the method of measuring the specific resistance of the substrate is a method of using said product. A single claim which claims both an apparatus and the method steps of using the apparatus is indefinite under 35 U.S.C. 112(b). IPXL Holdings v. Amazon.com, Inc., 430 F.2d 1377, 1384, 77 USPQ2d 1140, 1145 (Fed. Cir. 2005).
Additionally, regarding claims 1 and 9, the language “…continuously performed at measurement intervals…” is indefinite. It is unclear in what way the measurement is continuous, particularly when performed at spatial intervals, which inherently suggests discontinuities. In an alternative interpretation, measurement may be continuous through time. However, such an interpretation is inconsistent with the measurement method described in the specification wherein a probe is moved between measurement locations, where the time in which the probe is moving between measurements is a temporal discontinuity in measurement. Therefore, the meaning of “continuously” in this context is indefinite. Additionally, as set forth in In re Miyazaki, “if a claim is amenable to two or more plausible claim constructions, the USPTO is justified in requiring the applicant to more precisely define the metes and bounds of the claimed invention by holding the claim unpatentable under 35 U.S.C. §112, second paragraph, as indefinite.” 89 USPQ2d 1207, 1211 (Bd. Pat. App. & Int. 2008). For the purpose of examination, Examiner interprets the claims as reciting “…
Regarding claim 2, the claim recites “The Group-III element nitride semiconductor substrate according to claim 1, wherein the measurement of the specific resistance is performed through mapping measurement in the first surface by an electric capacitance method.” A single claim which claims both an apparatus and the method steps of using the apparatus is indefinite under 35 U.S.C. 112(b). IPXL Holdings v. Amazon.com, Inc., 430 F.2d 1377, 1384, 77 USPQ2d 1140, 1145 (Fed. Cir. 2005).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Fujikura et al. (JP 2012246195 A, hereinafter F1).
Regarding independent claim 1, F1 discloses in F1 FIG. 3(a)-3(c) and associated text A Group-III element nitride semiconductor substrate (FIG. 3 shows characteristics of a GaN layer (F1 [0027])), comprising: a first surface (the “front face” on which resistivity is measured (F1 [0061])); and a second surface (a layer inherently has at least two surfaces; since F1 identifies a “front face” (F1 [0061]), there is at least another face, i.e. a “back face”), wherein a minimum value of a specific resistance in the first surface is 1×107 Ω∙cm or more (As can be seen from FIG. 3, sample No. 7 has an average resistivity of 2×1011 Ω∙cm (F1 [0078]), and a variation of approximately 25% (note that although this datapoint is not labeled “No. 7” in the graph of FIG. 3(b), the graphs of FIG. 3(a)-3(b) represent various characteristics of the same set of samples and using the same scale and dependent variable for the x-axis, making it obvious that the points with an x-value of ~4×10-3 correspond to sample No. 7 in each case). Using the given variation formula “=±((maximum value - minimum value) / mean value) / 2” (F1 [0041]), the average resistivity of 2×1011 Ω∙cm, and the fact that the maximum value must inherently be greater than or equal to the average, the minimum resistivity measurement must have been at least 1×1011 Ω∙cm (see derivation below)), wherein the minimum value of the specific resistance in the first surface is 0.01 or more times as large as a maximum value of the specific resistance in the first surface (the minimum possible value of the ratio of minimum to maximum resistivities for the aforementioned average resistivity and variation values disclosed is 0.5 (see derivation below)), wherein measurement of the specific resistance is performed at measurement intervals (F1 [0061]).
Derivation of the minimum possible value of the minimum resistivity measurement:
v
a
r
i
a
t
i
o
n
=
ρ
m
a
x
-
ρ
m
i
n
2
×
ρ
-
; where
ρ
-
=
2
×
10
11
Ω∙cm, and
v
a
r
i
a
t
i
o
n
=
0.25
Derivation of the minimum possible value of the minimum resistivity to maximum resistivity ratio:
v
a
r
i
a
t
i
o
n
=
ρ
m
a
x
-
ρ
m
i
n
2
×
ρ
-
; where
ρ
-
=
2
×
10
11
Ω∙cm, and
v
a
r
i
a
t
i
o
n
=
0.25
F1 does not explicitly disclose measurement intervals of 10 mm or less. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to try measurement intervals of 10 mm or less on the substrate of F1 with routine experiment and optimization since one of ordinary skill in the art would have recognized that smaller intervals between measurements would enable greater accuracy in measuring the uniformity of the resistivity of the substrate and would have therefore been motivated to reduce the measurement intervals to obtain more thorough and accurate data on the uniformity and homogeneity of the substrate. See also In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Additionally, the limitation “measurement of the specific resistance is performed at measurement intervals of 10 mm or less” is an intended use of the substrate which does not further limit its structure and therefore holds no patentable weight.
Regarding dependent claim 2, F1 further discloses The Group-III element nitride semiconductor substrate according to claim 1, but does not explicitly disclose the measurement of the specific resistance is performed through mapping measurement in the first surface by an electric capacitance method. However, this limitation is an intended use of the substrate which does not further limit its structure and therefore holds no patentable weight.
Regarding dependent claim 4, F1 further discloses The Group-III element nitride semiconductor substrate according to claim 1, wherein an oxygen concentration in the Group-III element nitride semiconductor substrate measured by SIMS is from 2×1016 atoms/cm3 to 6×1016 atoms/cm3 (growth conditions of the samples produced resulted in an oxygen concentration of 3×1016 atoms/cm3 (F1 [0063])).
Regarding dependent claim 5, F1 further discloses The Group-III element nitride semiconductor substrate according to claim 1, wherein the Group-III element nitride semiconductor substrate is free of a nanopipe therein (a “nanopipe” or “defect, which…had a width in a [11-20] direction of 20 nm or more”, as the term is interpreted in light of the example provided in the instant disclosure ([0111]) is not present in the description of the nitride semiconductors described in F1, therefore said nitride semiconductors are considered to be free of a nanopipe).
Regarding dependent claim 6, F1 further discloses The Group-III element nitride semiconductor substrate according to claim 1, wherein the Group-III element nitride semiconductor substrate has a diameter of 75 mm or more (the nitride semiconductor wafer size is 4-8 inches (~100-200mm; F1[0039])).
Regarding independent claim 9, F1 discloses in F1 FIG. 3(a)-3(c) and associated text A Group-III element nitride semiconductor substrate (FIG. 3 shows characteristics of a GaN layer (F1 [0027])), comprising: a first surface (the “front face” on which resistivity is measured (F1 [0061])); and a second surface (a layer inherently has at least two surfaces; since F1 identifies a “front face” (F1 [0061]), there is at least another face, i.e. a “back face”), wherein a minimum value of a specific resistance in the first surface is 1×107 Ω∙cm or more (As can be seen from FIG. 3, sample No. 7 has an average resistivity of 2×1011 Ω∙cm (F1 [0078]), and a variation of approximately 25% (note that although this datapoint is not labeled “No. 7” in the graph of FIG. 3(b), the graphs of FIG. 3(a)-3(b) represent various characteristics of the same set of samples and using the same scale and dependent variable for the x-axis, making it obvious that the points with an x-value of ~4×10-3 correspond to sample No. 7 in each case). Using the given variation formula “=±((maximum value - minimum value) / mean value) / 2” (F1 [0041]), the average resistivity of 2×1011 Ω∙cm, and the fact that the maximum value must inherently be greater than or equal to the average, the minimum resistivity measurement must have been at least 1×1011 Ω∙cm (see derivation below)), wherein the minimum value of the specific resistance in the first surface is 0.01 or more times as large as a maximum value of the specific resistance in the first surface (the minimum possible value of the ratio of minimum to maximum resistivities for the aforementioned average resistivity and variation values disclosed is 0.5 (see derivation below)), wherein the Group-III element nitride semiconductor substrate comprises Zn, Mn or Fe as a dopant (Fe is used as a dopant (F1 [0035])), wherein the Group-III element nitride semiconductor substrate is free of a nanopipe therein (no mention of a “nanopipe” or “defect, which…had a width in a [11-20] direction of 20 nm or more”, as the term is interpreted in light of the instant specification ([0111]) is present in the description of the nitride semiconductors described in F1, therefore said nitride semiconductors are considered to be free of a nanopipe), and wherein an oxygen concentration in the Group-III element nitride semiconductor substrate measured by SIMS is from 2×1016 atoms/cm3 to 6×1016 atoms/cm3 (growth conditions of the samples produced and oxygen concentration of 3×1016 atoms/cm3 (F1 [0063] )), wherein measurement of the specific resistance is performed at measurement intervals (F1 [0061]).
Derivation of the minimum possible value of the minimum resistivity measurement:
v
a
r
i
a
t
i
o
n
=
ρ
m
a
x
-
ρ
m
i
n
2
×
ρ
-
; where
ρ
-
=
2
×
10
11
Ω∙cm, and
v
a
r
i
a
t
i
o
n
=
0.25
Derivation of the minimum possible value of the minimum resistivity to maximum resistivity ratio:
v
a
r
i
a
t
i
o
n
=
ρ
m
a
x
-
ρ
m
i
n
2
×
ρ
-
; where
ρ
-
=
2
×
10
11
Ω∙cm, and
v
a
r
i
a
t
i
o
n
=
0.25
F1 does not explicitly disclose measurement intervals of 5 mm or less. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to try measurement intervals of 5 mm or less on the substrate of F1 with routine experiment and optimization since one of ordinary skill in the art would have recognized that smaller intervals between measurements would enable greater accuracy in measuring the uniformity of the resistivity of the substrate and would have therefore been motivated to reduce the measurement intervals to obtain more thorough and accurate data on the uniformity and homogeneity of the substrate. See also In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Additionally, the limitation “measurement of the specific resistance is performed at measurement intervals of 5 mm or less” is an intended use of the substrate which does not further limit its structure and therefore holds no patentable weight.
Claims 2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over F1, and further in view of Iwai et al. (JP 2011020896 A, hereinafter I1).
Regarding dependent claim 2, F1 discloses The Group-III element nitride semiconductor substrate according to claim 1. F1 does not explicitly disclose the Group-III element nitride semiconductor substrate comprises Zn as a dopant.
However, in the same field of endeavor, I1 discloses in I1 FIG. 7 and associated text the Group-III element nitride semiconductor substrate comprises Zn as a dopant (the Zn-doped GaN substrate exhibits similarly high resistivity compared to the Fe-doped GaN substrate of F1 (I1 [0028])).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have Zn as a dopant as disclosed by I1 in the substrate of F1, since it has been held that selection of a known material on the basis of its suitability for the intended use supports a prima facie obviousness determination. In re Leshin, 125 USPQ 416; Sinclair & Carroll Co. v. Interchemical Corp., 65 USPQ 297.
Regarding dependent claim 10, F1 discloses in F1 FIG. 3(a)-3(c) and associated text The Group-III element nitride semiconductor substrate according to claim 9, wherein the minimum value of the specific resistance in the first surface is 1×1011 Ω∙cm or more (1×1011 Ω∙cm is the minimum possible resistivity measurement of sample No. 7 as calculated above), and wherein the minimum value of the specific resistance in the first surface is 0.5 or more times as large as the maximum value of the specific resistance in the first surface (0.5 is the minimum possible value of the minimum-to-maximum measured resistivity ratio possible for sample No. 7 as calculated above). F1 does not explicitly disclose the Group-III element nitride semiconductor substrate comprises Zn as a dopant.
However, in the same field of endeavor, I1 discloses in I1 FIG. 7 and associated text the Group-III element nitride semiconductor substrate comprises Zn as a dopant (the Zn-doped GaN substrate exhibits similarly high resistivity compared to the Fe-doped GaN substrate of F1 (I1 [0028])).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have Zn as a dopant as disclosed by I1 in the substrate of F1, since it has been held that selection of a known material on the basis of its suitability for the intended use supports a prima facie obviousness determination. In re Leshin, 125 USPQ 416; Sinclair & Carroll Co. v. Interchemical Corp., 65 USPQ 297.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over F1, and further in view of Gambin et al. (US 20130026489 A1, hereinafter G1).
Regarding dependent claim 7, F1 further discloses in F1 FIG. 7(b) and associated text An epitaxial substrate, comprising: the Group-III element nitride semiconductor substrate of claim 1 (semi-insulating free-standing nitride-semiconductor substrate 20); a channel layer formed of GaN (undoped GaN layer 34); and a barrier layer formed of at least one kind selected from InAlGaN, InAlN, and AlGaN (AlGaN layer 35), the channel layer and the barrier layer being arranged in the stated order on the first surface of the Group-III element nitride semiconductor substrate (as shown in F1 FIG. 7(b), the layers are arranged in the following order: substrate 20, channel layer 34, and barrier layer 35).
F1 does not explicitly disclose a buffer layer formed of at least one kind selected from AlGaN and AlN; or the buffer layer, the channel layer, and the barrier layer being arranged in the stated order on the first surface of the Group-III element nitride semiconductor substrate.
However, in the same field of endeavor, G1 discloses in G1 FIG. 2 and associated text a buffer layer formed of at least one kind selected from AlGaN and AlN (AlN buffer 34); and the buffer layer being arranged below the channel layer and the barrier layer on the first surface of the substrate (buffer 34 is on substrate 32 and below barrier 36 and channel 38).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the AlN buffer of G1 with the epitaxial substrate structure of F1 such that the buffer layer, the channel layer, and the barrier layer being arranged in the stated order on the first surface of the Group-III element nitride semiconductor substrate to provide “both a structure for facilitating epitaxial growth and a layer that reduces defects that may occur in the substrate” (G1 [0020]).
Regarding dependent claim 8, F1 further discloses in F1 FIG. 7(b) and associated text A functional device, comprising: the Group-III element nitride semiconductor substrate of claim 1 (semi-insulating free-standing nitride-semiconductor substrate 20); a channel layer formed of GaN (undoped GaN layer 34); and a barrier layer formed of at least one kind selected from InAlGaN, InAlN, and AlGaN (AlGaN layer 35), the channel layer and the barrier layer being arranged in the stated order on the first surface of the Group-III element nitride semiconductor substrate (as shown in F1 FIG. 7(b), the layers are arranged in the following order: substrate 20, channel layer 34, and barrier layer 35).
F1 does not explicitly disclose a buffer layer formed of at least one kind selected from AlGaN and AlN; or the buffer layer, the channel layer, and the barrier layer being arranged in the stated order on the first surface of the Group-III element nitride semiconductor substrate.
However, in the same field of endeavor, G1 discloses in G1 FIG. 2 and associated text a buffer layer formed of at least one kind selected from AlGaN and AlN (AlN buffer 34); and the buffer layer being arranged below the channel layer and the barrier layer on the first surface of the substrate (buffer 34 is on substrate 32 and below barrier 36 and channel 38).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the AlN buffer of G1 with the functional device structure of F1 such that the buffer layer, the channel layer, and the barrier layer being arranged in the stated order on the first surface of the Group-III element nitride semiconductor substrate to provide “both a structure for facilitating epitaxial growth and a layer that reduces defects that may occur in the substrate” (G1 [0020]).
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
US 20150187926 A1, pertaining to a high-resistivity Zn-doped GaN semiconductor substrate.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVERETT TRAJAN RIRIE whose telephone number is (571) 272-9559. The examiner can normally be reached Mon - Thu 8:30 am - 6:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EVERETT T RIRIE/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights