Prosecution Insights
Last updated: August 17, 2026
Application No. 18/754,531

BARRIER LAYER REMOVAL DEVICE AND BARRIER LAYER REMOVAL METHOD

Non-Final OA §102§103
Filed
Jun 26, 2024
Priority
Dec 26, 2023 — RE 10-2023-0191126
Examiner
CROWELL, ANNA M
Art Unit
1713
Tech Center
1700 — Chemical & Materials Engineering
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
45%
Grant Probability
Moderate
1-2
OA Rounds
1y 8m
Est. Remaining
76%
With Interview

Examiner Intelligence

Grants 45% of resolved cases
45%
Career Allowance Rate
196 granted / 438 resolved
-20.3% vs TC avg
Strong +31% interview lift
Without
With
+30.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 10m
Avg Prosecution
31 currently pending
Career history
473
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
57.9%
+17.9% vs TC avg
§102
16.5%
-23.5% vs TC avg
§112
13.7%
-26.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 438 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group I (claims 1-13) in the reply filed on June 15, 2026 is acknowledged. Claims 14-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 and 6-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Holden et al. (U.S. 2016/0086852). Referring to Figures 4B and 6A and paragraphs [0046]-[0052], [0058]-[0061], Holden et al. disclose a barrier layer removal device, comprising: a frame 404 mounted with a tape 402 to which a wafer 406 is attached, wherein the wafer includes a barrier layer disposed on one surface (par.[0059]); a support 408 on which the wafer 406, attached to the tape 402, is disposed (Fig. 6A); a frame cover 600 disposed above the frame, wherein the frame fixes the wafer on the support by pressing an edge region of the one surface of the wafer (par.[0059]); and a nozzle for spraying an etchant on the barrier layer of the wafer (i.e. nozzle used in wet etching-pars.[0085],[0092]). With regards to “the wafer includes a barrier layer disposed on one surface”, the limitation is considered intended use in an apparatus claims and therefore are of no significance in determining patentability. Hence, it should be noted that the inclusion of material or article worked upon by a structure being claimed does not impart patentability to the claims (MPEP 2115). With respect to claim 6, the device of Holden et al. further includes wherein the support does not vacuum-suction the wafer when the frame cover presses the wafer (Figs 4 & 6). With respect to claim 7, the device of Holden et al. further includes wherein the barrier layer is a metal layer (As stated above, the barrier layer is considered intended use-MPEP 2115). With respect to claim 8, the device of Holden et al. further includes wherein the barrier layer includes titanium (Ti) (As stated above, the barrier layer is considered intended use-MPEP 2115). With respect to claim 9, the device of Holden et al. further includes wherein the wafer 406 is a reconstituted wafer including a substrate, a plurality of semiconductor chips disposed on the substrate while being spaced apart from each other, and a molding material encapsulating the plurality of semiconductor chips on the substrate, and wherein the barrier layer is disposed on the substrate (As stated above, the wafer is considered intended use-MPEP 2115). With respect to claim 10, the device of Holden et al. further includes wherein the reconstituted wafer further includes a rewiring structure disposed on the molding material and electrically connected to the substrate (As stated above, wafer is considered intended use-MPEP 2115). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 2-5 and 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Holden et al. (U.S. 2016/0086852) in view of Engesser (U.S. 7,799,695). The teachings of Holden et al. have been discussed above. Holden et al. fail to teach a contact pin pressing the edge region of the one surface of the wafer together with the frame cover. Referring to Figure 1 and column 5, lines 48-57, Engesser teach a device wherein a contact pin 3 pressing the edge region of the one surface of the wafer together as a means to secure the wafer during processing. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the apparatus of Holden et al. to have a contact pin pressing the edge region of the one surface of the wafer as taught by Engesser since it is a means to secure the wafer during processing. The resulting apparatus of Holden et al. in view of Engesser would yield a contact pin pressing the edge region of the one surface of the wafer together with the frame cover. With respect to claim 3, the device of Holden et al. in view of Engesser further includes wherein the contact pin presses a point inside the wafer rather than a portion of the wafer that is pressed by the frame cover (The particular placement of a contact pin of Engesser is considered an obvious matter of design choice that would yield improvement in securing the wafer-MPEP 2144.04 VIC). With respect to claim 4, the device of Holden et al. in view of Engesser further includes wherein the frame cover 600 presses a portion disposed within about 1 mm from an edge of the wafer along a circumference of the wafer (i.e. Holden et al.), and the contact pin 3 presses a point disposed within about 5 mm from the edge of the wafer (i.e. Engesser) (The particular placement of a frame cover and a contact pin of Holden et al. in view of Engesser are considered an obvious matter of design choice that would yield improvement in securing the wafer-MPEP 2144.04 VIC). With respect to claim 5, the device of Holden et al. in view of Engesser further includes wherein the contact pin 3 presses a point outside a point where dicing lines of the wafer intersect each other (The particular placement of a contact pin of Engesser is considered an obvious matter of design choice that would yield improvement in securing the wafer-MPEP 2144.04 VIC). With respect to claim 11, referring to Figures 4B and 6A and paragraphs [0046]-[0052], [0058]-[0061], Holden et al. disclose a barrier layer removal device, comprising: a frame 404 mounted with a tape 402 to which a wafer 406 is attached, wherein the wafer includes a barrier layer disposed on a first surface (par.[0059]); a support 408 on which the wafer 406, attached to the tape 402, is disposed (Fig. 6A); a frame cover 600 disposed above the frame, wherein the frame fixes the wafer on the support by pressing an edge region of the one surface of the wafer (par.[0059]); and a nozzle for spraying an etchant on the barrier layer of the wafer (i.e. nozzle used in wet etching-pars.[0085],[0092]). With regards to “the wafer includes a barrier layer disposed on one surface”, the limitation is considered intended use in an apparatus claims and therefore are of no significance in determining patentability. Hence, it should be noted that the inclusion of material or article worked upon by a structure being claimed does not impart patentability to the claims (MPEP 2115). Holden et al. fail to teach a plurality of contact pins pressing the edge region of the one surface of the wafer together with the frame cover. Referring to Figure 1 and column 5, lines 48-57, Engesser teach a device wherein a plurality of contact pins 3 pressing the edge region of the first surface of the wafer together as a means to secure the wafer during processing. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the apparatus of Holden et al. to have a plurality of contact pins pressing the edge region of the first surface of the wafer as taught by Engesser since it is a means to secure the wafer during processing. The resulting apparatus of Holden et al. in view of Engesser would yield a plurality of contact pins pressing the edge region of the first surface of the wafer together with the frame cover. With respect to claim 12, the device of Holden et al. in view of Engesser further includes wherein the plurality of contact pins 3 include a first contact pin and a second contact pin, each pressing points disposed on a plane in opposite directions from a center of the first surface of the wafer (Engesser-Figure 1 and column 5, lines 48-57). With respect to claim 13, the device of Holden et al. in view of Engesser further includes wherein the plurality of contact pins further include a third contact pin and a fourth contact pin, each pressing points disposed on the plane in opposite directions from the center of the first surface of the wafer, and wherein a first virtual line and a second virtual line intersect each other, the first virtual line connecting the point pressed by the first contact pin to the point pressed by the second contact pin, and the second virtual line connecting the point pressed by the third contact pin to the point pressed by the fourth contact pin (Engesser-Figure 1 and column 5, lines 48-57, Additionally, four contact pins is considered mere duplication of parts-MPEP 2144.04 VIB). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Harikai et al.’188, Shih et al.’613, Iwai’739, Yano’672, Kubo et al.’383, Yamasaki et al.’007, Hwang et al.’531, Chang et al.’565, Yang et al.’793, Nakamura’242, and Penmethsa et al.’159 teach a device having a frame cover, a frame, a support, and a tape. Okutani’324 and Ueno et al.’231 teach a contact pin used to secure a wafer. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michelle CROWELL whose telephone number is (571)272-1432. The examiner can normally be reached Monday-Thursday 10:00am-6:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Parviz Hassanzadeh can be reached at 571-272-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Michelle CROWELL/Examiner, Art Unit 1716 /SYLVIA MACARTHUR/Primary Examiner, Art Unit 1716
Read full office action

Prosecution Timeline

Jun 26, 2024
Application Filed
Jul 15, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
45%
Grant Probability
76%
With Interview (+30.8%)
3y 10m (~1y 8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 438 resolved cases by this examiner. Grant probability derived from career allowance rate.

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