Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 15 recites the limitation "the second metal layer" in the second subparagraph. There is insufficient antecedent basis for this limitation in the claim.
For purposes of compact prosecution, the first subparagraph that recites “a second interconnection layer on the first metal layer” will be interpreted to instead recite “a second metal
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al (“Cho”), US 2025/0248117 (the US counterpart of, and used as a translation for, KR 20220065924 dated 5-23-2022) in view of Choi et al. (“Choi”), US 2008/0012134 (listed in the IDS dated 6-26-2024).
Regarding Claim 10, Cho discloses a semiconductor device (Figs. 1-5D, 21A-21D; ¶ 0009-0011, 0021 “a semiconductor device”), comprising:
a substrate (100; Figs. 5A-5D, 21A-21D; ¶ 0048 “substrate”) including an active pattern (AP1, AP2; Figs. 5A-5D, 21A-21D; ¶ 0048 “first and second active patterns AP1 and AP2”);
a channel pattern (CH1, CH2; Figs. 21A-21B; ¶ 0160 “first and second channel patterns CH1 and CH2”) on the active pattern (Figs. 21A-21B; ¶ 0160 “active pattern AP1 may include the first channel pattern CHI” and “active pattern AP2 may include the second channel pattern CH2”), the channel pattern comprising a plurality of semiconductor patterns (SP1, SP2, SP3; Figs. 21A-21B; ¶ 0160 “channel patterns CH1 and CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3”) which are stacked (Figs. 21A-21B; ¶ 0160 “sequentially stacked”) in a vertical direction perpendicular to an upper surface of the substrate (Figs. 21A-21B; ¶ 0160 “n a vertical direction (e.g., a third direction D3)”) and spaced apart from each other in the vertical direction (Figs. 21A, 21B; ¶ 0160 “semiconductor patterns SP1, SP2, and SP3 may be spaced apart from each other in a vertical direction (e.g., a third direction D3)”);
a source/drain pattern (SD1, SD2; Figs. 21A-21B; ¶ 0162 “source/drain patterns SD1”, ¶ 0163 “source/drain patterns SD2”) connected to the channel pattern (Figs. 21A-21B; ¶ 0162 “channel pattern CH1 may be interposed between each adjacent pair of the first source/drain patterns SD1”, ¶ 0163 “channel pattern CH2 may be interposed between each adjacent pair of the second source/drain patterns SD2”); a gate electrode (GE; Figs. 21A-21B, 21D; ¶ 0166 “gate electrode GE”) on the plurality of semiconductor patterns (Fig. 21D; ¶ 0166 “gate electrode GE may be provided to surround the first to third semiconductor patterns SP1, SP2, and SP3 of each of the first and second channel patterns CH1 and CH2”;
an active contact (AC; Fig. 21C; ¶ 0170 “active contacts AC”) electrically connected to the source/drain pattern (Fig. 21C; ¶ 0170 “active contacts AC may be…connected to the first and second source/drain patterns SD1 and SD2, respectively”);
a metal interconnection structure (M1, M2; Figs. 5C, 21C; ¶ 0092 “first metal layer M1 may be provided in the third interlayer insulating layer 130”, ¶ 0097 “second metal layer M2 may be provided in the fourth interlayer insulating layer 140”, ¶ 0170-0171) on the active contact (Figs. 5C, 21C; ¶ 0095 “active contact AC and the interconnection line of the first metal layer M1 may be electrically connected to each other through the first via VI1”), the metal interconnection structure comprising a conductive via (VI1; Figs. 5C, 21C; ¶ 0095 “vias VI1”) and an interconnection pattern (M1_1; Figs. 5C, 1C; ¶ 0092 “interconnection lines M1_I”, ¶ 0094 “interconnection lines M1_I of the first metal layer M1”) on the conductive via (Figs. 5C, 21C; ¶ 0095 ”vias VII may be respectively provided below the interconnection lines…of the first metal layer M1” and “the interconnection line of the first metal layer M1 may be electrically connected to…the first via VI1”, ¶ 0096 “the interconnection line of the first metal layer M1 and the first via VII thereunder”).
Cho does not disclose
a diffusion prevention pattern between the interconnection pattern and the conductive via,
wherein a level of a top surface of the diffusion prevention pattern is different from a level of a bottommost surface of the interconnection pattern in contact with the diffusion prevention pattern in the vertical direction, relative to the upper surface of the substrate, and
the diffusion prevention pattern comprises ruthenium oxide.
Choi discloses
a diffusion prevention pattern (145; Fig. 2; ¶ 0023 “diffusion barrier layer 145”) between (Fig. 2; ¶ 0024 “165 may be electrically connected to the first metal interconnection 115 through the first diffusion barrier layer 145”, ¶ 0025 “diffusion barrier layer 145 between the first and second metal interconnections 115 and 165”) the interconnection pattern (115; Fig. 2; ¶ 0023 “metal interconnection 115”, ¶ 0020 “metal interconnection 115 may be electrically connected to active devices such as transistors”) and the conductive via (165; Fig. 2; ¶ 0024 “metal…165”),
wherein a level of a top surface of the diffusion prevention pattern (Fig. 2 the top surface of diffusion prevention pattern 145; ¶ 0024 “165 may be electrically connected to the first metal interconnection 115 through the first diffusion barrier layer 145”, ¶ 0025 “diffusion barrier layer 145 between the first and second metal interconnections 115 and 165”) is different from (Fig. 2 the top surface of 145 is different from the bottom surface of 115) a level of a bottommost surface of the interconnection pattern (Fig. 2 the bottom surface of 115; ¶ 0024 “165 may be electrically connected to the first metal interconnection 115 through the first diffusion barrier layer 145”, ¶ 0025 “diffusion barrier layer 145 between the first and second metal interconnections 115 and 165”) in contact with the diffusion prevention pattern (Fig. 2; ¶ 0023 “diffusion barrier layer 145 is disposed on the exposed first metal interconnection 115”) in the vertical direction (Fig. 2; ¶ 0023 “diffusion barrier layer 145 is disposed on the exposed first metal interconnection 115” therefore 145 is on 115 “in the vertical direction”), relative to the upper surface (Fig. 2 the upper surface of substrate 110; ¶ 0023 “145 is disposed on the exposed first metal interconnection 115”) of the substrate (110; Fig. 2; ¶ 0020 “semiconductor substrate 110”), and
the diffusion prevention pattern (145) comprises ruthenium oxide (¶ 0023 “diffusion barrier layer 145 may comprise...ruthenium(Ru)” and “diffusion barrier layer 145 may further comprise an oxide of the selected material”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cho to have a diffusion prevention pattern between the interconnection pattern and the conductive via, wherein a level of a top surface of the diffusion prevention pattern is different from a level of a bottommost surface of the interconnection pattern in contact with the diffusion prevention pattern in the vertical direction, relative to the upper surface of the substrate, and the diffusion prevention pattern comprises ruthenium oxide, as taught by Choi, because “diffusion barrier layer 145 between the first and second metal interconnections 115 and 165 can prevent the metal atoms in the first metal interconnection 115 from being diffused into the second metal interconnection 165” (Choi ¶ 0025) and “in particular, when the first diffusion barrier layer 145 comprises oxide…as described above, the diffusion barrier effect between the first and second metal interconnections 115 and 165 may be further improved” (Choi ¶ 0025), thereby improving the performance and reliability of the semiconductor device.
Regarding Claim 13, Cho discloses
wherein the metal interconnection structure (M1, M2) comprises a first metal layer (M1; Figs. 5C, 21C; ¶ 0092 “metal layer M1 may be provided in the third interlayer insulating layer 130”) and a second metal layer (M2; Figs. 5C, 21C; ¶ 0097 “metal layer M2 may be provided in the fourth interlayer insulating layer 140”) on the first metal layer (Figs, 5C, 21C; ¶ 0079 “fourth interlayer insulating layer 140 may be provided on the third interlayer insulating layer 130”),
the conductive via comprises a first conductive via in the first metal layer (VI1; Figs. 5C, 21C; ¶ 0095 “metal layer M1 may further include first vias VI1”) and a second conductive via in the second metal layer (VI2; Figs. 5C, 21C; ¶ 0098 “metal layer M2 may further include second vias VI2”),
the interconnection pattern comprises a first interconnection pattern in the first metal layer (M1_I; Figs. 5C, 21C; ¶ 0092 “metal layer M1 may include…interconnection lines M1_I”, ¶ 0094 “interconnection lines M1_I of the first metal layer M1”) and a second interconnection pattern in the second metal layer (M2_I; Figs. 5C, 21C; ¶ 0097 “metal layer M2 may include a plurality of second interconnection lines M2_I”).
Cho does not disclose
the diffusion prevention pattern is between the second conductive via and the second interconnection pattern.
Choi discloses
the diffusion prevention pattern (145) is between (Fig. 2; ¶ 0025 “diffusion barrier layer 145 between the first and second metal interconnections 115 and 165”, ¶ 0024 “165 may be electrically connected to the first metal interconnection 115 through the first diffusion barrier layer 145”) the second conductive via (165; Fig. 2; ¶ 0024 “metal…165”) and the second interconnection pattern (115; Fig. 2; ¶ 0023 “metal interconnection 115”, ¶ 0020 “metal interconnection 115 may be electrically connected to active devices such as transistors”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cho to have the diffusion prevention pattern is between the second conductive via and the second interconnection pattern, as taught by Choi, because “diffusion barrier layer 145 between the first and second metal interconnections 115 and 165 can prevent the metal atoms in the first metal interconnection 115 from being diffused into the second metal interconnection 165” (Choi ¶ 0025), thereby improving the performance and reliability of the semiconductor device.
Regarding Claim 14, Cho does not disclose
a selection barrier pattern in contact with a side surface of the diffusion prevention pattern,
wherein a level of a top surface of the selection barrier pattern is lower than the level of the top surface of the diffusion prevention pattern in the vertical direction, relative to the upper surface of the substrate.
Choi discloses
a selection barrier pattern (120; Fig. 2; ¶ 0021 “layer 120”) in contact with a side surface (Fig. 2; ¶ 0023 “an opening 135 that penetrates the…layer 120, and a first diffusion barrier layer 145 is disposed on the exposed first metal interconnection 115”) of the diffusion prevention pattern (145),
wherein a level of a top surface of the selection barrier pattern (Fig. 2 the top surface of 120) is lower than (Fig. 2) the level of the top surface of the diffusion prevention pattern (Fig. 2 the top surface of 145) in the vertical direction (Fig. 2), relative to the upper surface of the substrate (Fig. 2 the upper surface of substrate 110).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cho to have a selection barrier pattern in contact with a side surface of the diffusion prevention pattern, wherein a level of a top surface of the selection barrier pattern is lower than the level of the top surface of the diffusion prevention pattern in the vertical direction, relative to the upper surface of the substrate, as taught by Choi, because “layer 120 may function as a diffusion barrier layer that prevents metal atoms…in the first metal interconnection 115 from being diffused into a layer thereon” and “layer 120 may prevent a top surface of the first metal interconnection 115 from being damaged due to an over-etching process” (Choi ¶ 0021, 0029), thereby improving the performance and reliability of the semiconductor device.
Regarding Claim 15, Cho discloses
wherein the metal interconnection structure (M1, M2) comprises a first metal layer (M1; Figs. 5C, 21C; ¶ 0092 “metal layer M1 may be provided in the third interlayer insulating layer 130”) and a second interconnection layer (M2; Figs. 5C, 21C; ¶ 0097 “metal layer M2 may be provided in the fourth interlayer insulating layer 140”) on the first metal layer (Figs, 5C, 21C; ¶ 0079 “fourth interlayer insulating layer 140 may be provided on the third interlayer insulating layer 130”),
the conductive via comprises a first conductive via in the first metal layer (VI1; Figs. 5C, 21C; ¶ 0095 “metal layer M1 may further include first vias VI1”) and a second conductive via in the second metal layer (VI2; Figs. 5C, 21C; ¶ 0098 “metal layer M2 may further include second vias VI2”),
the interconnection pattern comprises a first interconnection pattern in the first metal layer (M1_I; Figs. 5C, 21C; ¶ 0092 “metal layer M1 may include…interconnection lines M1_I”, ¶ 0094 “interconnection lines M1_I of the first metal layer M1”) and a second interconnection pattern in the second metal layer (M2_I; Figs. 5C, 21C; ¶ 0097 “metal layer M2 may include a plurality of second interconnection lines M2_I”).
Cho does not disclose
the diffusion prevention pattern is between the first conductive via and the first interconnection pattern.
Choi discloses
the diffusion prevention pattern (145) is between (Fig. 2; ¶ 0025 “diffusion barrier layer 145 between the first and second metal interconnections 115 and 165”, ¶ 0024 “165 may be electrically connected to the first metal interconnection 115 through the first diffusion barrier layer 145”) the first conductive via (165; Fig. 2; ¶ 0024 “metal…165”) and the first interconnection pattern (115; Fig. 2; ¶ 0023 “metal interconnection 115”, ¶ 0020 “metal interconnection 115 may be electrically connected to active devices such as transistors”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Cho to have the diffusion prevention pattern is between the first conductive via and the first interconnection pattern, as taught by Choi, because “diffusion barrier layer 145 between the first and second metal interconnections 115 and 165 can prevent the metal atoms in the first metal interconnection 115 from being diffused into the second metal interconnection 165” (Choi ¶ 0025), thereby improving the performance and reliability of the semiconductor device.
Allowable Subject Matter
Claims 1-9 and 18-20 are allowable.
Regarding Claim 1, the prior art does not disclose a diffusion prevention pattern between the first interconnection pattern and the second conductive via, wherein a level of a bottom surface of the diffusion prevention pattern is lower than a level of the topmost surface of the first interconnection pattern in the vertical direction, relative to the upper surface of the substrate and in the combination as claimed.
Claims 2-9 are allowable for depending on Claim 1.
Regarding Claim 18, the prior art does not disclose a diffusion prevention pattern between the first conductive via and the first interconnection pattern; and a selection barrier pattern extending around a portion of a bottom surface of the first interconnection pattern and a side surface of the first interconnection pattern, wherein a side surface of the diffusion prevention pattern is in contact with the first interconnection pattern, the selection barrier pattern, and the first via insulating layer and in the combination as claimed.
Claims 19-20 are allowable for depending on Claim 18.
Claims 11-12 and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 11, the prior art does not teach or render obvious further comprising: a via insulating layer extending around the conductive via; and a selection barrier pattern between the via insulating layer and the interconnection pattern, wherein the level of the top surface of the diffusion prevention pattern is lower than a level of a top surface of the selection barrier pattern in the vertical direction, relative to the upper surface of the substrate. Therefore, the combination of the features of Claims 10 and 11 is considered allowable.
Claim 12 incorporates all of the limitations of Claim 11. Therefore, the combination of the features of Claims 10, 11, and 12 is considered allowable.
Regarding Claim 16, the prior art does not teach or render obvious further comprising: a first pattern insulating layer extending around the first interconnection pattern; a first via insulating layer extending around the first conductive via; and a selection barrier pattern between the first pattern insulating layer and the first interconnection pattern and between the first via insulating layer and the first interconnection pattern, wherein a side surface of the diffusion prevention pattern is in contact with the first interconnection pattern, the selection barrier pattern, and the first via insulating layer. Therefore, the combination of the features of Claims 10 and 16 is considered allowable.
Claim 17 incorporates all of the limitations of Claim 16. Therefore, the combination of the features of Claims 10, 16, and 17 is considered allowable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Bark et al. US 2002/0359379, Bark et al. US 2021/0351123, Park et al. US 2022/0399452, Kim et al. US 2022/0399463, Kang et al. US 2022/0199798, Park et al. US 2022/0173053, and Kim et al. US 2022/045103 disclose a semiconductor device having a channel pattern, a source/drain pattern, a first metal layer, and a second metal layer.
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/R.K./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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