Prosecution Insights
Last updated: August 17, 2026
Application No. 18/754,628

SEMICONDUCTOR PACKAGE HAVING A THREE-DIMENSIONAL PRINTED ENCLOSURE

Non-Final OA §102§103
Filed
Jun 26, 2024
Examiner
SMITH, SAMUEL JONATHAN
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SanDisk Technologies Inc.
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
1y 4m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
39 granted / 47 resolved
+15.0% vs TC avg
Moderate +5% lift
Without
With
+5.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
21 currently pending
Career history
60
Total Applications
across all art units

Statute-Specific Performance

§103
58.2%
+18.2% vs TC avg
§102
32.8%
-7.2% vs TC avg
§112
8.5%
-31.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 47 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-9 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Wainerdi (US 20190207582 A1). Regarding claim 1, Wainerdi discloses a method for encapsulating an electronic device, the method comprising: providing a substrate (Fig. 5A, 508) having a first side (upper surface) with a plurality of components (comprising at least 507, 506, 505, and 504) secured thereto; and three-dimensional (3D) printing a mold compound (503; para. 44 "The full protective shell 503 is formed using 3D printing technology as described above such that the semiconductor die 504 is placed within the inner space of shell structure") on the first side of the substrate (Fig. 5A shows the mold compound on the upper surface of the substrate) such that the mold compound covers the plurality of components (Fig. 5A shows the mold compound covering at least 507, 506, 505 and 504). Regarding claim 2, Wainerdi discloses wherein the mold compound comprises a thermosetting liquid resin (Para. 28 "a 3D printer is used to deposit layers of ink on the top surface of the semiconductor die", para. 30 " the protective shell is made of ceramic materials (e.g., 3D printable resin form)", para. 28 "the ink can be, for example,... a UV-curable polymer or a UV-curable polymer-based mixture", where thermosetting resins are known to be UV curable). Regarding claim 3, Wainerdi discloses further comprising curing the 3D printed mold compound during a curing process (Para. 29 "a series of inkjet printers can be used, such as where several different distinct nanoinks are to be printed. Such different nanoinks may comprise different metals, may be printed in interactive patterns or layouts, and/or may be printed atop one other, such as after a cure process for each one"; alternatively para. 35 "the protective shell are printed and the semiconductor package is sent to a bake to dry/cure step. In an implementation, UV snap cure may be used for a faster result"). Regarding claim 4, Wainerdi discloses further comprising forming a mark (uppermost 3D printed layer of 503) on an outer surface (upper surface) of the 3D printed mold compound as part of the curing process (curing process comprising at least forming the marking and sending the package to cure; para. 35 "the protective shell are printed and the semiconductor package is sent to a bake to dry/cure step. In an implementation, UV snap cure may be used for a faster result"). Regarding claim 5, Wainerdi discloses wherein the curing process includes: activating one or more ultraviolet light sources on a thermosetting liquid resin to form an enclosure around the plurality of components (Wainerdi does not explicitly disclose UV light sources. However, Wainderdi discloses using 3D printing an enclosure around the plurality of components with a thermosetting liquid resin, and UV curing said resin. It is therefore inherent that one would need to activate one or more ultraviolet light sources in order to supply ultraviolet light to cure the UV curable resin taught by Wainderdi). Regarding claim 6, Wainerdi discloses wherein activating the one or more ultraviolet light sources comprises selectively activating the one or more ultraviolet light sources (Para. 29 "a series of inkjet printers can be used, such as where several different distinct nanoinks are to be printed. Such different nanoinks may comprise different metals, may be printed in interactive patterns or layouts, and/or may be printed atop one other, such as after a cure process for each one", where the one or more ultraviolet light sources would necessarily be activated selectively depending on the layer being cured). Regarding claim 7, Wainerdi discloses wherein the one or more ultraviolet light sources are selectively activated based, at least in part, on a layer of the enclosure being formed (Para. 29 "a series of inkjet printers can be used, such as where several different distinct nanoinks are to be printed. Such different nanoinks may comprise different metals, may be printed in interactive patterns or layouts, and/or may be printed atop one other, such as after a cure process for each one", where the one or more ultraviolet light sources would necessarily be activated selectively depending on the layer being cured). Regarding claim 8, Wainerdi discloses wherein the one or more ultraviolet light sources are selectively activated based, at least in part, on a shape of the enclosure being formed (Para. 29 "a series of inkjet printers can be used, such as where several different distinct nanoinks are to be printed. Such different nanoinks may comprise different metals, may be printed in interactive patterns or layouts, and/or may be printed atop one other, such as after a cure process for each one", where the one or more ultraviolet light sources would necessarily be activated selectively depending on the layer being cured, and therefore necessarily be shaped by this process). Regarding claim 9, Wainerdi discloses wherein the one or more ultraviolet light sources are selectively activated based, at least in part, on a marking to be included on the enclosure (In the case of using a cure process for each layer as described in para. 29, the ultraviolet light sources would necessarily be activated selectively based on the formation of the marking). Claim Rejections - 35 USC § 103 Claim(s) 10-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wainerdi (US 20190207582 A1). Regarding claim 10, Wainerdi discloses a semiconductor package, comprising: a substrate (Fig. 5A, 508); a plurality of electronic components (comprising at least 507, 506, 505, and 504) mounted on the substrate; and an enclosure (503) at least partially surrounding the plurality of electronic components (Fig. 5A shows the enclosure covering at least 507, 506, 505, and 504), the enclosure being formed by a three-dimensional (3D) printing process (para. 44 "The full protective shell 503 is formed using 3D printing technology as described above such that the semiconductor die 504 is placed within the inner space of shell structure"). However, the claim language “the enclosure being formed by a three-dimensional (3D) printing process in which the plurality of electronic components are immersed in a thermosetting liquid resin” recites intermediate process steps that do not affect the structure of the final device. Therefore, the process limitations recited in a “product by process” claim would not carry patentable weight in a claim drawn to structure because distinct structure is not necessarily produced. See MPEP 2113. In re Thorpe, 227 USPQ 964 (Fed. Cir. 1985). Regarding claim 11, Wainerdi discloses wherein the 3D printing process includes a curing process (Para. 35 "the protective shell are printed and the semiconductor package is sent to a bake to dry/cure step. In an implementation, UV snap cure may be used for a faster result") wherein the 3D printing process includes a curing process in which one or more ultraviolet lights are selectively activated (Wainerdi does not explicitly disclose UV light sources. However, Wainderdi discloses using 3D printing an enclosure around the plurality of components with a thermosetting liquid resin, and UV curing said resin. It is therefore inherent that one would need to activate one or more ultraviolet light sources in order to supply ultraviolet light to cure the UV curable resin taught by Wainderdi). However, the claim language “wherein the 3D printing process includes a curing process wherein the 3D printing process includes a curing process in which one or more ultraviolet lights are selectively activated” recites intermediate process steps that do not affect the structure of the final device. Therefore, the process limitations recited in a “product by process” claim would not carry patentable weight in a claim drawn to structure because distinct structure is not necessarily produced. See MPEP 2113. In re Thorpe, 227 USPQ 964 (Fed. Cir. 1985). Regarding claim 12, Wainerdi discloses wherein the enclosure includes a marking (uppermost 3D printed layer of 503). Regarding claim 13, Wainerdi discloses wherein the marking was formed during a curing process (Para. 29 "a series of inkjet printers can be used, such as where several different distinct nanoinks are to be printed. Such different nanoinks may comprise different metals, may be printed in interactive patterns or layouts, and/or may be printed atop one other, such as after a cure process for each one"; the curing process comprising at least forming the marking and curing the layer comprising the marking). However, the claim language “wherein the marking was formed during a curing process” recites intermediate process steps that do not affect the structure of the final device. Therefore, the process limitations recited in a “product by process” claim would not carry patentable weight in a claim drawn to structure because distinct structure is not necessarily produced. See MPEP 2113. In re Thorpe, 227 USPQ 964 (Fed. Cir. 1985). Regarding claim 14, Wainerdi discloses wherein the enclosure has a shape that was formed by selectively activating one or more ultraviolet lights as part of a curing process (Para. 29 "a series of inkjet printers can be used, such as where several different distinct nanoinks are to be printed. Such different nanoinks may comprise different metals, may be printed in interactive patterns or layouts, and/or may be printed atop one other, such as after a cure process for each one", where the one or more ultraviolet light sources would necessarily be activated selectively depending on the layer being cured, and therefore necessarily be shaped by this process). However, the claim language “a shape that was formed by selectively activating one or more ultraviolet lights as part of a curing process” recites intermediate process steps that do not affect the structure of the final device. Therefore, the process limitations recited in a “product by process” claim would not carry patentable weight in a claim drawn to structure because distinct structure is not necessarily produced. See MPEP 2113. In re Thorpe, 227 USPQ 964 (Fed. Cir. 1985). Regarding claim 15, Wainerdi discloses a semiconductor package, comprising: a substrate (Fig. 5A, comprises at least 508, 507, and 506); at least one semiconductor die (504) mounted on the substrate (Shown); a communication means (513) electrically coupling the at least one semiconductor die to the substrate (Shown); and a three-dimensional (3D) printed enclosing means (503) at least partially surrounding the at least one semiconductor die and the communication means (Shown). However, the claim language “a three-dimensional (3D) printed enclosing means” recites intermediate process steps that do not affect the structure of the final device. Therefore, the process limitations recited in a “product by process” claim would not carry patentable weight in a claim drawn to structure because distinct structure is not necessarily produced. See MPEP 2113. In re Thorpe, 227 USPQ 964 (Fed. Cir. 1985). Regarding claim 16, Wainerdi discloses further comprising a marking formed on the 3D printed enclosing means (uppermost 3D printed layer of 503). Regarding claim 17, Wainerdi discloses wherein the 3D printed enclosing means and the marking formed on the 3D printed enclosing means were formed as part of a 3D printing process (uppermost layer of 503 is necessarily formed as part of the 3D printing process). However, the claim language “wherein the 3D printed enclosing means and the marking formed on the 3D printed enclosing means were formed as part of a 3D printing process” recites intermediate process steps that do not affect the structure of the final device. Therefore, the process limitations recited in a “product by process” claim would not carry patentable weight in a claim drawn to structure because distinct structure is not necessarily produced. See MPEP 2113. In re Thorpe, 227 USPQ 964 (Fed. Cir. 1985). Regarding claim 18, Wainerdi discloses wherein the 3D printed enclosing means is cured (Para. 29 "a series of inkjet printers can be used, such as where several different distinct nanoinks are to be printed. Such different nanoinks may comprise different metals, may be printed in interactive patterns or layouts, and/or may be printed atop one other, such as after a cure process for each one"; alternatively para. 35 "the protective shell are printed and the semiconductor package is sent to a bake to dry/cure step. In an implementation, UV snap cure may be used for a faster result") and the marking is formed by selectively activating one or more ultraviolet light sources during a curing process (the curing process comprising at least forming the uppermost layer of the enclosure and curing it by activating ultraviolet light sources). However, the claim language “wherein the 3D printed enclosing means is cured and the marking is formed by selectively activating one or more ultraviolet light sources during a curing process” recites intermediate process steps that do not affect the structure of the final device. Therefore, the process limitations recited in a “product by process” claim would not carry patentable weight in a claim drawn to structure because distinct structure is not necessarily produced. See MPEP 2113. In re Thorpe, 227 USPQ 964 (Fed. Cir. 1985). Regarding claim 19, Wainerdi discloses wherein the 3D printed enclosing means comprises a thermosetting liquid resin (Para. 28 "a 3D printer is used to deposit layers of ink on the top surface of the semiconductor die", para. 30 " the protective shell is made of ceramic materials (e.g., 3D printable resin form)", para. 28 "the ink can be, for example,... a UV-curable polymer or a UV-curable polymer-based mixture", where thermosetting resins are known to be UV curable). Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Wainerdi (US 20190207582 A1) as applied to claim 15-19 above, and further in view of Sawanobori (US 20210242138 A1). Regarding claim 20, Wainerdi discloses the semiconductor package of claim 15. However, Wainerdi does not disclose wherein the at least one semiconductor die is a NAND memory die. On the other hand, Sawanobori discloses wherein the at least one semiconductor die is a NAND memory die (Fig. 1; para. 12 "Each of the semiconductor chips 30 and 50 may be a memory chip such as a NAND flash memory"). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Wainerdi according to the teachings of Sawanobori such that the at least one semiconductor die would be a NAND memory die, in order to bring the flexibility, cost efficiency, and simplified manufacturing of 3D printing to the manufacturing of NAND memory devices. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL J SMITH whose telephone number is (703)756-5706. The examiner can normally be reached M-F 8-5 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571) 272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /S.J.S./ Examiner, Art Unit 2817 Primary Examiner, Art Unit 2817/ALI NARAGHI/
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Prosecution Timeline

Jun 26, 2024
Application Filed
Jun 26, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
88%
With Interview (+5.4%)
3y 6m (~1y 4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 47 resolved cases by this examiner. Grant probability derived from career allowance rate.

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