DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 10, the claim recites the limitation "the first conductive layer" and “the second conductive layer” in lines 4-5. There is insufficient antecedent basis for this limitation in the claim.
It is indefinite as to whether the first and second conductive layers refer to the first and second conductive layer patterns of claim 4 or some other layers. For the purposes of examination the former interpretation will be used.
Regarding claim 18, the claim recites the limitation "the first conductive layer" and “the second conductive layer” in lines 4-5. There is insufficient antecedent basis for this limitation in the claim.
It is indefinite as to whether the first and second conductive layers refer to the first and second conductive layer patterns of claim 17 or some other layers. For the purposes of examination the former interpretation will be used.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-10, and 16-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (US 20110266541 A1) herein after “Yang”.
Regarding claim 1, Figs. 2 and 4A of Yang disclose a semiconductor structure (Fig. 4A, semiconductor chip 100A, ¶ [0015]), comprising:
a semiconductor substrate (Fig. 4A, semiconductor substrate 103, ¶ [0023]) having a circuit region (Fig. 4A, circuit region 102, ¶ [0015]) and a seal ring region (Figs. 2 and 4A, seal ring region 104, enhanced region 105, CSR region 108, ¶ [0015-0016] and [0023]) surrounding the circuit region (102);
an electronic circuit (Fig. 4A, electrical elements 112, ¶ [0018]) disposed on the semiconductor substrate (103) in the circuit region (102);
a first seal ring (Fig. 2, “The seal ring region 104 having a seal ring structure”, ¶ [0016]) disposed on the semiconductor substrate (103) in the seal ring region (104, 105, 108) and surrounding the circuit region (102);
a buffer zone (Fig. 4A, enhanced region 105, ¶ [0023]) located in the seal ring region (104, 105, 108) and interposed between the circuit region (102) and the first seal ring (104), wherein the first seal ring (104) is separated from the circuit region (102) by the buffer zone (Fig. 4A, “The enhanced region 105 having the enhanced structure 110 is disposed between the circuit region 102 and the CSR region 108”, ¶ [0023]); and
a conductive routing (Fig. 4A, metal line 116, ¶ [0019]) disposed on the semiconductor substrate (103) in the buffer zone (105), wherein the conductive routing (116) is electrically connected to the electronic circuit (112).
Regarding claim 2, Figs. 2 and 4A of Yang disclose the semiconductor structure as claimed in claim 1 as applied above, and Figs. 2 and 4A of Yang further disclose wherein the conductive routing (116) comprises a connecting portion (portion of 116 in 105) extending from the buffer zone (105) to the circuit region (102).
Regarding claim 3, Figs. 2 and 4A of Yang disclose the semiconductor structure as claimed in claim 1 as applied above, and Figs. 2 and 4A of Yang further disclose wherein the conductive routing (116) is separated from the first seal ring (104).
Regarding claim 4, Figs. 2 and 4A of Yang disclose the semiconductor structure as claimed in claim 1 as applied above, and Figs. 4A-4B of Yang further disclose comprising:
an interconnect structure (interconnection structure shown in Fig. 4A-4B) disposed on the semiconductor substrate (103); and
a shielding structure (Fig. 4B, metal layers M1-MT, ¶ [0027]), wherein the shielding structure (M1-MT) and the conductive routing (116) are embedded in dielectric layers (Fig. 4A, multiple dielectric layers 118, ¶ [0025]) of the interconnect structure (interconnection structure shown in Fig. 4A-4B) in the buffer zone (105), wherein the shielding structure (M1-MT) surrounds and is separated from the conductive routing (116), and the shielding structure (M1-MT) comprises:
a first conductive layer pattern (M4) located above a top surface of the conductive routing (116);
a second conductive layer pattern (M2) located below a bottom surface of the conductive routing (116), wherein the first conductive layer pattern (M4) and the second conductive layer pattern (M2) overlap each other; and
third conductive layer patterns (M3) disposed beside opposite side surfaces of the conductive routing (116).
Regarding claim 6, Figs. 4A-4B of Yang disclose the semiconductor structure as claimed in claim 4 as applied above, and Figs. 4A-4B of Yang further disclose wherein the first conductive layer pattern (M4), the second conductive layer pattern (M2) and the conductive routing (116) belong to different levels of conductive layers of the interconnect structure (interconnection structure shown in Fig. 4A-4B).
Regarding claim 7, Figs. 4A-4B of Yang disclose the semiconductor structure as claimed in claim 4 as applied above, and Figs. 4A-4B of Yang further disclose wherein the first conductive layer pattern (M4) and the conductive routing (116) belong to adjacent levels of conductive layers of the interconnect structure (interconnection structure shown in Fig. 4A-4B).
Regarding claim 8, Figs. 4A-4B of Yang disclose the semiconductor structure as claimed in claim 4 as applied above, and Figs. 4A-4B of Yang further disclose wherein the second conductive layer pattern (M2) and the conductive routing (116) belong to adjacent levels of conductive layers of the interconnect structure (interconnection structure shown in Fig. 4A-4B).
Regarding claim 9, Figs. 4A-4B of Yang disclose the semiconductor structure as claimed in claim 4 as applied above, and Figs. 4A-4B of Yang further disclose wherein the third conductive layer patterns (M3) and the conductive routing (116) belong to the same level of conductive layers of the interconnect structure (interconnection structure shown in Fig. 4A-4B).
Regarding claim 10, Figs. 4A-4B of Yang disclose the semiconductor structure as claimed in claim 4 as applied above, and Figs. 4A-4B of Yang further wherein the shielding structure (M1-MT) further comprises:
conductive vias (Fig. 4B, vias V1-V4, ¶ [0027]) close to the opposite side surfaces of the conductive routing (116), wherein the first conductive layer is electrically connected to the second conductive layer by the conductive vias (V1-V4) and the third conductive layer pattern.
Regarding claim 16, Figs. 2 and 4A of Yang disclose a semiconductor die (100A), comprising:
a circuit region (102);
a seal ring region (104, 105, 108) surrounding the circuit region (102), wherein the seal ring region (104, 105, 108) comprises a buffer zone (105) surrounding a boundary of the circuit region (102);
an electronic circuit (112) disposed in the circuit region (102);
a seal ring structure (104) disposed in the seal ring region (104, 105, 108) and surrounding the circuit region (102), wherein the seal ring structure (104) is separated from the boundary of the circuit region (102) by the buffer zone (105); and
a signal routing (M1-MT) disposed in the buffer zone (105) and extending into the circuit region (102), wherein the signal routing (M1-MT) is electrically connected to the electronic circuit (112).
Regarding claim 17, Figs. 2 and 4A of Yang disclose the semiconductor structure as claimed in claim 16 as applied above, and Figs. 4A-4B of Yang further disclose comprising:
a semiconductor substrate (103), wherein the seal ring structure (104) and the signal routing (M1-MT) are disposed on the semiconductor substrate (103);
an interconnect structure (interconnection structure shown in Fig. 4A-4B) disposed on the semiconductor substrate (103); and
a shielding structure (M1-MT) disposed in the interconnect structure (interconnection structure shown in Fig. 4A-4B) in the buffer zone (105), wherein the shielding structure (M1-MT) surrounds and is separated from the signal routing (M1-MT), wherein the shielding structure (M1-MT) comprises:
a first conductive layer pattern (M4) and a second conductive layer pattern (M2) located on opposite surfaces of the signal routing (M1-MT); and
third conductive layer patterns (M3) located beside the signal routing (M1-MT) and interposed between the first conductive layer pattern (M4) and the second conductive layer pattern (M2).
Regarding claim 18, Figs. 4A-4B of Yang disclose the semiconductor structure as claimed in claim 17 as applied above, and Figs. 4A-4B of Yang further disclose wherein the shielding structure (M1-MT) further comprises:
conductive vias (V1-V4) close to opposite side surfaces of the signal routing (M1-MT), wherein the first conductive layer is electrically connected to the second conductive layer by the conductive vias (V1-V4) and the third conductive layer pattern.
Regarding claim 19, Figs. 4A-4B of Yang disclose the semiconductor structure as claimed in claim 17 as applied above, and Figs. 4A-4B of Yang further disclose wherein the first conductive layer pattern (M4), the second conductive layer pattern (M2) and the signal routing (M1-MT) belong to different levels of conductive layers of the interconnect structure (interconnection structure shown in Fig. 4A-4B), and wherein the shielding structure (M1-MT) is grounded.
Claims 1, and 14-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Huang et al. (US 20230317638 A1) herein after “Huang”.
Regarding claim 1, Figs. 6-7 of Huang disclose a semiconductor structure (Fig. 7, semiconductor structure 100, ¶ [0017]), comprising:
a semiconductor substrate (Fig. 7, substrate 202, ¶ [0041]) having a circuit region (Fig. 6, circuit regions 150, ¶ [0017]) and a seal ring region (Fig. 7, inner seal rings 300, outer seal ring 350, redundant regions 400s, ¶ [0020]) surrounding the circuit region (150);
an electronic circuit (“a circuit region (or IC die) 150”, ¶ [0017]) disposed on the semiconductor substrate (202) in the circuit region (150);
a first seal ring (Fig. 7, sub seal ring, 212b, ¶ [0040]) disposed on the semiconductor substrate (202) in the seal ring region (350, 400s, 300) and surrounding the circuit region (150);
a buffer zone (Fig. 7, redundant regions 400s, ¶ [0020]) located in the seal ring region (350, 400s, 300) and interposed between the circuit region (150) and the first seal ring (212b), wherein the first seal ring (212b) is separated from the circuit region (150) by the buffer zone (400s); and
a conductive routing (Fig. 7, functional patterns 410, ¶ [0020]) disposed on the semiconductor substrate (202) in the buffer zone (400s), wherein the conductive routing (410) is electrically connected to the electronic circuit (Fig. 6, “another functional pattern 410 is connected to the circuit region 150 by a connection 414”, ¶ [0026]).
Regarding claim 14, Figs. 6-7 of Huang disclose the semiconductor structure as claimed in claim 1 as applied above, and Figs. 2 and 7 of Huang further disclose comprising:
a second seal ring (Fig. 7, sub seal ring, 212c, ¶ [0040]) disposed on the semiconductor substrate (202) in the seal ring region (350, 400s, 300), wherein the second seal ring (212c) surrounds the first seal ring (212b) and is surrounded by a scribe line region (Fig. 2, scribe lines 180, ¶ [0041]) of the semiconductor substrate (202), wherein the conductive routing (410) is separated from the second seal ring (212c).
Regarding claim 15, Figs. 2 and 7 of Huang disclose the semiconductor structure as claimed in claim 14 as applied above, and Figs. 7-8 of Huang further disclose comprising:
an interconnect structure (interconnection structure shown in Figs. 7-8) disposed on the semiconductor substrate (202), wherein the interconnect structure (interconnection structure shown in Figs. 7-8) comprises:
dielectric layers (Fig. 7, dielectric layers 210, ¶ [0044]) laminated on the semiconductor substrate (202);
conductive layer patterns (Fig. 7, metal layers 251, ¶ [0043]) embedded in the dielectric layers (210); and
conductive vias (Fig. 7, metal vias 252, ¶ [0043]) alternately arranged with and electrically connected to the conductive layer patterns (251),
wherein each of the first seal ring (212b) and second seal ring (212c) comprises the conductive layer patterns (251) alternately arranged with and electrically connected to the conductive vias (252) in the seal ring region (Fig. 7, “each of the sub seal rings 212a, 212b, 212c, and 212d further includes multiple metal layers 251 stacked one over another and vertically connected by metal vias 252”, ¶ [0043]), and the conductive layer patterns (251) of the first seal ring (212b) and second seal ring (212c) are located from a bottom-most level to a top-most level of conductive layers of the interconnect structure (interconnection structure shown in Figs. 7-8).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20110266541 A1) in view of Hsu (US 20070085172 A1).
Regarding claim 5, Figs. 4A-4B of Yang disclose the semiconductor structure as claimed in claim 4 as applied above, but Yang fails to disclose wherein the conductive routing is a signal routing, and the shielding structure is grounded.
In the similar field of endeavor of system-on-chip (SoC) technology, Fig. 4 of Hsu discloses wherein the conductive routing (Fig. 4, signal line 320, ¶ [0025]) is a signal routing, and the shielding structure (Fig. 4, grounded lines 340, ¶ [0026]) is grounded (“the signal line 320 may be accompanied with two adjacent grounded lines 340”, ¶ [0026]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Yang with the routing as disclosed by Hsu, to reduce coupling on the conductive routing (see Hsu, ¶ [0026]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20110266541 A1) in view of Yamanoue et al. (US 20070170591 A1) herein after “Yamanoue”.
Regarding claim 11, Figs. 2 and 4A of Yang disclose the semiconductor structure as claimed in claim 1 as applied above, but Yang fails to disclose comprising:
dummy patterns disposed on the semiconductor substrate in the buffer zone.
In the similar field of endeavor of semiconductor devices, Fig. 3 of Yamanoue discloses comprising:
dummy patterns (Fig. 3, dummy patterns 38b, ¶ [0037]) disposed on the semiconductor substrate (Fig. 3, silicon substrate 10, ¶ [0036]) in the buffer zone (Fig. 3, “dummy pattern region”, ¶ [0037]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Yang with the dummy patterns as disclosed by Yamanoue, to reduce the impact of mechanical and thermal stress (see Yamanoue, ¶ [0018]).
Claims 12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20110266541 A1) in view of Yamanoue (US 20070170591 A1) as evidenced by Hu et al. (US 20190164914 A1) herein after “Hu”.
Regarding claim 12, Yang and Yamanoue together disclose the semiconductor structure as claimed in claim 11 as applied above, but Yang and Yamanoue fail to explicitly disclose wherein the dummy patterns are electrically floating. However, Yamanoue discloses dummy patterns in ¶ [0037]. Dummy patterns are often floating as disclosed in, for example, ¶ [0023] of Hu, “Some of these bond pads may be… “dummy,” that is, electrically decoupled (e.g., floating) from any component with in the die”. Therefore, one of ordinary skill in the art would recognize that the dummy patterns disclosed by Yamanoue render obvious the floating dummy patterns of the instant application.
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Yang with the dummy patterns as disclosed by Yamanoue, to reduce the impact of mechanical and thermal stress (see Yamanoue, ¶ [0018]).
Regarding claim 20, Figs. 4A-4B of Yang disclose the semiconductor structure as claimed in claim 17 as applied above, but Yang fails to disclose comprising:
dummy patterns disposed on the semiconductor substrate in the buffer zone, wherein the dummy patterns are electrically floating.
In the similar field of endeavor of semiconductor devices, Fig. 3 of Yamanoue discloses comprising:
dummy patterns (Fig. 3, dummy patterns 38b, ¶ [0037]) disposed on the semiconductor substrate (Fig. 3, silicon substrate 10, ¶ [0036]) in the buffer zone (Fig. 3, “dummy pattern region”, ¶ [0037]).
Yamanoue fails to explicitly disclose wherein the dummy patterns are electrically floating. However, Yamanoue discloses dummy patterns in ¶ [0037]. Dummy patterns are often floating as disclosed in, for example, ¶ [0023] of Hu, “Some of these bond pads may be… “dummy,” that is, electrically decoupled (e.g., floating) from any component with in the die”. Therefore, one of ordinary skill in the art would recognize that the dummy patterns disclosed by Yamanoue render obvious the floating dummy patterns of the instant application.
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Yang with the dummy patterns as disclosed by Yamanoue, to reduce the impact of mechanical and thermal stress (see Yamanoue, ¶ [0018]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20110266541 A1) and Yamanoue (US 20070170591 A1) in further view of Nanjo et al. (US 20040089915 A1) herein after “Nanjo”.
Regarding claim 13, Yang and Yamanoue together disclose the semiconductor structure as claimed in claim 11 as applied above, but the combination fails to disclose wherein the dummy patterns comprise dummy active regions surrounded by isolation features in the semiconductor substrate, dummy poly patterns, dummy conductive patterns or a combination thereof.
In the similar field of endeavor of semiconductor devices, Fig. 2 of Nanjo discloses wherein the dummy patterns comprise dummy active regions (Fig. 2, active region dummies 18, ¶ [0054]) surrounded by isolation features (Fig. 2, isolation region 4, ¶ [0059]) in the semiconductor substrate (Fig. 2, silicon substrate 1, ¶ [0059]), dummy poly patterns, dummy conductive patterns or a combination thereof.
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Yang with the dummy active regions as disclosed by Nanjo, to ensure uniform manufacturing and reduce defects (see Nanjo, ¶ [0037]).
Conclusion
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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