DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this office action and presented for examination. Claims 1, 7, and 16 are newly amended by the response received November 26, 2025.
Full faith and credit have been given to Previous Examiner’s search and grounds of rejection. Current Examiner notes that the instant prior art rejections track the prior art rejections presented by Previous Examiner in the previous office action dated August 27, 2025; as such, the format of the instant prior art rejections has been largely maintained from the previous prior art rejections for consistency.
Claim 6 is associated with a “Currently Amended” status identifier, but does not appear to be amended. It is unclear as to whether an amendment was inadvertently omitted.
Specification
The disclosure is objected to because of the following informalities. Appropriate correction is required.
Page 2 of the response received November 26, 2025, conveys “Please amend the specification as follows: -- Add the following paragraph between paragraphs [0004] and [0005] on page 2 of the specification as originally filed: FIG. 2 illustrates a controller hierarchy that dispatches instructions to a reconfigurable systolic array and one or more processing units in a processing system, according to some embodiments.” However, the controller hierarchy 200 (which appears to itself encompass all elements in FIG. 2, including shader engines 210-212, which, according to original paragraph [0033], are implemented using one or more systolic arrays and one or more processing units), does not appear to be disclosed to itself dispatch instructions from the overall controller hierarchy 200 to a reconfigurable systolic array and one or more processing units in a processing system. Therefore, the newly added brief description of FIG. 2 does not appear to track FIG. 2 itself.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “in response to a reconfiguration of the systolic array that is to be used to process the instructions and in response to no conflict between the reconfiguration and a current configuration of the systolic array used by a previously dispatched packet that is executing on the systolic array, dispatching reconfiguration instructions to reconfigure the systolic array concurrently with execution of the previously dispatched packet by the processing unit” in lines 5-11. However, the metes and bounds of this limitation are indefinite. For example, on one hand, this limitation conveys that dispatching occurs in response to reconfiguring the systolic array (“in response to a reconfiguration of the systolic array … dispatching”); in other words, this limitation conveys that the dispatching occurs after reconfiguring the systolic array. However, on the other hand, the limitation also conveys that the recited dispatching is to reconfigure the systolic array (“dispatching reconfiguration instructions to reconfigure the systolic array”); in other words, this limitation also conveys that the dispatching occurs before reconfiguring the systolic array. Therefore, it is indefinite as to whether the dispatching occurs before or after reconfiguring the systolic array.
Claim 1 recites the limitation “the systolic array that is to be used to process the instructions” in lines 5-6. However, there is insufficient antecedent basis for this limitation in the claims.
Claims 2-6 are rejected for failing to alleviate the rejections of claim 1 above.
Claim 2 recites the limitation “The method of claim 1, further comprising: … dispatching the reconfiguration instructions for execution…” in line 4. However, it is indefinite, in view of the deletion of “for execution” in claim 1, line 9, as to whether the recited dispatching further limits, or is distinct from, “dispatching reconfiguration instructions” in claim 1, lines 8-9.
Claim 5 recites the limitation “The method of claim 1, further comprising: reconfiguring the systolic array based on the reconfiguration instructions” in lines 1-2. Claim 1 recites the limitation “in response to a reconfiguration of the systolic array that is to be used to process the instructions and in response to no conflict between the reconfiguration and a current configuration of the systolic array used by a previously dispatched packet that is executing on the systolic array, dispatching reconfiguration instructions to reconfigure the systolic array concurrently with execution of the previously dispatched packet by the processing unit” in lines 5-11. However, the metes and bounds of the limitation of claim 5 in the context of the limitation of claim 1 are indefinite. For example, on one hand, the limitation of claim 1 conveys that dispatching occurs in response to reconfiguring the systolic array (“in response to a reconfiguration of the systolic array … dispatching”); in other words, this limitation conveys that the dispatching occurs after reconfiguring the systolic array. However, on the other hand, the limitation of claim 5 conveys that reconfiguring the systolic array is based on the reconfiguration instructions (“reconfiguring the systolic array based on the reconfiguration instructions”); in other words, the limitation of claim 5 implicitly conveys that the dispatching of the reconfiguration instructions occurs before reconfiguring the systolic array. Therefore, it is indefinite as to whether the dispatching occurs before or after reconfiguring the systolic array.
Claim 6 is rejected for failing to alleviate the rejection of claim 5 above.
Claim 7 recites the limitation “dispatch reconfiguration instructions to reconfigure the at least one systolic array concurrently with execution of a previously dispatched packet by the at least one processing unit in response to a reconfiguration of the systolic array that is to be used to process the instructions and in response to no conflict between the reconfiguration and a current configuration of the systolic array used by the previously dispatched packet that is executing on the systolic array” in lines 9-16. However, the metes and bounds of this limitation are indefinite. For example, on one hand, this limitation conveys that dispatching occurs in response to reconfiguring the systolic array (“dispatch … in response to a reconfiguration of the systolic array”); in other words, this limitation conveys that the dispatching occurs after reconfiguring the systolic array. However, on the other hand, the limitation also conveys that the recited dispatching is to reconfigure the systolic array (“dispatch reconfiguration instructions to reconfigure the at least one systolic array”); in other words, this limitation also conveys that the dispatching occurs before reconfiguring the systolic array. Therefore, it is indefinite as to whether the dispatching occurs before or after reconfiguring the systolic array.
Claim 7 recites the limitation “the systolic array that is to be used to process the instructions” in lines 12-13. However, there is insufficient antecedent basis for this limitation in the claims.
Claim 7 recites the limitation “command processor configured to: receive packets comprising instructions for execution on the at least one processing unit or the at least one systolic array and to dispatch the instructions to the at least one processing unit or the at least one systolic array” in lines 4-8. However, it is indefinite, in view of the newly added colon, as to whether the claim is intended to convey that the recited command processor is configured to dispatch the instructions, or whether the claim is intended to convey that the intended use for the recited receiving packets is to dispatch the instructions, or whether another interpretation is intended.
Claims 8-15 are rejected for failing to alleviate the rejections of claim 7 above.
Claim 14 recites the limitation “The apparatus of claim 13 … reconfigure the at least one systolic array based on the reconfiguration instructions” in lines 1-3. Claim 7, upon which claim 14 is indirectly dependent, recites the limitation “dispatch reconfiguration instructions to reconfigure the at least one systolic array concurrently with execution of a previously dispatched packet by the at least one processing unit in response to a reconfiguration of the systolic array that is to be used to process the instructions and in response to no conflict between the reconfiguration and a current configuration of the systolic array used by the previously dispatched packet that is executing on the systolic array” in lines 9-16. However, the metes and bounds of the limitation of claim 14 in the context of the limitation of claim 7 are indefinite. For example, on one hand, the limitation of claim 7 conveys that dispatching occurs in response to reconfiguring the systolic array (“dispatch … in response to a reconfiguration of the systolic array”); in other words, this limitation conveys that the dispatching occurs after reconfiguring the systolic array. However, on the other hand, the limitation of claim 14 conveys that reconfiguring the systolic array is based on the reconfiguration instructions (“reconfigure the at least one systolic array based on the reconfiguration instructions”); in other words, the limitation of claim 14 implicitly conveys that the dispatching of the reconfiguration instructions occurs before reconfiguring the systolic array. Therefore, it is indefinite as to whether the dispatching occurs before or after reconfiguring the systolic array.
Claim 15 is rejected for failing to alleviate the rejection of claim 14 above.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7,11-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Brewer (patent application publication No. 2021/0055964).
Brewer taught the invention as claimed (as to claim 1) including a method comprising: receiving, at a command processor (dispatch interface) that dispatches instructions to a processing unit and a systolic array (e.g., see figs.12,15,16 and paragraph 0120)[note the configurable circuits/tiles arranged in an array corresponds to the systolic array and the kernels correspond to the instructions], a packet comprising instructions (e.g., see fig. 19A)[note the call message corresponds to the packet comprising instructions (see paragraph 0202)] for execution on the systolic array(e.g., see paragraphs 0196,0183-0184 and fig. 10)[note the pipelined tiles correspond to the systolic array]; and in response to a reconfiguration of the systolic array that is to be used to process the instructions and in response to no conflict between the reconfiguration and a current configuration of the systolic array used by a previously dispatched packet that is executing on the systolic array, dispatching reconfiguration instructions to reconfigure the systolic array concurrently with execution of the previously dispatched packet by the processing unit(e.g., see paragraphs 0013 and 0301-0304)[note the self- configuration or self-reconfiguration correspond to reconfiguration instruction for concurrent execution where the transmission of the selection of the instruction is using gates and wires which would have provided instantaneous selection of the configuration or reconfiguration instruction which corresponds to the execution concurrently previously dispatched configuration packet. Note providing the next instruction index effectively dispatches the next instruction to a next tile which includes self-configuration instruction(s)].
Due to the similarities between claims 1 and 7; claim 7 is rejected for the same reasons as claim 1 above.
As to claim 2 Brewer taught The method of claim 1, further comprising: receiving an acknowledgment from the systolic array indicating that execution of the previously dispatched packet on the systolic array is complete(e.g., see paragraphs 0282- 0285,0292); and dispatching the reconfiguration instructions for execution on the systolic array in response to receiving the acknowledgment (e.g., see paragraphs 0294 and 298- 0300 and 0302 and fig. 17A-17C)[note when all data completions have been received the next thread is started which includes instruction(s) self-reconfiguration or self-configuration].
As to claim 3 Brewer taught The method of claim 1, wherein dispatching the reconfiguration instructions comprises dispatching information indicating at least one of an updated kernel for execution on nodes of the systolic array, an updated stream switch configuration indicating routing of packets between the nodes of the systolic array, or an updated buffer descriptor indicating a memory location, a stride, or a block size of information stored in a memory (e.g., see paragraph 0259).
As to claim 4 Brewer taught The method of claim 3 wherein the nodes of the systolic array are configured to store pluralities of buffer descriptors, and the method further comprising: fetching, to the nodes of the systolic array, the updated buffer descriptor concurrently with the nodes executing the previously dispatched packet using a previously stored buffer descriptor (e.g., see paragraphs 0202 and 0265 and 0208- 0210).
As to claim 5 Brewer taught The method of claim 1, further comprising: reconfiguring the systolic array based on the reconfiguration instructions concurrently with the processing unit executing the previously dispatched packet (e.g. see paragraph 0302).
As to claim 6 Brewer taught The method of claim 5, further comprising: dispatching instructions from the packet in response to receiving an acknowledgment indicating that the reconfiguration and execution of the previously dispatched packet is complete (e.g., see paragraphs 0300,0302-0303).
As to claim 11 Brewer taught The apparatus of claim 7, wherein the command processor is configured to wait for an acknowledgment from the at least one systolic array indicating that execution of the previously dispatched packet on the systolic array is complete and wherein the command processor is configured to dispatch the reconfiguration instructions for execution on the at least one systolic array in response to receiving the acknowledgment (e.g. see paragraphs 0202 and 0302)[note Brewer taught the tile 210 can commence execution once it has received sufficient completion messages and testing output for determining where to conditionally branch and selection of instruction(s) for another tile which implements self-reconfiguration].
As to claim 12 Brewer taught The apparatus of claim 7, wherein the command processor is configured to dispatch information indicating at least one of an updated kernel for execution on nodes of the at least one systolic array, an updated stream switch configuration indicating routing of packets between the nodes of the at least one systolic array, and an updated buffer descriptor indicating a memory location, a stride, or a block size of information stored in a memory (e.g., see paragraph 0202)[note Brewer taught at paragraph 0202- "The dispatch interface 225 has also maintained various counts (in registers 475) of the number of completion and data messages it will need to receive to know that kernel execution has completed, and will then assemble and transmit the work descriptor return data packets, with the resulting data, a call ID, the return information (e.g., address of the requestor)"
As to claim 13 Brewer taught The apparatus of claim 12, wherein the nodes of the systolic array are configured to store pluralities of buffer descriptors(e.g., see paragraph 0202) , and the apparatus further comprising: at least one management processor (dispatch interface 225) for the at least one systolic array, the at least one management processor being configured to fetch the updated buffer descriptor to the nodes of the at least one systolic array concurrently with the nodes executing the previously dispatched packet using a previously stored buffer descriptor (e.g., see fig. 10 and paragraphs 0225,0203).
As to claim 14 Brewer taught The apparatus of claim 13, wherein the at least one management processor(145,155) is configured to reconfigure the at least one systolic array based on the reconfiguration instructions concurrently with the at least one processing unit executing the previously dispatched packet (e.g., see figs. 7,8, 9A and paragraphs 0301-0302).
As to claim 15 Brewer taught The apparatus of claim 14, wherein the command processor is configured to dispatch instructions from the packets to the at least one management processor in response to receiving an acknowledgment indicating that the reconfiguration and execution of the previously dispatched packets are complete (e.g., see paragraphs 0282-0285,and 0292); (e.g., see paragraphs 0294 and-298- 0300 and 0302 and fig. 17A-17C)[note when all data completions have been received the next thread is started which includes instruction(s) self-reconfiguration or self-configuration].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8-10,16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brewer (patent application publication No. 2021/0055964).
As to claim 8 Brewer taught The apparatus of claim 7, but did not expressly detail wherein the command processor is configured to inspect a packet to determine whether the reconfiguration of the at least one systolic array is to be performed to process the instructions in the packet. However, Brewer taught any asynchronous network transmitting packets for execution and including work descriptor including call ID return values and configuration argument values (e.g., see paragraph 0201-0202). Therefore one of ordinary skill in the art would have been motivated to inspect the packets to determine the action to be performed by the packet including the type of configuration to be performed.
As to claim 9 Brewer taught The apparatus of claim 8, Also Brewer taught wherein the command processor is configured to determine whether a previously dispatched packet is executing on the at least one systolic array (e.g.. see paragraph 0294). As to the determination being in response to determining that reconfiguration of the at least one systolic array is to be performed, to process the instructions in the packet Brewer taught using the configuration multiplexer to determine reconfiguration is to be performed in a synchronous manner (e.g., see paragraph 0301-0302). Therefore one of ordinary skill would have been motivated to perform the determination of whether a previously dispatched packet is executing in response to determining reconfiguration is to be performed at least to ensure that the reconfiguration could be performed properly without conflict and therefore delaying reconfiguration until the there was no conflict.
As to claim 10 Brewer taught The apparatus of claim 9, wherein the command processor is configured to determine whether a previously dispatched packet is executing on the at least one systolic array in response to determining that reconfiguration of the at least one systolic array is to be performed to process the instructions (e.g., see paragraphs 0294 and 0301-0302)[note the reconfiguration as taught by Brewer was implemented to configure the array for processing instruction(s) (e.g., see paragraphs 0031 and 0076 and 0303).
As to claim 16, Brewer taught A method comprising: responsive to an indication that nodes of a systolic array are to be reconfigured to execute at least one first instruction (e.g., see paragraph 0302-0303); and selectively reconfiguring the nodes of the systolic array (e.g., see paragraph 0302) concurrently with execution of at least one second instruction on a processing unit based on whether at least one third instruction is executing on the systolic array [note Brewer taught conditional branching for executing one instruction or another instruction on a next tile when the tile is enabled for execution and the selecting the next instruction for a next tile dynamic reconfiguration is enabled] Brewer did not expressly detail reconfiguring concurrently based on whether a third instruction is executing. Brewer however taught three or more tiles executing instruction(s) (e.g., see figs. 7,12,16 and paragraph 0197) One of ordinary skill would have been motivated to perform the execution of the second instruction depending on whether a third instruction is executing on the tile(s) at least to prevent conflicts as to accessing resources such a memory or switches for transmission of data/instructions.
As to claim 17 Brewer taught The method of claim 16, wherein selectively reconfiguring the nodes comprises reconfiguring the nodes concurrently with execution of the at least one second instruction on the processing unit (e.g. see paragraph 0302) but did not expressly detail it was in response to determining that there is no conflict between the reconfiguration and a current configuration used by the at least one third instruction However Brewer taught at least three or more tiles that execute the instruction(s)(e.g. see fig. 7) It would have been obvious to one of ordinary skill to determine that there is no conflict between the current configuration and a third instruction executing on a third tile when a instruction that reconfigures a first tile is performed and this would ensure that there is no conflicting access to switches or memory that would either slow the reconfiguration of allow access to shared memory where another instruction could overwrite the data used by the reconfiguration].
As to claim 18 Brewer taught The method of claim 16, wherein selectively reconfiguring the nodes comprises reconfiguring the nodes in response to receiving acknowledgement that execution of the at least one third instruction on the systolic array is complete (e.g., see paragraphs 0300, 0302-0303).
As to claim 19 Brewer taught The method of claim 16, wherein selectively reconfiguring the nodes of the systolic array comprises dispatching information indicating at least one of an updated kernel for execution on the nodes of the systolic array, an updated stream switch configuration indicating routing of packets between the nodes of the systolic array, or an updated buffer descriptor indicating a memory location, a stride, or a block size of information stored in a memory (e.g., see paragraph 0202)[note Brewer taught at paragraph [0202] "The dispatch interface 225 has also maintained various counts (in registers 475) of the number of completion and data messages it will need to receive to know that kernel execution has completed, and will then assemble and transmit the work descriptor return data packets, with the resulting data, a call ID, the return information (e.g., address of the requestor)"]
As to claim 20 Brewer taught The method of claim 19, wherein the nodes of the systolic array are configured to store pluralities of buffer descriptors, and the method further comprising: fetching, to the nodes of the systolic array, the updated buffer descriptor concurrently with the nodes executing the at least one third instruction using a previously stored buffer descriptor (e.g., see paragraphs 0202 and 0265 and 0208- 0210).
Response to Arguments
Applicant on page 9 argues: ‘For example, on page 3 of the Office Action, the Office alleges that Brewer's "dispatch interface circuit" corresponds to the claimed "command processor" that dispatches instructions to both a processing unit and a systolic array, and that the reconfigurable circuits or tiles of Brewer correspond to the claimed systolic array. The Applicant respectfully disagrees. Brewer discloses a homogeneous reconfigurable computing fabric known as a "hybrid threading fabric (HTF)" composed of identical configurable circuits or tiles (see Brewer at paragraphs [0176]- [0183]) that communicate through a synchronous mesh and asynchronous packet network. Brewer's "dispatch interface" merely receives host messages and transmits asynchronous data packets to tiles within the same reconfigurable fabric (see Brewer at paragraphs [0201]-[0203]). Brewer contains no disclosure of a "processing unit" distinct from the tile-based array, nor any suggestion that its dispatch interface communicates concurrently with a separate data-parallel processor, such as a GPU, CPU, or NPU. In contrast, claim 1 requires a command processor that dispatches instructions to two different compute domains: a parallel "processing unit" and a distinct "systolic array". Brewer's disclosure of a single, monolithic reconfigurable array is therefore fundamentally different in structure and operation.’
However, Current Examiner submits that the recited command processor, under the broadest reasonable interpretation, may be taught by Brewer’s dispatch interface. Current Examiner further submits that the claims, under the broadest reasonable interpretation, do not mandate that the recited processing unit is separate from the recited systolic array. Current Examiner further submits that the claims, under the broadest reasonable interpretation, do not mandate that the dispatch interface communicates concurrently with a separate data-parallel processor, such as a GPU, CPU, or NPU. Current Examiner further submits that the claims do not require two different compute domains, a “parallel” processing unit, and a systolic array that is distinct from the processing unit. While Brewer’s invention may be fundamentally different from the overall instant invention, Current Examiner submits that Brewer nevertheless teaches the claimed limitations under the broadest reasonable interpretation.
Current Examiner also notes that claim 1 contains contingent limitations across lines 5-11 (“in response to a reconfiguration of the systolic array that is to be used to process the instructions and in response to no conflict between the reconfiguration and a current configuration of the systolic array used by a previously dispatched packet that is executing on the systolic array, dispatching reconfiguration instructions to reconfigure the systolic array concurrently with execution of the previously dispatched packet by the processing unit”). The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met — see MPEP 2111.04. For the purposes of compact prosecution, Current Examiner recommends amending the limitations to remove the contingent aspect of the limitations.
Applicant on page 9 argues: ‘The Office further relies on Brewer's description of "self-configuration or self- reconfiguration" of the tiles (see Brewer at paragraphs [0013] and [0301]-[0304]) as allegedly corresponding to the claimed "dispatching reconfiguration instructions to reconfigure the systolic array concurrently with execution of the previously dispatched packet by the processing unit". The Applicant respectfully disagrees. Brewer's discussion of "self-reconfiguration" merely describes that each tile may select the next instruction index based on local logic or conditional branching using multiplexers and gates (see Brewer at paragraphs [0301]- [0304]). This operation occurs internally within a single tile to determine its next instruction and does not constitute a "dispatching" of reconfiguration instructions from a command processor, as claimed. Nor does Brewer disclose any concurrent operation with a separate processing unit. The "instantaneous selection of an instruction index" by logic gates within a tile (see Brewer at paragraph [0303]) is not equivalent to system-level reconfiguration of a systolic array under command processor control. Brewer's self-configuration is automatic and local, whereas claim 1 requires a dispatch of reconfiguration instructions from a command processor to the systolic array in coordination with concurrent processing-unit execution.’
Regarding the argued dispatching limitation, Current Examiner first notes that claim 1 contains contingent limitations across lines 5-11 (“in response to a reconfiguration of the systolic array that is to be used to process the instructions and in response to no conflict between the reconfiguration and a current configuration of the systolic array used by a previously dispatched packet that is executing on the systolic array, dispatching reconfiguration instructions to reconfigure the systolic array concurrently with execution of the previously dispatched packet by the processing unit”). The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met — see MPEP 2111.04. For the purposes of compact prosecution, Current Examiner recommends amending the limitations to remove the contingent aspect of the limitations.
In addition, Current Examiner submits that the claim does not mandate that the dispatching of reconfiguration instructions is from a command processor. Current Examiner further submits that the claim does not mandate concurrent operation with a “separate” processing unit (although Current Examiner submits that Brewer discloses that the reconfigurable circuits of the systolic array operate concurrently). Current Examiner submits that the claim does not recite “system-level” reconfiguration, or that the reconfiguration is under command processor control. Current Examiner submits that claim 1 does not recite dispatching reconfiguration instructions “from a command processor”, or “coordination” with concurrent processing-unit execution.
Applicant on page 10 argues: ‘The Office also alleges that Brewer's system performs such reconfiguration concurrently with execution of previously dispatched packets, citing the asynchronous nature of Brewer's network (see Brewer at paragraphs [0183] and [0184]). However, Brewer teaches that reconfiguration of its kernels occurs serially, not concurrently. Brewer states that when a new kernel configuration is required, "the HTF circuit cluster waits for all previous work to complete and loads the new kernel configuration" (see Brewer at paragraph [0259]). This direct statement contradicts the claimed requirement of concurrent reconfiguration with another processor's execution. Brewer's asynchronous message network enables non-deterministic packet arrival order, but it does not describe or suggest concurrent reconfiguration of the computing fabric while other processors continue execution.’
Regarding the argued reconfiguration subject matter, Current Examiner first notes that claim 1 contains contingent limitations across lines 5-11 (“in response to a reconfiguration of the systolic array that is to be used to process the instructions and in response to no conflict between the reconfiguration and a current configuration of the systolic array used by a previously dispatched packet that is executing on the systolic array, dispatching reconfiguration instructions to reconfigure the systolic array concurrently with execution of the previously dispatched packet by the processing unit”). The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met — see MPEP 2111.04. For the purposes of compact prosecution, Current Examiner recommends amending the limitations to remove the contingent aspect of the limitations.
Current Examiner further notes that Brewer discloses multiple HTF circuit clusters (see paragraph [0180]) and submits that the serial aspect of Brewer, as noted, is within an HTF circuit cluster. Current Examiner further notes that the self-configuration and self-reconfiguration aspects of Brewer were relied upon to teach the reconfiguration of claim 1, and these self-configurations and self-reconfigurations may occur concurrent to execution in other configurable circuits, within or outside a particular HTF circuit cluster. Current Examiner further notes that the self-configuration and self-reconfiguration aspects of Brewer entail execution that entails reconfiguring, such that the execution is concurrent with the reconfiguring.
Applicant on page 10 argues: ‘Additionally, claim 1 requires that a "conflict" does not exist between the reconfiguration and the current configuration of the systolic array used by a previously dispatched packet. Brewer does not disclose any such conflict determination. Brewer's architecture either (1) loads a new kernel after all previous threads complete (see Brewer at paragraph [0259]), or (2) performs conditional branching within a tile, which inherently assumes compatibility with the current configuration (see Brewer at paragraph [0301]). There is no concept in Brewer of evaluating configuration conflicts or selectively serializing or parallelizing reconfiguration based on such conflicts. By contrast, claim 1 requires that when a conflict exists, the reconfiguration is deferred, but when no conflict exists, the reconfiguration instructions are dispatched for concurrent execution with the processing unit's ongoing task. This conditional, conflict-aware concurrency is entirely absent from Brewer.’
Regarding the argued conflict and dispatching reconfiguration instructions subject matter, Current Examiner first notes that claim 1 contains contingent limitations across lines 5-11 (“in response to a reconfiguration of the systolic array that is to be used to process the instructions and in response to no conflict between the reconfiguration and a current configuration of the systolic array used by a previously dispatched packet that is executing on the systolic array, dispatching reconfiguration instructions to reconfigure the systolic array concurrently with execution of the previously dispatched packet by the processing unit”). The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met — see MPEP 2111.04. For the purposes of compact prosecution, Current Examiner recommends amending the limitations to remove the contingent aspect of the limitations.
In addition, Current Examiner notes that claim 1 does not require a conflict “determination” or “evaluation” or selectively serializing reconfiguration. Current Examiner further notes that claim 1 does not recite deferring reconfiguration.
Applicant across pages 10-11 argues: ‘Moreover, Brewer does not teach or suggest that any "processing unit" concurrently executes a "previously dispatched packet" during the reconfiguration of the array. Brewer's tiles all belong to the same reconfigurable fabric, and there is no disclosure of a parallel processor executing separate instructions concurrently with fabric reconfiguration. The only other processing entities described in Brewer are host processors or the hybrid threading processor (see Brewer at paragraph [0178]), which operate as controllers or dispatching entities rather than concurrently executing compute units. Thus, Brewer lacks the claimed concurrent operation between two different computing domains.’
Regarding the argued subject matter, Current Examiner first notes that claim 1 contains contingent limitations across lines 5-11 (“in response to a reconfiguration of the systolic array that is to be used to process the instructions and in response to no conflict between the reconfiguration and a current configuration of the systolic array used by a previously dispatched packet that is executing on the systolic array, dispatching reconfiguration instructions to reconfigure the systolic array concurrently with execution of the previously dispatched packet by the processing unit”). The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met — see MPEP 2111.04. For the purposes of compact prosecution, Current Examiner recommends amending the limitations to remove the contingent aspect of the limitations.
Current Examiner further notes that the self-configuration and self-reconfiguration aspects of Brewer were relied upon to teach the reconfiguration of claim 1, and these self-configurations and self-reconfigurations may occur concurrent to execution in other configurable circuits, within or outside a particular HTF circuit cluster. Current Examiner also notes that the self-configuration and self-reconfiguration aspects of Brewer entail execution that entails reconfiguring, such that the execution is concurrent with the reconfiguring. Current Examiner additionally notes that the claims do not recite “different computing domains”.
Applicant on page 11 argues: “As explained below, Brewer fails to disclose or suggest the features of a command structure that conditionally performs concurrent reconfiguration of nodes in a systolic array while a separate processing unit executes another instruction based on whether an additional instruction is executing on the systolic array, as set forth in claim 16.”
Regarding the argued subject matter, Current Examiner first notes that claim 16 contains contingent limitations across lines 2-6 (“responsive to an indication that nodes of a systolic array are to be reconfigured to execute at least one first instruction, selectively reconfiguring the nodes of the systolic array concurrently with execution of at least one second instruction on a processing unit based on whether at least one third instruction is executing on the systolic array”). The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met — see MPEP 2111.04. For the purposes of compact prosecution, Current Examiner recommends amending the limitations to remove the contingent aspect of the limitations.
Current Examiner further notes that claim 16 does not require “a command structure” and a “separate” processing unit.
Applicant on page 12 argues: ‘Brewer's disclosure of "conditional branching" at paragraphs [0301]-[0304] does not describe or suggest any system-level or node-level reconfiguration of a systolic array in response to an indication to execute a first instruction while concurrently executing a second instruction on a separate processing unit. Brewer's so-called "conditional branching circuitry" (see Brewer at paragraph [0301]) merely selects, within a single tile, between two instruction indices stored in the tile's local instruction memory based on the output of an arithmetic or logic operation. The logic gates and multiplexers described in paragraphs [0301]-[0303] of Brewer perform only a simple branch or case selection between two preloaded instructions within a tile. Brewer explicitly states that "the current tile 210 conditionally specifies an alternate instruction for connected tiles 210 to execute, enabling the performance of one or more case statements" (see Brewer at paragraph [0303]). This local conditional selection of a next instruction index does not involve reconfiguring any inter-node connections, updating buffer descriptors, or uploading new kernel configurations as required by the claimed "selectively reconfiguring the nodes of the systolic array". Brewer's local instruction index selection is therefore not a reconfiguration of the array or its nodes, but a simple branch within a fixed datapath configuration.’
Regarding the argued subject matter, Current Examiner first notes that claim 16 contains contingent limitations across lines 2-6 (“responsive to an indication that nodes of a systolic array are to be reconfigured to execute at least one first instruction, selectively reconfiguring the nodes of the systolic array concurrently with execution of at least one second instruction on a processing unit based on whether at least one third instruction is executing on the systolic array”). The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met — see MPEP 2111.04. For the purposes of compact prosecution, Current Examiner recommends amending the limitations to remove the contingent aspect of the limitations.
Current Examiner further notes that the claim does not recite, for example, “system-level or node-level reconfiguration” and a “separate” processing unit. Current Examiner further notes that Brewer characterizes the conditional branching subject matter as self-configuration and self-reconfiguration, and therefore the aforementioned subject matter would be reasonably considered tot each the recited reconfiguring subject matter. Current Examiner notes that the claim does not mandate reconfiguring inter-node connections, updating buffer descriptors, or uploading new kernel configurations.
Applicant across pages 12-13 argues: ‘Furthermore, Brewer's disclosure contains no suggestion that such conditional branching occurs "concurrently with execution of at least one second instruction on a processing unit." Brewer's architecture, as described throughout paragraphs [0176]-[0183], is a homogeneous reconfigurable compute fabric (the "hybrid threading fabric") comprising multiple tiles interconnected by synchronous and asynchronous networks. The "dispatch interface" described in Brewer at paragraphs [0201]-[0203] merely dispatches messages to tiles within the same fabric. Brewer nowhere describes a separate "processing unit" distinct from the tile-based fabric that executes another instruction concurrently with reconfiguration of the array. Claim 1, by contrast, requires concurrency between two distinct computational domains. (a systolic array being reconfigured and a separate processing unit executing another instruction) based on whether a third instruction is executing on the systolic array. Brewer's system operates within a single homogeneous fabric, without any such inter-processor concurrency or coordination.’
Regarding the argued subject matter, Current Examiner first notes that claim 16 contains contingent limitations across lines 2-6 (“responsive to an indication that nodes of a systolic array are to be reconfigured to execute at least one first instruction, selectively reconfiguring the nodes of the systolic array concurrently with execution of at least one second instruction on a processing unit based on whether at least one third instruction is executing on the systolic array”). The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met — see MPEP 2111.04. For the purposes of compact prosecution, Current Examiner recommends amending the limitations to remove the contingent aspect of the limitations.
Current Examiner additionally notes that the claim does not recite a “separate” processing unit or two distinct computational domains.
Applicant on page 13 argues: ‘Brewer also does not disclose or suggest that its tile-level conditional branching is performed "based on whether at least one third instruction is executing on the systolic array". The logic in Brewer's tiles does not inspect or consider the execution state of other instructions on the array. Each tile makes an independent local selection of its next instruction index based solely on its own arithmetic output, as illustrated in FIG. 24 of Brewer Brewer nowhere describes or implies a determination of whether another instruction (let alone a "third instruction") is currently executing elsewhere in the array. Nor does Brewer suggest that this local instruction selection would occur concurrently with reconfiguration of other nodes. To the contrary, Brewer teaches that the configuration of the array (i.e., loading of kernels or instruction sets) occurs serially, after completion of previous work. Brewer explicitly states that "the HTF circuit cluster waits for all previous work to complete and loads the new kernel configuration" (see Brewer at paragraph [0259]). This statement directly contradicts the concept of "selectively reconfiguring" concurrently with another instruction's execution.’
Regarding the argued subject matter, Current Examiner first notes that claim 16 contains contingent limitations across lines 2-6 (“responsive to an indication that nodes of a systolic array are to be reconfigured to execute at least one first instruction, selectively reconfiguring the nodes of the systolic array concurrently with execution of at least one second instruction on a processing unit based on whether at least one third instruction is executing on the systolic array”). The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met — see MPEP 2111.04. For the purposes of compact prosecution, Current Examiner recommends amending the limitations to remove the contingent aspect of the limitations.
Current Examiner first generally notes that Applicant appears to be acknowledging that other configurable circuits may execute concurrent with reconfiguration of a configurable circuit. Current Examiner further notes that Brewer discloses multiple HTF circuit clusters (see paragraph [0180]) and submits that the serial aspect of Brewer, as noted, is within an HTF circuit cluster. Current Examiner further notes that the self-configuration and self-reconfiguration aspects of Brewer were relied upon to teach the reconfiguration of claim 16, and these self-configurations and self-reconfigurations may occur concurrent to execution in other configurable circuits, within or outside a particular HTF circuit cluster.
Applicant across pages 13-14 argues: ‘The Office's reasoning that a person of ordinary skill in the art would have been motivated to perform execution of the second instruction depending on whether a third instruction is executing to prevent conflicts in accessing shared resources such as memory or switches is unsupported by Brewer. Brewer's fabric inherently prevents resource conflicts by using asynchronous packet scheduling and flow control circuits to manage backpressure (see Brewer at paragraphs [0234] and [0235]). These built-in flow control mechanisms obviate any need for conditional or selective reconfiguration based on whether other instructions are executing. Indeed, Brewer's flow control circuit simply halts tile pipelines when buffer thresholds are reached and resumes operation when congestion clears; it does not suggest any higher-level instruction scheduling based on concurrent instruction execution states. Brewer, therefore, provides no teaching or motivation to modify its operation to introduce the claimed conflict-aware selective reconfiguration.’
Regarding the argued subject matter, Current Examiner first notes that claim 16 contains contingent limitations across lines 2-6 (“responsive to an indication that nodes of a systolic array are to be reconfigured to execute at least one first instruction, selectively reconfiguring the nodes of the systolic array concurrently with execution of at least one second instruction on a processing unit based on whether at least one third instruction is executing on the systolic array”). The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met — see MPEP 2111.04. For the purposes of compact prosecution, Current Examiner recommends amending the limitations to remove the contingent aspect of the limitations.
Current Examiner further notes that the claims does not mandate that the reconfiguring is based on whether at least one third instruction is executing on the systolic array. Rather, the claim can be reasonably interpreted to encompass execution of at least one second instruction being based on whether at least one third instruction is executed. Therefore, the claim does not mandate conflict-aware selective reconfiguration.
Applicant on page 14 argues: ‘Moreover, even if one were to assume, arguendo, that Brewer's conditional branching might be viewed as a form of "reconfiguration", there remains no disclosure or suggestion of concurrency with a processing unit executing a previously dispatched instruction. Brewer's architecture lacks a second processing domain, and thus there is no structural or functional basis for concurrency between an array reconfiguration and another processor's execution. Any assertion that a person of ordinary skill would modify Brewer to add such a capability is based on impermissible hindsight reconstruction. Brewer's system is self-contained and self- scheduling within a single compute fabric, and its teachings provide no motivation or reasonable expectation of success for introducing external concurrent execution control as claimed.’
Regarding the argued subject matter, Current Examiner first notes that claim 16 contains contingent limitations across lines 2-6 (“responsive to an indication that nodes of a systolic array are to be reconfigured to execute at least one first instruction, selectively reconfiguring the nodes of the systolic array concurrently with execution of at least one second instruction on a processing unit based on whether at least one third instruction is executing on the systolic array”). The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met — see MPEP 2111.04. For the purposes of compact prosecution, Current Examiner recommends amending the limitations to remove the contingent aspect of the limitations.
Current Examiner further notes that Brewer discloses multiple HTF circuit clusters (see paragraph [0180]) and submits that the serial aspect of Brewer, as noted, is within an HTF circuit cluster. Current Examiner further notes that the self-configuration and self-reconfiguration aspects of Brewer were relied upon to teach the reconfiguration of claim 16, and these self-configurations and self-reconfigurations may occur concurrent to execution in other configurable circuits, within or outside a particular HTF circuit cluster.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KEITH E VICARY/ Primary Examiner, Art Unit 2183
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