DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copies have been filed in Chinese Patent Application No. 202311596673.3, filed on 11/24/2023, and Chinese Patent Application No. 202410752415.8, filed on 6/11/2024.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDSs) submitted on 10/30/2025 and 2/5/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The title of the invention has been suggested as, “DISPLAY PANEL WITH A SHIELDING STRUCTURE COMPRISING A SHIELDING LAYER AND AN ISOLATION STRUCTURE, METHOD FOR MANUFACTURING DISPLAY PANEL WITH A SHIELDING STRUCTURE COMPRISING A SHIELDING LAYER AND AN ISOLATION STRUCTURE, AND DISPLAY APPARATUS”.
Appropriate corrections are required.
Claim Objections
Claims 17 and 23-26 are objected, because the following limitations/phrases should be aligned to the prior limitations/phrases to avoid 112 issues due to indefiniteness:
On lines 6-7 of claim 17, it is not clear what is meant by “opposite” in the phrase “the pixel opening is arranged opposite to the first opening”. For examining purpose, “the pixel opening is arranged opposite to the first opening” is considered to be “the pixel opening is arranged in the first opening”.
Claim 23, which is dependent on claim 20, recites “a first portion “, “a second portion”, and “a first opening”, which were already introduced in claim 20. This is confusing and not proper, and it is not immediately clear if the Applicant actually intended claim 23 to be dependent on claim 19 rather than claim 20. Therefore, for a proper interpretation of claim 23, claim 23 should be rephrased according to its intended dependency. For the purpose of examination, claim 23 is examined as it is currently phrased.
Claims 24-26 are objected because these claims depend on claim 23.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-8, 11-12, 14-16, and 19-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 2019/0237533 A1).
Regarding claim 1, Kim teaches a display panel (display unit 10, Figs. 4-8, [0066]) having a display area (display area DA, Fig. 4, [0067]) and a non-display area (peripheral area PA, Fig. 4, [0073]) arranged surrounding at least a portion of the display area (display area DA, Fig. 4), the display panel (display unit 10, Figs. 4, 6A, and 8) comprising:
a substrate (comprising substrate 100 ([0091]), inorganic insulating layer 210 ([0109]), and inorganic protection layer 205 ([0110]); Fig. 8: these layers will be referred as substrate);
an isolation structure (comprising pixel defining layer 208 and opposite electrode 223, Fig. 8, [0100], the pixel definition layer isolates different conductive elements and “The opposite electrode 223 may contact the second shielding layer 1270 via a hole 208H” ([0118]) and therefore provides electromagnetic isolation) formed at one side (upper side, Fig. 8) of the substrate (substrate, Fig. 8) and comprising a first portion (portions of pixel defining layer 208 and opposite electrode 223 in the display area DA, Fig. 8) located in the display area (display area DA, Fig. 8) and a second portion (portions of pixel defining layer 208 and opposite electrode 223 in the peripheral area PA, Fig. 8) located in the non-display area (peripheral area, Fig. 8), the first portion (portions of pixel defining layer 208 and opposite electrode 223 in the display area DA, Fig. 8) encircling a first opening (opening in the pixel defining layer 208 where the OLED is located, Fig. 8: the opening is formed by the pixel defining layer 208 and therefore, the pixel defining layer in the display area encircles the opening), and the second portion (portions of pixel defining layer 208 and opposite electrode 223 in the peripheral area DA, Fig. 8) encircling a second opening (via hole 208H, Fig. 8, [0118]: pixel defining layer 208 encircles the via hole 208H);
a light-emitting unit (organic light-emitting diode OLED, Fig. 8, [0108]) formed at one side (upper side, Fig. 8) of the substrate (substrate, Fig. 8) and located in the first opening (opening where the OLED is located, Fig. 8);
a shielding layer (second power supply wiring 170 comprising first shielding layer 1170 and second shielding layer 1270, Fig. 8, [0112]) at least partially formed in the second opening (via hole 208H, Fig. 8) and electrically connected to the second portion (portions of pixel defining layer 208 and opposite electrode 223 in the peripheral area DA, Fig. 8: first shielding layer is electrically connected to opposite electrode 223 in the via hole 208H); and
an electrically conductive layer (the layer including first sensing electrodes 410, first signal lines 415-1 through 415-2, and second signal lines 425-1 through 425-4, Figs. 6 and 8, [0084]) formed at a side of the shielding layer (second power supply wiring 170 comprising first shielding layer 1170 and second shielding layer 1270, Fig. 8), the light-emitting unit (organic light-emitting diode OLED, Fig. 8), and the isolation structure (comprising pixel defining layer 208 and opposite electrode 223, Fig. 8) being away from the substrate (substrate, Fig. 8).
Regarding claim 3, Kim teaches the display panel according to claim 1, wherein the electrically conductive layer (the layer including first sensing electrodes 410 and second signal lines 425-1 through 425-4, Fig. 8, [0084]) comprises a touch control layer (the layer including first sensing electrodes 410, second signal lines 425-1 through 425-4, and second signal lines 425-1 through 425-4; Figs. 6 and 8, [0086]: “The first sensing lines 410C1l through 410C4 and the second sensing lines 420R1 through 420R5 may be disposed on the display area DA and may be connected to a sensing signal pad 440 via the first and second signal lines 415-1 through 415-4 and 425-1 through 425-5 in the peripheral area PA.” where sensing is a touch-based sensing ([0053])) comprising a touch control wiring (second signal lines 425-1 through 425-5, Figs. 6 and 8) located in the non-display area (peripheral area PA, Fig. 8), and an orthographic projection of the touch control wiring (first signal lines 415-1 through 415-5, second signal lines 425-1 through 425-5, Figs. 6 and 8) on the substrate (substrate (see claim 1), Fig. 8) is located within an orthographic projection of the shielding layer (second power supply wiring 170 comprising first shielding layer 1170 and second shielding layer 1270, Fig. 8) on the substrate (substrate (see claim 1), Fig. 8), or within an orthographic projection of the isolation structure on the substrate.
Regarding claim 4, Kim teaches the display panel according to claim 3, wherein the substrate (comprising substrate 100 ([0091]), inorganic insulating layer 210 ([0109]), and inorganic protection layer 205 ([0110]); Fig. 8) comprises a metal layer (inorganic insulating layer 210 includes metal layers) comprising a metal wiring (data lines DL in the peripheral area PA, Fig. 8) located in the non-display area (peripheral area PA, Fig. 8), and an orthographic projection of the touch control wiring (second signal lines 425-1 through 425-5, Figs. 8) on the metal layer (inorganic insulating layer 210 includes metal layers) at least partially overlaps the metal wiring (data lines DL in the peripheral area PA, Fig. 8).
Regarding claim 5, Kim teaches the display panel according to claim 3, wherein the non-display area (peripheral area PA, Fig. 8) comprises at least a second opening (valley hole 206H, Fig. 8, [0122]), and the at least a second opening (valley hole 206VH, Fig. 8) is arranged surrounding the display area (display area DA, Fig, 8, [0122]: “the first and second insulating layers 206 and 207 disposed in the peripheral area PA may respectively include valley holes 206VH and 207VH.”, and therefore the valley hole 206H surrounds the display area DA (see also Fig. 4)).
Regarding claim 6, Kim teaches the display panel according to claim 5, wherein the touch control wiring (first signal lines 415-1 through 415-5 and second signal lines 425-1 through 425-5, Figs. 6 and 8) comprises a wiring segment (portions of first signal lines 415-1 through 415-5 and second signal lines 425-1 through 425-5 in the peripheral area PA, Figs. 6 and 8) extending surrounding a portion of the display area (right and left sides of the display area DA, Fig. 6), and an orthographic projection of the wiring segment (portions of first signal lines 415-1 through 415-5 and second signal lines 425-1 through 425-5 in the peripheral area PA, Figs. 6 and 8) on the substrate (substrate (see claim 1), Fig. 8) is located within an orthographic projection of the second opening (via hole 208H, Fig. 8) on the substrate (substrate (see claim 1), Fig. 8); and
the orthographic projection of the wiring segment (portions of first signal lines 415-1 through 415-5 and second signal lines 425-1 through 425-5 in the peripheral area PA, Figs. 6 and 8) on the substrate is located within the orthographic projection of the shielding layer (second power supply wiring 170 comprising first shielding layer 1170 and second shielding layer 1270, Fig. 8) on the substrate (substrate (see claim 1), Fig. 8).
Regarding claim 7, Kim teaches the display panel of claim 3, wherein the touch control wiring (first signal lines 415-1 through 415-5 and second signal lines 425-1 through 425-5, Figs. 6 and 8) comprises a wiring segment (portions of first signal lines 415-1 through 415-5 and second signal lines 425-1 through 425-5 in the peripheral area PA, Figs. 6 and 8) extending surrounding a portion of the display area (right and left sides of the display area DA, Fig. 6), a portion of an orthographic projection of the wiring segment (first signal lines 415-1 through 415-5 and second signal lines 425-1 through 425-5, Figs. 6 and 8) on the substrate (substrate (see claim 1), Fig. 8) is located within an orthographic projection of the second opening (via hole 208H, Fig. 8) on the substrate (substrate (see claim 1), Fig. 8), a portion of the orthographic projection of the wiring segment (first signal lines 415-1 through 415-5 and second signal lines 425-1 through 425-5, Figs. 6 and 8) on the substrate (substrate (see claim 1), Fig. 8) is located within an orthographic projection of the second portion (portions of pixel defining layer 208 and opposite electrode 223 in the peripheral area PA, Fig. 8) on the substrate, and an edge (the edge at the leftmost side in Fig. 8) of the orthographic projection of the second portion (portions of pixel defining layer 208 and opposite electrode 223 in the peripheral area PA, Fig. 8) on the substrate (substrate (see claim 1), Fig. 8) does not overlap the orthographic projection of the wiring segment (first signal lines 415-1 through 415-5 and second signal lines 425-1 through 425-5, Figs. 6 and 8) on the substrate (substrate (see claim 1), Fig. 8).
Regarding claim 8, Kim teaches the display panel according to claim 3, wherein the non-display area (peripheral area PA, Fig. 8) comprises a plurality of second openings (openings in the pixel definition layer 208 at the valley hole 206H and on the left side of the valley hole 206VH as shown in Fig 8), and the plurality of second openings (openings in the pixel definition layer 208 at the valley hole 206H and on the left side of the valley hole 206VH as shown in Fig 8) are distributed along a periphery of the display area (peripheral area PA, Fig. 8).
Regarding claim 9, while Kim teaches the display panel according to claim 8, wherein
the plurality of second openings (openings in the pixel definition layer 208 on the left side of the valley hole 206VH as shown in Fig 8) are uniformly distributed (Fig. 8: the openings are uniformly distributed towards the edge pf the peripheral region) in the non-display area (peripheral region PA, Fig. 8).
Regarding claim 11, Kim teaches the display panel according to claim 8, wherein
an extension direction (x direction in Figs. 6 and 8) of a portion of the second portion (portions of pixel defining layer 208 and opposite electrode 223 in the peripheral area PA, Fig. 8) located between two of the second openings (the openings along the x direction in Fig. 8) adjacent along the periphery of the display area (peripheral area PA, Figs. 6 and 8) intersects with an extension direction (y direction, Fig. 6) of the touch control wiring (first signal lines 415-1 through 415-5, second signal lines 425-1 through 425-5, Figs. 6 and 8).
Regarding claim 12, Kim teaches the display panel according to claim 8, wherein an orthographic projection of a portion of the second portion (portions of pixel defining layer 208 and opposite electrode 223 in the peripheral area PA, Fig. 8) located between two of the second openings (the openings along the x direction in Fig. 8) adjacent along the periphery of the display area (peripheral area PA, Fig. 8) on the substrate (substrate (see claim 1), Fig. 8) is a first projection, and the first projection partially overlaps the orthographic projection of the touch control wiring (first signal lines 415-1 through 415-5, second signal lines 425-1 through 425-5, Figs. 6 and 8) on the substrate (substrate (see claim 1), Fig. 8).
Regarding claim 14, Kim teaches the display panel according to claim 1, wherein the non-display area (peripheral area PA, Fig. 8) further comprises a levelling area (see leveling area as labeled in Illustrative Fig. 1, which is an annotated version of Fig. 8) located at a side of the second portion (portions of pixel defining layer 208 and opposite electrode 223 in the peripheral area PA, Illustrative Fig. 1) away from the display area (display area DA, Illustrative Fig. 1), the display panel further comprises an encapsulation layer (comprising the encapsulation member 300 and capping layer 230, Illustrative Fig. 1, ([0105]-[0106]) located at a side (upper side) of the shielding layer (second power supply wiring 170 comprising first shielding layer 1170 and second shielding layer 1270, Fig. 8) and the
light-emitting unit (organic light-emitting diode OLED, Fig. 8) away from the substrate (substrate, Illustrative Fig. 1) and between the substrate (substrate, Illustrative Fig. 1) and the electrically conductive layer (the layer including first sensing electrodes 410, first signal lines 415-1 through 415-2, and second signal lines 425-1 through 425-4 (Figs. 6 and 8) shown as electrically conductive layer in Illustrative Fig. 1), and along a direction perpendicular to a plane where the substrate is located (z direction in Illustrative Fig. 1), a thickness of a portion of the encapsulation layer (comprising the encapsulation member 300 and capping layer 230, Illustrative Fig. 1) within the levelling area (leveling area, Illustrative Fig. 1) is less than a thickness of a portion of the encapsulation layer (comprising the encapsulation member 300 and capping layer 230, Illustrative Fig. 1) located within the display area (display area DA, Illustrative Fig. 1) and less than a thickness of a portion of the encapsulation layer (the portion of the encapsulation member 300 and capping layer 230 between the leveling area and display area DA in Illustrative Fig. 1) located between the levelling area (leveling area, Illustrative Fig. 1) and the display area (display area DA, Illustrative Fig. 1);
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the encapsulation layer (comprising the encapsulation member 300 and capping layer 230, Illustrative Fig. 1) is in contact with a side surface of the isolation structure (comprising pixel defining layer 208 and opposite electrode 223, Illustrative Fig. 1) facing the second opening (via hole 208H, Illustrative Fig. 1).
Regarding claim 15, while Kim teaches the display panel according to claim 14, wherein
the shielding layer (second power supply wiring 170 comprising first shielding layer 1170 and second shielding layer 1270, Illustrative Fig. 1) comprises a first sub-portion (portion of the second shielding layer 1270 in the via home 208H, Illustrative Fig. 1) located in the second opening (via hole 208H, Illustrative Fig. 1) and a second sub-portion (portion of the second shielding layer 1270 touching the side surface of the pixel definition layer 208, see second sub-portion as shown Illustrative Fig. 1) located at a side (the left side surface of the pixel definition layer has a slope pointing away from the substrate, Illustrative Fig. 1) of the second portion (portions of pixel defining layer 208 and opposite electrode 223 in the peripheral area PA, Illustrative Fig. 1) away from the substrate (substrate, Illustrative Fig. 1), and the encapsulation layer (comprising the encapsulation member 300 and capping layer 230, Illustrative Fig. 1) is in contact with a side (top surface) of the second sub-portion (second sub-portion, Illustrative Fig. 1) away from the substrate (substrate, Illustrative Fig. 1); and
the encapsulation layer (comprising the encapsulation member 300 and capping layer 230, Illustrative Fig. 1) is in contact with a side surface (side surface at the border of the leveling area, Illustrative Fig. 1) of the isolation structure (comprising pixel defining layer 208 and opposite electrode 223, Illustrative Fig. 1) away from the second opening (via hole 208H, Illustrative Fig. 1).
Regarding claim 16, Kim teaches the display panel according to claim 1, wherein the isolation structure (comprising pixel defining layer 208 and opposite electrode 223, Fig. 8) comprises a first isolation portion (pixel defining layer 208, Fig. 8) and a second isolation portion (opposite electrode 223, Fig. 8), the second isolation portion (opposite electrode 223, Fig. 8) is located at a side (upper side in Fig. 8) of the first isolation portion (pixel defining layer 208, Fig. 8) away from the substrate (substrate (see claim 1), Fig. 8), and an orthographic projection of the second isolation portion (opposite electrode 223, Fig. 8) on the substrate (substrate (see claim 1), Fig. 8) covers (even though not completely) an orthographic projection of the first isolation portion (pixel defining layer 208, Fig. 8) on the substrate (substrate (see claim 1), Fig. 8).
Regarding claim 19, Kim teaches a display panel (display unit 10, Figs. 4-8, [0066]), having a display area (display area DA, Fig. 4, [0067]) and a non-display area (peripheral area PA, Fig. 4, [0073]) arranged surrounding at least a portion of the display area (display area DA, Fig. 4), the display panel comprising:
a substrate (comprising substrate 100 ([0091]), inorganic insulating layer 210 ([0109]), and inorganic protection layer 205 ([0110]); Fig. 8: these layers will be referred as substrate) comprising a circuit structure (comprising thin film transistor TFTs and their connections embedded in inorganic insulating layer 210, Fig. 8, [0093]);
a light-emitting unit (organic light-emitting diode OLED, Fig. 8, [0108]) formed at one side (upper side) of the substrate (substrate, Fig. 8) and located in the display area (display area DA, Fig. 8);
an electrically conductive layer (the layer including first sensing electrodes 410, first signal lines 415-1 through 415-2, and second signal lines 425-1 through 425-4, Figs. 6 and 8, [0084]) formed at a side (upper side, Fig. 8) of the light-emitting unit (organic light-emitting diode OLED, Fig. 8) away from the substrate (substrate, Fig. 8); and
a shielding structure (comprising second power supply wiring 170 ([0112]), pixel defining layer 208, and opposite electrode 223 ([0100]: the pixel definition layer isolates different conductive elements and “The opposite electrode 223 may contact the second shielding layer 1270 via a hole 208H” ([0118]) and therefore provides electromagnetic shielding), Fig. 8) arranged between the electrically conductive layer (the layer including first sensing electrodes 410, first signal lines 415-1 through 415-2, and second signal lines 425-1 through 425-4, Fig. 8) and the circuit structure (comprising thin film transistor TFTs and their connections embedded in inorganic insulating layer 210, Fig. 8) of the substrate (substrate, Fig. 8) and at least partially located in the non-display area (peripheral area PA, Fig. 8), and an orthographic projection of the shielding structure (comprising second power supply wiring 170, pixel defining layer 208, and opposite electrode 223, Fig. 8) on the substrate (substrate, Fig. 8) covering an orthographic projection of the electrically conductive layer (the layer including first sensing electrodes 410, first signal lines 415-1 through 415-2, and second signal lines 425-1 through 425-4, Fig. 8) on the substrate (substrate, Fig. 8).
Regarding claim 20, Kim teaches the display panel according to claim 19, wherein the shielding structure (comprising second power supply wiring 170, pixel defining layer 208, and opposite electrode 223, Fig. 8) comprises an isolation structure (comprising first shielding layer 1170 ([0112]), pixel defining layer 208 and opposite electrode 223, Fig. 8) formed at one side (upper side, Fig. 8) of the substrate (substrate, Fig. 8), the isolation structure (comprising pixel defining layer 208 and opposite electrode 223, Fig. 8) comprises a first portion (portions of pixel defining layer 208 and opposite electrode 223 in the display area DA, Fig. 8) located in the display area (display area DA, Fig. 8) and a second portion (portions of first shielding layer 1170, pixel defining layer 208 and opposite electrode 223 in the peripheral area PA, Fig. 8) located in the non-display area (peripheral area PA, Fig. 8), the first portion (portions of pixel defining layer 208 and opposite electrode 223 in the display area DA, Fig. 8) encircles a first opening (opening where the OLED is located, Fig. 8: the opening is formed by the pixel defining layer 208 and therefore, the pixel defining layer in the display area encircles the opening), and the light-emitting unit (organic light-emitting diode OLED, Fig. 8) is located in the first opening (opening where the OLED is located, Fig. 8) ;
an orthographic projection of the second portion (portions of first shielding layer 1170, pixel defining layer 208 and opposite electrode 223 in the peripheral area PA, Fig. 8) on the substrate (substrate, Fig. 8) overlaps an orthographic projection of the electrically conductive layer (the layer including first sensing electrodes 410 and second signal lines 425-1 through 425-4, Fig. 8) on the substrate (substrate, Fig. 8).
Regarding claim 21, Kim teaches the display panel according to claim 20, wherein
within the non-display area (peripheral area, Fig. 8), the orthographic projection of the second portion (portions of first shielding layer 1170, pixel defining layer 208 and opposite electrode 223 in the peripheral area PA, Fig. 8) on the substrate (substrate, Fig. 8) completely covers the orthographic projection of the electrically conductive layer (the layer including first sensing electrodes 410, first signal lines 415-1 through 415-2, and second signal lines 425-1 through 425-4, Fig. 8) on the substrate (substrate, Fig. 8);
at least a portion of film layers of the first portion (portions of pixel defining layer 208 and opposite electrode 223 in the display area DA, Fig. 8) and at least a portion of film layers of the second portion (portions of first shielding layer 1170, pixel defining layer 208 and opposite electrode 223 in the peripheral area PA, Fig. 8) have a same material and are manufactured in a same layer (pixel defining layer 208 and opposite electrode 223 of the two portions are the same layers, and therefore are from the same materials and parts of the same layer);
the second portion (portions of first shielding layer 1170, pixel defining layer 208 and opposite electrode 223 in the peripheral area PA, Figs. 4, 6 and 8) is arranged surrounding the display area (display area DA, Figs, 4, 6, and 8) in the non-display area (peripheral area PA, Figs. 4, 6, and 8).
Regarding claim 22, Kim teaches the display panel according to claim 19, wherein the light-emitting unit comprises a first electrode (pixel electrode 221, Fig. 8, [0100]), a light-emitting functional layer (intermediate layer 222, Fig. 8, [0102]: “intermediate layer 222 may have a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), …”), and a second electrode (opposite electrode 223, Fig. 8, [0100]) stacked along a direction away from the substrate (substrate, Fig. 8), and the shielding structure (comprising second power supply wiring 170 ([0112]), pixel defining layer 208, and opposite electrode 223) comprises a shielding layer (second power supply wiring 170 comprising first shielding layer 1170 and second shielding layer 1270, Fig. 8, [0112]) manufactured in the same layer as the second electrode or the first electrode (pixel electrode 221, Fig. 8: second shielding layer 1270 is the same layer where the pixel electrode 221 is located);
an orthographic projection of the shielding layer (first shielding layer 1170 and second shielding layer 1270, Fig. 8) on the substrate (substrate, Fig. 8) overlaps the orthographic projection of the electrically conductive layer (the layer including first sensing electrodes 410, first signal lines 415-1 through 415-2, and second signal lines 425-1 through 425-4, Fig. 8) on the substrate (substrate, Fig. 8); and
in the non-display area (peripheral area PA, Fig. 8), the orthographic projection of the shielding layer (second shielding layer 1170 and second shielding layer 1270, Fig. 8) on the substrate (substrate, Fig. 8) completely covers the orthographic projection of the electrically conductive layer (the layer including first sensing electrodes 410, first signal lines 415-1 through 415-2, and second signal lines 425-1 through 425-4, Figs. 6 and 8) on the substrate (substrate, Fig. 8).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 10, 13, and 18 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2019/0237533 A1).
Regarding claim 10, while Kim teaches the display panel according to claim 8,
Kim does not disclose that
an area of an orthographic projection of at least a portion of the second openings on the substrate is greater than an area of an orthographic projection of the first opening on the substrate.
However, Kim discloses that “the first and second insulating layers 206 and 207 disposed in the peripheral area PA may respectively include valley holes 206VH and 207VH” (Fig. 8) and “Damage to the organic light-emitting diode OLED or the like due to penetration of external foreign matters through bulk of each of the first and second insulating layers 206 and 207 may be prevented through valley holes 206VH and 207VH”. Therefore, valley hole 206H is extends along or follows the edges of the periphery of the display region, and a person of ordinary skill in the art before the effective filing date of the claimed invention would expect an area of an orthographic projection of at least a portion of the second openings (valley hole 206H) on the substrate to be greater than an area of an orthographic projection of the first opening (single OLED region, Fig. 8) on the substrate. Thus, Kim teaches the limitations of claim 10.
Regarding claim 13, Kim teaches the display panel according to claim 8, wherein
the touch control wiring (second signal lines 425-1 through 425-5, Figs. 6 and 8) comprises a first segment (segment extending in the y direction, Fig. 6A) extending along a first direction (y direction, Fig. 6A), and an orthographic projection of a portion of the second openings (the openings on the left side of the valley hole 206VH, Fig. 8) on the substrate is a rectangle in shape (see Figs. 9A-C: openings follow the arrangement of holes of 1170H, and a person of ordinary skill in the art before the effective filing date of the claimed invention would make the holes the same shape to simplify the design), and sizes of a portion of the plurality of second openings (the openings on the left side of the valley hole 206VH, Fig. 8) along the first direction (y direction) are same (while Kim does not show the size of the openings in the y direction, because of the regular and same size arrangement of the holes 1170H and 1270H (Figs. 9A-C), the openings would be the same size in y direction which would simplify the design). Thus, Kim meets all the limitations of claim 13
Regarding claim 18, Kim teaches a method for manufacturing a display panel (display unit 10, Figs. 4-8, [0066]) having a display area (display area DA, Fig. 4, [0067]) and a non-display area (peripheral area PA, Fig. 4, [0073]) arranged surrounding at least a portion of the display area (display area DA, Fig. 4), the method (while Kim does not specifically disclose the steps of forming the device, a person of ordinary skill in the art before the effective filing date would understand that the method involves the general steps below) comprising:
providing a substrate (substrate 100, Fig. 8, [0091]);
forming an isolation structure (comprising pixel defining layer 208 and opposite electrode 223, Fig. 8, [0100], the pixel definition layer isolates different conductive elements and “The opposite electrode 223 may contact the second shielding layer 1270 via a hole 208H” ([0118]) and therefore provides electromagnetic isolation) at one side (upper side, Fig. 8) of the substrate (substrate, Fig. 8), the isolation structure (comprising pixel defining layer 208 and opposite electrode 223, Fig. 8) comprising a first portion (portions of pixel defining layer 208 and opposite electrode 223 in the display area DA, Fig. 8) located in the display area (display area DA, Fig. 8) and a second portion (portions of pixel defining layer 208 and opposite electrode 223 in the peripheral area PA, Fig. 8) located in the non-display area (peripheral area, Fig. 8), the first portion (portions of pixel defining layer 208 and opposite electrode 223 in the display area DA, Fig. 8) encircling a first opening (opening where the OLED is located, Fig. 8: the opening is formed by the pixel defining layer 208 and therefore, the pixel defining layer in the display area encircles the opening), and the second portion (portions of pixel defining layer 208 and opposite electrode 223 in the peripheral area DA, Fig. 8) encircling a second opening (via hole 208H, Fig. 8, [0118]);
forming a light-emitting unit (organic light-emitting diode OLED, Fig. 8, [0108]) within the first opening (opening where the OLED is located, Fig. 8);
forming a shielding layer (second power supply wiring 170 comprising first shielding layer 1170 and second shielding layer 1270, Fig. 8, [0112]) at a side (bottom surface, Fig. 8) of the isolation structure (comprising pixel defining layer 208 and opposite electrode 223, Fig. 8) away from the substrate (substrate 100, Fig. 8: bottom surface of the isolation structure is separated from the substrate), at least a portion of the shielding layer (second power supply wiring 170 comprising first shielding layer 1170 and second shielding layer 1270, Fig. 8) being formed in the second opening (via hole 208H, Fig. 8) and electrically connected to the second portion (portions of pixel defining layer 208 and opposite electrode 223 in the peripheral area DA, Fig. 8: first shielding layer is electrically connected to opposite electrode 223 in the via hole 208H); and
forming an electrically conductive layer (the layer including first sensing electrodes 410, first signal lines 415-1 through 415-2, and second signal lines 425-1 through 425-4, Figs. 6 and 8, [0084]) at a side (upper side, Fig. 8) of the shielding layer (second power supply wiring 170 comprising first shielding layer 1170 and second shielding layer 1270, Fig. 8), the light-emitting unit (organic light-emitting diode OLED, Fig. 8), and the isolation structure (comprising pixel defining layer 208 and opposite electrode 223, Fig. 8) away from the substrate (substrate 100, Fig. 8).
Allowable Subject Matter
Claims 2, 17, and 23-26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 2 and 17, claim 2, disclosing the limitation “the light-emitting material layer … comprises a first section located in the second opening and a second section located at a side of the second portion away from the substrate”, would be allowable if this limitation is incorporated in a claim combining claims 1 and 2.
Regarding closest prior art identified, Kim (US 2019/0237533 A1) teaches the display panel according to claim 1, wherein the light-emitting unit (organic light-emitting diode OLED, Fig. 8, [0108]) comprises a first electrode (opposite electrode 223, Fig. 8, [0100]), a light-emitting functional layer (intermediate layer 222, Fig. 8, [0102]: “intermediate layer 222 may have a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), …”) and a second electrode (pixel electrode 221, Fig. 8, [0100]) stacked along a direction (upper direction) away from the substrate (substrate, Fig. 8), and the shielding layer (second power supply wiring 170 comprising first shielding layer 1170 and second shielding layer 1270, Fig. 8) is manufactured in the same layer as the second electrode (pixel electrode 221, Fig. 8: second shielding layer 1270 is the same layer where the pixel electrode 221 is located);
the shielding layer (second power supply wiring 170 comprising first shielding layer 1170 and second shielding layer 1270, Fig. 8) comprises a first sub-portion (the portion at the second shielding layer 1270 located at the bottom of the via hole 208H, Fig. 8) located in the second opening (via hole 208H, Fig. 8) and a second sub-portion (the portion at the second shielding layer 1270 located on the bottom surface of the pixel defining layer 208, Fig. 8) located at a side of the second portion (bottom surface of the pixel defining layer 208, Fig. 8) away from the substrate (substrate, Fig. 8); and
the display panel further comprises a light-emitting material layer (emission layer EML within intermediate layer 222; emission layer EML is not shown in figures, [0102]: “intermediate layer 222 may have a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), …”), the light-emitting material layer (emission layer EML) is arranged in the same layer as the light-emitting functional layer (intermediate layer 222).
Kim, however, does not teach that
the light-emitting material layer comprises a first section located in the second opening and a second section located at a side of the second portion away from the substrate.
There has been no prior art identified that can modify Kim further to meet the limitation that “the light-emitting material layer … comprises a first section located in the second opening and a second section located at a side of the second portion away from the substrate.” when this limitation is further accompanied by the remaining limitations of claims 1 and 2. Therefore, claim 2 is objected.
Claim 17 is also objected because claim 17 directly depends on claim 2.
Regarding claims 23-26, claim 23, disclosing the limitation “the light-emitting material layer … comprises a first section located in the second opening and a second section located at a side of the second portion away from the substrate”, would be allowable if this limitation is incorporated in a claim combining claims 19-20 and 23.
Regarding closest prior art identified, Kim (US 2019/0237533 A1) teaches the display panel according to claim 20, wherein the shielding structure (comprising second power supply wiring 170, pixel defining layer 208, and opposite electrode 223, Fig. 8) comprises an isolation structure (comprising first shielding layer 1170 ([0112]), pixel defining layer 208 and opposite electrode 223, Fig. 8) and a shielding layer (second shielding 1270, Fig. 8) formed at one side (upper side of Fig. 8) of the substrate (substrate, Fig. 8), the isolation structure (comprising first shielding layer 1170 ([0112]), pixel defining layer 208 and opposite electrode 223, Fig. 8) comprises a first portion (portions of pixel defining layer 208 and opposite electrode 223 in the display area DA, Fig. 8) located in the display area (display area DA, Fig. 8) and a second portion (portions of first shielding layer 1170, pixel defining layer 208 and opposite electrode 223 in the peripheral area PA, Fig. 8) located in the non-display area (peripheral area PA, Fig. 8), the first portion (portions of pixel defining layer 208 and opposite electrode 223 in the display area DA, Fig. 8) encircles a first opening (opening where the OLED is located, Fig. 8: the opening is formed by the pixel defining layer 208 and therefore, the pixel defining layer in the display area encircles the opening), and the second portion (portions of first shielding layer 1170, pixel defining layer 208 and opposite electrode 223 in the peripheral area PA, Fig. 8) encircles a second opening (via hole 208H, Fig. 8, [0118]: pixel defining layer 208 encircles the via hole 208H);
the light-emitting unit (organic light-emitting diode OLED, Fig. 8, [0108]) is located in the first opening (opening in the pixel defining layer 208 where the OLED is located, Fig. 8), the shielding layer (second shielding 1270, Fig. 8) comprises a first sub-portion (the portion at the second shielding layer 1270 located at the bottom of the via hole 208H, Fig. 8) located in the second opening (via hole 208H, Fig. 8), and the first sub-portion (the portion at the second shielding layer 1270 located at the bottom of the via hole 208H, Fig. 8) is electrically connected to the second portion (portions of first shielding layer 1170, pixel defining layer 208 and opposite electrode 223 in the peripheral area PA, Fig. 8: first shielding layer is electrically connected to opposite electrode 223 in the via hole 208H);
the shielding layer (second shielding 1270, Fig. 8) further comprises a second sub-portion (the portion at the second shielding layer 1270 located on the bottom surface of the pixel defining layer 208, Fig. 8) located at a side (side and bottom surfaces of the pixel defining layer 208, Fig. 8) of the second portion (portions of first shielding layer 1170, pixel defining layer 208 and opposite electrode 223 in the peripheral area PA, Fig. 8) away from the substrate (substrate, Fig. 8: side and bottom surface are separated by other layers from the substrate);
the light-emitting unit comprises (organic light-emitting diode OLED, Fig. 8, [0108]) a first electrode (pixel electrode 221, Fig. 8, [0100]), a light-emitting functional layer (intermediate layer 222, Fig. 8, [0102]: “intermediate layer 222 may have a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), …”), and a second electrode (opposite electrode 223, Fig. 8, [0100]) stacked along a direction (upper direction in Fig. 8) away from the substrate (substrate, Fig. 8), and the shielding layer (second shielding 1270, Fig. 8) is manufactured in the same layer as the second electrode or the first electrode (pixel electrode 221, Fig. 8: second shielding layer 1270 is the same layer where the pixel electrode 221 is located); and
the display panel further comprises a light-emitting material layer (emission layer EML within intermediate layer 222; emission layer EML is not shown in figures, [0102]: “intermediate layer 222 may have a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), …”), the light-emitting material layer (emission layer EML) is arranged in the same layer as at least a portion of the light-emitting functional layer (intermediate layer 222)
at least a portion of film layers of the first portion (portions of pixel defining layer 208 and opposite electrode 223 in the display area DA, Fig. 8) and at least a portion of film layers of the second portion (portions of first shielding layer 1170, pixel defining layer 208 and opposite electrode 223 in the peripheral area PA, Fig. 8) have a same material and are manufactured in a same layer (pixel defining layer 208 and opposite electrode 223 of the two portions are the same layers, and therefore are from the same materials and parts of the same layer).
Kim, however, does not teach that
the light-emitting material layer comprises a first section located in the second opening and a second section located at a side of the second portion away from the substrate.
There has been no prior art identified that can modify Kim further to meet the limitation that “the light-emitting material layer … comprises a first section located in the second opening and a second section located at a side of the second portion away from the substrate.” when this limitation is further accompanied by the remaining limitations of claims 19-20 and 23. Therefore, claim 23 is objected.
Claim 24-26 are also objected because claim 23-26 directly depend on claim 23.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park (US 2020/0194534 A1) teaches a display device with a shielding structure which is relevant to all claims.
Yu (US 2023/0180574 A1) teaches a display device with a shielding structure which is relevant to all claims.
Sung (US 2023/0209977 A1) teaches a display device with a shielding structure which is relevant to all claims.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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