DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, filed 12/17/2025, with respect to the rejection of the claim(s), have been considered but are moot in view of the new ground of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s1, 2, 10, 11, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Vanaraj et al (US2016/0299724 A1) (hereinafter D1) and further in view of Kim et al (US2010/0295600 A1) (hereinafter D2).
Claim(s) 1, 2, 10, 11, 19 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by
Claim 1: D1 teaches a method of operating a memory package, comprising the steps of: preparing a plurality of memory dies ([0073]- Figs. 1, 11A), each memory die having a plurality of memory blocks with arrays of memory cells (e.g. [0076]), the plurality of memory dies including a plurality of user data dies that contain user data (Die0-Di2, Fig. 11A- [0145]) and an XOR die that contains XOR data (Die3- [0145]); detecting a read error during a read operation in a failed die of the plurality of user data dies ([0084]); reading some of the user data of the user data dies besides the failed die and reading some of the XOR data of the XOR die ([0145]); and performing a read recovery operation that includes an XOR operation using, as inputs, the user data of the user data dies besides the failed die and the XOR data of the XOR die ([0145]).
Not explicitly taught by D1 is that the dies are in a stacked arrangement and that the dies are all in electrical communication with a processing unit by way of a plurality of TSVs. However, such a technique was known in the art, before the effective filing date of the claimed invention, as disclosed by D2 (see Fig. 1. Fig. 3, and [0003]). Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to combine a known data management algorithm, as taught by D1, with a known, suitable hardware platform, as taught by D2, since such a modification would have been a predictable engineering combination.
As per claims 10 and 19, the claimed features are rejected similarly to claim 1 above.
Claim 2: D1 and D2 teach the method as set forth in claim 1, wherein the step of detecting the read error during the read operation includes a failing error correction code (ECC) operation ([0084]- D1).
As per claims 11 and 20, the claimed features are rejected similarly to claim 2 above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3-7 and 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over D1 and D2 as applied to claim 1 above, and further in view of Helmick et al (US 2021/0081273 A1) (hereinafter D3).
Claim 3: D1 and D2 teach the method as set forth in claim 2, but fail to teach that the user data in the plurality of user data dies and the XOR data in the XOR die are in a single bit per memory cell (SLC) storage scheme. However, D2 explicitly discloses that NAND flash memory may be implemented using SLC, MLC, TLC, or QLC ([0037], [0043], [0045]). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to use SLC, a well-known, reliable, and conventional storage scheme, for storing both user data and XOR data in the memory system taught by D1, particularly in applications where enhanced data integrity or simpler error recovery is desired.
As per claim 12, the claimed features are rejected similarly to claim 3 above.
Claim 4: D1, D2 and D3 teach the method as set forth in claim 3, but fail to teach that the SLC storage scheme of the user data is a first SLC storage scheme with a first threshold voltage Vt window, and the SLC storage scheme of the XOR data is a second SLC storage scheme that has a second threshold voltage window Vt that is greater than the first threshold voltage Vt window. However, D3 teaches adjusting read voltage thresholds (e.g. via “soft reads”) to improve data reliability and error recovery ([0088]). And since XOR data is critical for data reconstruction, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to store such critical data using a more robust storage scheme, such as an SLC scheme with a wider threshold voltage window, in order to reduce the likelihood of read errors. Utilizing a more robust storage scheme for critical data represents nothing more than a predictable design choice to improve overall system reliability.
As per claim 13, the claimed features are rejected similarly to claim 4 above.
Claim 5: D1, D2 and D3 teach the method as set forth in claim 4, but fail to teach that the first SLC storage scheme is associated with a first read pass voltage VREAD_1 and the second SLC storage scheme is associated with a second read pass voltage VREAD_2 that is greater than the first read pass voltage VREAD_1. D3 teaches that read recovery may involve adjusting read parameters, such as voltage levels, to enhance data accuracy ([0088]). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to employ a higher read pass voltage (VREAD2) in connection with the XOR data read stored in an SLC scheme in order to further ensure data integrity during read operations, particularly given the recognized criticality of XOR data in the recovery process. One of ordinary skill in the art would have found it obvious to make such an adjustment because using higher read voltage for critical data constitutes the predictable use of a known technique to improve reliability, and there would have been expectation of success for doing so.
As per claim 14, the claimed features are rejected similarly to claim 5 above.
Claim 6: D1, D2 and D3 teach the method as set forth in claim 4, but fail to teach that all of the memory cells programmed according to the first SLC storage scheme have threshold voltages below 2 V. However, D3 teaches that read recovery may involve adjusting read parameters, such as voltage levels, to enhance data accuracy ([0088]). Therefore, such a modification is considered to constitute a routine design choice well within the skill of the ordinary artisan. The recited specific threshold value of 2 V does not impart patentable distinction, as the selection of a particular threshold voltage for an SLC-based scheme would have been an obvious matter of design choice to one of ordinary skill in the art. In particular, varying the exact threshold voltage level constitutes nothing more than optimizing a result-effective variable to balance reliability and performance, and such optimization would have been expected to yield predictable results.
As per claim 15, the claimed features are rejected similarly to claim 6 above.
Claim 7: D1, D2 and D3 teach the method as set forth in claim 6, but fail to teach that some of the memory cells programmed according to the second SLC storage scheme have threshold voltages above 2 V. However, as noted above, D3 teaches the use of adjusted voltage thresholds for improve reliability. Therefore, using a higher threshold voltage for XOR data to enhance its integrity would have been an obvious extension of the teachings in the D2’s disclosure.
As per claim 16, the claimed features are rejected similarly to claim 7 above.
Claim(s) 8, 9, 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over D1.
Claim 8: D1 and D2 teach the method as set forth in claim 1, but fail to teach that the plurality of memory dies are all of similar construction such that for each address of each word line in any one of the memory dies, there is a corresponding word line with the same address in every other one of the plurality of memory dies. However, D1 describes a single relative memory address that identifies the same physical location (e.g. plane, block, page -[0127] & [0132]). Figure 11A shows a configuration where dies (Die0 – Die3) are addressed using a common XOR-based redundancy scheme, which would have implied identical addressing for parity recovery, for one of ordinary skill in the art, before the effective filing date of the claimed invention.
As per claim 17, the claimed features are rejected similarly to claim 8 above.
Claim 9: D1 and D2 teach the method as set forth in claim 8, wherein the step of detecting the read error during the read operation occurs when performing the read operation on a selected word line that has a selected address, and wherein the step of reading some of the user data and some of the XOR data includes reading the word lines that have the same selected address in the user data dies other than the failed die and in the XOR die. However, D1 teaches, in paragraph [0145], that during failure recovery, data is read from non-failed dies and the XOR die using the same addressing (e.g. …”by XORing the corresponding XOR value…with corresponding data values read from the other memory portions”). D1 also describes, in paragraphs [0100]-[0102], sub-request protocols where a single instruction portion contains a relative address applied to all dies, ensuring simultaneous access to the same word line across dies. Thus, the use of identical addressing across dies for efficiency (e.g., reduced overhead) was known in memory systems (e.g. RAID-like stripping) and XOR-based recovery was also a well-established technique for data redundancy. Therefore, combining these elements to enable parallel access during recovery would have been predictable to a POSITA, before the effective filing date of the claimed invention, because it merely applies existing redundancy techniques to a memory architecture with identical addressing.
As per claim 18, the claimed features are rejected similarly to claim 9 above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 1/26/2026