DETAILED ACTION
This Office action responds to Applicant’s invention filed on 06/26/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-20.
Information Disclosure Statement (IDS)
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Specification Objection
The specification has been checked to the extend necessary to determine the presence of possible minor errors. However, the Applicant’s cooperation is requested in correcting any errors of which Applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 and 13-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng (US 2020/0131028).
Regarding claim 1, Cheng shows (see, e.g., Cheng: figs. 3A-3N, 3N(1)-3N(5), and 4) all aspects of a method for producing a sensor system, comprising:
Providing a first semiconductor wafer 40/45/48/49/50/58
wherein:
A microelectromechanical sensor element 55 is structured in the first semiconductor wafer 40/45/48/49/50/58
Providing a second semiconductor wafer 70
Connecting the first semiconductor wafer 40/45/48/49/50/58 and the second semiconductor wafer 70 to cover the microelectromechanical sensor element 55
Etching a hole 76 through the second semiconductor wafer 70 from a side opposite a contact surface (between element 70 and 60) between the first semiconductor wafer 40/45/48/49/50/58 and the second semiconductor wafer 70
Regarding claim 2, Cheng shows (see, e.g., Cheng: figs. 3A-3N, 3N(1)-3N(5), and 4) that etching the hole 76 through the second semiconductor wafer 70 includes: etching the hole 62 through the contact surface (between element 70 and 60).
Regarding claim 3, Cheng shows (see, e.g., Cheng: figs. 3A-3N, 3N(1)-3N(5), and 4) that the hole 76 is provided with a side-wall insulation 82 (see, e.g., Cheng: par. [0037]).
Regarding claim 4, Cheng shows (see, e.g., Cheng: figs. 3A-3N, 3N(1)-3N(5), and 4) removing the side-wall insulation 82 on a hole bottom of the hole 76.
Regarding claim 5, Cheng shows (see, e.g., Cheng: figs. 3A-3N, 3N(1)-3N(5), and 4) producing a via 85/86 in the hole 76.
Regarding claim 6, Cheng shows (see, e.g., Cheng: figs. 3A-3N, 3N(1)-3N(5), and 4) that the via 85/86 directly contacts the microelectromechanical sensor element 55.
Regarding claim 7, Cheng shows (see, e.g., Cheng: figs. 3A-3N, 3N(1)-3N(5), and 4) that the via 85/86 extends through the contact surface (between element 70 and 60) between the first semiconductor wafer 40/45/48/49/50/58 and the second semiconductor wafer 70.
Regarding claim 13, Cheng shows (see, e.g., Cheng: figs. 3A-3N, 3N(1)-3N(5), and 4) all aspects of a method for producing a sensor system, comprising:
Connecting a first semiconductor wafer 40/45/48/49/50/58 and a second semiconductor wafer 70 to cover a microelectromechanical sensor element 55 structured in the first semiconductor wafer 40/45/48/49/50/58
Etching a hole 76 through a contact surface (between element 70 and 60) between the first semiconductor wafer 40/45/48/49/50/58 and the second semiconductor wafer 70 and from a side opposite the contact surface
Producing a via 85/86 in the hole 76
wherein:
the via 85/86 extends through the second semiconductor wafer 70 and through the contact surface (between element 70 and 60)
Regarding claim 14, Cheng shows (see, e.g., Cheng: figs. 3A-3N, 3N(1)-3N(5), and 4) that the hole 76 is provided with a side-wall insulation 82 (see, e.g., Cheng: par. [0037]).
Regarding claim 15, Cheng shows (see, e.g., Cheng: figs. 3A-3N, 3N(1)-3N(5), and 4) removing the side-wall insulation 82 on a hole bottom of the hole 76.
Regarding claim 16, Cheng shows (see, e.g., Cheng: figs. 3A-3N, 3N(1)-3N(5), and 4) removing the side-wall insulation 82 on a hole bottom of the hole 76.
Regarding claim 17, Cheng shows (see, e.g., Cheng: figs. 3A-3N, 3N(1)-3N(5), and 4) that the via 85/86 directly contacts the microelectromechanical sensor element 55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8, 10-12, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Partridge (US 2007/0172976).
Regarding claim 8, Cheng shows (see, e.g., Cheng: figs. 3A-3N, 3N(1)-3N(5), and 4) most aspects of a method for producing a sensor system, including a first semiconductor wafer 40/45/48/49/50/58 and a second semiconductor wafer 70.
However, Cheng fails (see, e.g., Cheng: figs. 3A-3N, 3N(1)-3N(5), and 4) to show the method step of producing a semiconductor device in the second semiconductor wafer 70 after connecting the first semiconductor wafer 40/45/48/49/50/58 and the second semiconductor wafer 70. Partridge, in a similar method to Cheng, shows (see, e.g., Partridge: fig. 6C) the method step of producing a semiconductor device 40 in the second semiconductor wafer 14b after connecting the first semiconductor wafer 14a and the second semiconductor wafer 14b (see, e.g., Partridge: par. [0108] - [0109]). Partridge also shows (see, e.g., Partridge: fig. 6C) that the method step of producing a semiconductor device 40 in the second semiconductor wafer 14b after connecting the first semiconductor wafer 14a and the second semiconductor wafer 14b is a suitable method step to fabricate integrated circuits (for example, CMOS transistors) that are connected to and/or micromachined mechanical structures 12 (see, e.g., Partridge: par. [0108]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the method step of Partridge of producing a semiconductor device in the second semiconductor wafer after connecting the first semiconductor wafer and the second semiconductor wafer in the method of Cheng in order to fabricate integrated circuits (for example, CMOS transistors) that are connected to and/or micromachined mechanical structures.
Regarding claim 10, Cheng shows (see, e.g., Cheng: figs. 3A-3N, 3N(1)-3N(5), and 4) most aspects of a method for producing a sensor system, including a first semiconductor wafer 40/45/48/49/50/58 and a second semiconductor wafer 70.
However, Cheng fails (see, e.g., Cheng: figs. 3A-3N, 3N(1)-3N(5), and 4) to show that at least one of the first semiconductor wafer 40/45/48/49/50/58 or the second semiconductor wafer 70 comprises a silicon-on-insulator (SOI) wafer. Cheng is also silent about the types of the first and second semiconductor wafers. Partridge, in a similar method to Cheng, shows (see, e.g., Partridge: fig. 6C) that the first semiconductor wafer 14a is a silicon-on-insulator (SOI) wafer.
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the semiconductor wafers of Cheng or the silicon-on-insulator (SOI) wafers of Partridge because these were recognized in the semiconductor art for their use as substrate for semiconductor device fabrication, as taught by Cheng and by Partridge, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Regarding claim 11, Cheng shows (see, e.g., Cheng: figs. 3A-3N, 3N(1)-3N(5), and 4) most aspects of a method for producing a sensor system, including a first semiconductor wafer 40/45/48/49/50/58 and a second semiconductor wafer 70.
However, Cheng fails (see, e.g., Cheng: figs. 3A-3N, 3N(1)-3N(5), and 4) to show a semiconductor device in the second semiconductor wafer 70. Partridge, in a similar method to Cheng, shows (see, e.g., Partridge: fig. 6C) a semiconductor device 40 in the second semiconductor wafer 14b (see, e.g., Partridge: par. [0108] - [0109]). Partridge also shows (see, e.g., Partridge: fig. 6C) that the method step of producing a semiconductor device 40 in the second semiconductor wafer 14b after connecting the first semiconductor wafer 14a and the second semiconductor wafer 14b is a suitable method step to fabricate integrated circuits (for example, CMOS transistors) that are connected to and/or micromachined mechanical structures 12 (see, e.g., Partridge: par. [0108]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the method step of Partridge of producing a semiconductor device in the second semiconductor wafer after connecting the first semiconductor wafer and the second semiconductor wafer in the method of Cheng in order to fabricate integrated circuits (for example, CMOS transistors) that are connected to and/or micromachined mechanical structures.
Cheng in view of Partridge shows (see, e.g., Partridge: fig. 6C) a method step of connecting, in an electrically conductive manner, the semiconductor device 40 to the microelectromechanical sensor element 12 (through the circuitry 16/18).
Regarding claim 12, Cheng in view of Partridge shows (see, e.g., Partridge: fig. 6C) a via 26b that connects the semiconductor device 40 to the microelectromechanical sensor element 12 in the electrically conductive manner.
Regarding claim 18, Cheng shows (see, e.g., Cheng: figs. 3A-3N, 3N(1)-3N(5), and 4) most aspects of a method for producing a sensor system, including a first semiconductor wafer 40/45/48/49/50/58 and a second semiconductor wafer 70.
However, Cheng fails (see, e.g., Cheng: figs. 3A-3N, 3N(1)-3N(5), and 4) to show the method step of producing a semiconductor device in the second semiconductor wafer 70 after connecting the first semiconductor wafer 40/45/48/49/50/58 and the second semiconductor wafer 70. Partridge, in a similar method to Cheng, shows (see, e.g., Partridge: fig. 6C) the method step of producing a semiconductor device 40 in the second semiconductor wafer 14b after connecting the first semiconductor wafer 14a and the second semiconductor wafer 14b (see, e.g., Partridge: par. [0108] - [0109]). Partridge also shows (see, e.g., Partridge: fig. 6C) that the method step of producing a semiconductor device 40 in the second semiconductor wafer 14b after connecting the first semiconductor wafer 14a and the second semiconductor wafer 14b is a suitable method step to fabricate integrated circuits (for example, CMOS transistors) that are connected to and/or micromachined mechanical structures 12 (see, e.g., Partridge: par. [0108]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the method step of Partridge of producing a semiconductor device in the second semiconductor wafer after connecting the first semiconductor wafer and the second semiconductor wafer in the method of Cheng in order to fabricate integrated circuits (for example, CMOS transistors) that are connected to and/or micromachined mechanical structures.
Regarding claim 19, Cheng shows (see, e.g., Cheng: figs. 3A-3N, 3N(1)-3N(5), and 4) most aspects of a method for producing a sensor system, including a first semiconductor wafer 40/45/48/49/50/58 and a second semiconductor wafer 70.
However, Cheng fails (see, e.g., Cheng: figs. 3A-3N, 3N(1)-3N(5), and 4) to show a semiconductor device in the second semiconductor wafer 70. Partridge, in a similar method to Cheng, shows (see, e.g., Partridge: fig. 6C) a semiconductor device 40 in the second semiconductor wafer 14b (see, e.g., Partridge: par. [0108] - [0109]). Partridge also shows (see, e.g., Partridge: fig. 6C) that the method step of producing a semiconductor device 40 in the second semiconductor wafer 14b after connecting the first semiconductor wafer 14a and the second semiconductor wafer 14b is a suitable method step to fabricate integrated circuits (for example, CMOS transistors) that are connected to and/or micromachined mechanical structures 12 (see, e.g., Partridge: par. [0108]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the method step of Partridge of producing a semiconductor device in the second semiconductor wafer after connecting the first semiconductor wafer and the second semiconductor wafer in the method of Cheng in order to fabricate integrated circuits (for example, CMOS transistors) that are connected to and/or micromachined mechanical structures.
Cheng in view of Partridge shows (see, e.g., Partridge: fig. 6C) a method step of connecting, in an electrically conductive manner, the semiconductor device 40 to the microelectromechanical sensor element 12 (through the circuitry 16/18).
Regarding claim 20, Cheng in view of Partridge shows (see, e.g., Partridge: fig. 6C) a via 26b that connects the semiconductor device 40 to the microelectromechanical sensor element 12 in the electrically conductive manner
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Kang (US 10941033).
Regarding claim 9, Cheng shows (see, e.g., Cheng: figs. 3A-3N, 3N(1)-3N(5), and 4) most aspects of a method for producing a sensor system, including a first semiconductor wafer 40/45/48/49/50/58 and a second semiconductor wafer 70.
However, Cheng fails (see, e.g., Cheng: figs. 3A-3N, 3N(1)-3N(5), and 4) to show an integrated sensor element in the second semiconductor wafer 70 after connecting the first semiconductor wafer 40/45/48/49/50/58 and the second semiconductor wafer 70. Kang, in a similar method to Cheng, shows (see, e.g., Kang: figs. 1-12) an integrated sensor element in the second semiconductor wafer 102/414 (see, e.g., Kang: col.5/II.6-12). Kang also shows (see, e.g., Kang: figs. 1-12) that the method step of an integrated sensor element in the second semiconductor wafer 102/414 after connecting the first semiconductor wafer 102/41 and the second semiconductor wafer 1124 is a suitable method step to fabricate a gyroscope or an accelerometer (see, e.g., Kang: col.6/II.21-30).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the method step of Kang of producing an integrated sensor element in the second semiconductor wafer after connecting the first semiconductor wafer and the second semiconductor wafer in the method of Cheng in order to fabricate a gyroscope or an accelerometer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIBERIU DAN ONUTA whose telephone number is (571) 270-0074 and between the hours of 9:00 AM to 5:00 PM (Eastern Standard Time) Monday through Friday or by e-mail via Tiberiu.Onuta@uspto.gov. If attempts to reach the examiner by telephone or email are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/TIBERIU DAN ONUTA/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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