DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-13 are pending.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Re claim 1 and 9 recite “ a first P+ electrically non-contacted region”, “ a first N+ electrically non-contacted region” and “ a second N+ non-contacted region”. It is unclear what is meant by “electrically non-contacted”, Specifically, the claim fails to specify what structure or component the region is not electrically contacted by, or whether the limitation requires the region to be electrically floating, free of ohmic contact or otherwise isolated. The metes and bounds of the claim may not be reasonably certain. Accordingly, one of ordinary skill in the art would not reasonably would not know the scope of the claim. Therefore, the claim is indefinite.
Claims 2-8 and 10-13 are rejected as being dependent on claims 1and 9.
For best understand and examination purpose, the claim will be best considered based on drawing, disclosure, and/or applicable prior arts.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al (US 20060258067 A1) in view of Ker et al (US 20050133869A1) and Jou et al (US20120193718A1).
Re claim 1 Jeon teaches, a silicon controlled rectifier (SCR) (fig, 11) comprising: a first P-type well region (70, fig 11) [0034] and a N-type well region (60, fig 11) [0034] in a substrate (50, fig 11) [0034]; and
wherein the first P-type well region comprises: a first P+ region (76’ fig 11) [0054] and a first N+ region (72, fig 11) [0054]; and
a first P+ electrically non-contacted region (74, fig 11) [0054]
wherein the N-type well region (60, fig 11) comprises: a first N+ electrically non-contacted region (64, fig 11) [0054];
a second N+ region (66’, fig 11) [0056];
a second P+ region (62, fig 11) [0056].
Jeon does not teach the N-type well region comprises a third P+ region, each is disposed on opposite sides of the second N+ region; and
Ker teaches the N-type well region (221, fig 2B) [0047] comprises a third P+ region (225, fig 2B) [0049] each is disposed on opposite sides of the second N+ region ( second P region 235 and third p region 225 each disposed on opposite sides of the second N+ region 227, fig 2B) [0047].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Ker into the structure of Jeon to include the N-type well region comprises a third P+ region, each is disposed on opposite sides of the second N+ region as claimed.
The ordinary artisan would have been motivated to modify Jeon based on the teaching of Ker in the above manner for the purpose of increasing the holding voltage [0060].
Jeon and Ker do not teach the N-type well region comprises a second N+ electrically non-contacted region.
Jou teaches the N-type well region (212, fig 2) [0021] comprises a second N+ electrically non-contacted region (222, fig 2) [0023].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Joe into the structure of Jeon and Ker to include as claimed.
The ordinary artisan would have been motivated to modify Jeon and Ker based on the teaching of Jou in the above manner for the purpose of increasing the holding voltage of the ESD protection structure [0035].
Re claim 2 Jeon in view of Ker and Jou teach the SCR of claim 1,
further comprising, an SCR anode (257, fig 2A) [Ker 0052] coupled to the second N+ region (227, fig 2A) [0047], the second P+ region (225, fig 2A) [Ker, 0047] and the third P+ region (235, fig 2A) [Ker, 0047].
Re claim 3 Jeon in view of Ker and Jou teach the SCR of claim 1, further comprising, an SCR cathode (cathode, fig 11) [Jeon, 0035] coupled to the first P+ region (76’, fig 11) [Jeon , 0035] and the first N+ region (72, fig 11) [Jeon, 0060].
Re claim 4 Jeon in view of Jeon, Ker Jou teach the SCR of claim 1,
Jeon and Jou do not teach the second P+ region provides an emitter for a PNP bipolar junction transistor (BJT); the N-type well region provides a base for the PNP BJT; and
the first P+ region provides a collector for the PNP BJT.
Ker fig 1A-1B teach the second P+ region (111, fig 1A-1B) [0007] provides an emitter (fig 1B) [0007] for a PNP bipolar junction transistor (BJT) (Q1, fig 1A-1B) [0007]; the N-type well region (103, fig 1A-1B) provides a base for the PNP BJT (Q1, fig 1A-1B) [0007]; and
the first P+ region (108, fig 1A-1B) [0007] provides a collector for the PNP BJT (Q1 fig 1A-1B) [0007].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Ker into the structure of Ker, Jeon and Jou to include the second P+ region provides an emitter for a PNP bipolar junction transistor (BJT); the N-type well region provides a base for the PNP BJT; and the first P+ region provides a collector for the PNP BJT as claimed.
The ordinary artisan would have been motivated to modify Jeon and Jou in the above manner for the purpose of reducing switch voltage and the turn-on time as to effectively serve as an electrostatic discharge devices and circuit [0022].
Re claim 5 Jeon view of Ker and Jou teach the SCR of claim 1, wherein:
Jeon and Jou do not teach the first N+ region provides an emitter for an NPN bipolar junction transistor (BJT);
the first P-type well region provides a base for the NPN BJT;
the second N+ region provides a collector for the NPN BJT.
Ker fig 1A-1B do teach the first N+ region (bottom N of Q2, fig 1B) [0007] provides an emitter for an NPN bipolar junction transistor(Q2, fig1B) (BJT) [0007];
the first P-type well region (middle P in Q2 fig 1B) [0007] provides a base for the NPN BJT [0007];
the second N+ region (top N of Q2, fig 1B) provides a collector for the NPN BJT [0007].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Ker to include the first N+ region provides an emitter for an NPN bipolar junction transistor (BJT);
the first P-type well region provides a base for the NPN BJT; the second N+ region provides a collector for the NPN BJT as claimed.
The ordinary artisan would have been motivated to modify Jeon and Jou in the above manner for the purpose of reducing switch voltage and the turn-on time as to effectively serve as a electrostatic discharge devices and circuit [0022].
Re claim 9 Jeon teaches a silicon controlled rectifier (SCR), comprising:
a first semiconductor region (P-well, fig 11) [0058] disposed in a substrate (50, fig 11) [0060];
a second semiconductor region (N-well, fig 11) [0060] disposed having an opposite conductivity type to the first semiconductor region (P-well);
a first P+ region (76’, fig 11) [0056] and a first N+ region (72, fig 11) [0060] disposed in the first semiconductor region (70, fig 11) [0060];
a first P+ electrically non-contacted region (74, fig 11) [0061] disposed in the first semiconductor region (P-well);
a first N+ electrically non-contacted region (64, fig 11)[0061] disposed in the second semiconductor region (N-well) [0060];
a second N+ region (66’, fig 11) [0061] disposed in the second semiconductor region (N-well) [0060];
a second P+ region (62, fig 11) [0061].
Jeon does not teach a third P+ region disposed in the second semiconductor region, where each is disposed on opposite sides of the second N+ region;
Ker teaches a third P+ region (225, fig 2B) [0049] disposed in the second semiconductor region, where each is disposed on opposite sides of the second N+ region;
(second P region 235 and third p region 225 each disposed on opposite sides of the second N+ region 227, fig 2B) [0047].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Ker into the structure of Jeon to include a third P+ region disposed in the second semiconductor region, where each is disposed on opposite sides of the second N+ region as claimed.
The ordinary artisan would have been motivated to modify Jeon based on the teaching of Ker in the above manner for the purpose of increasing the holding voltage [0060].
Jeon and Ker do not teach a second N+ electrically non-contacted region disposed in the second semiconductor region.
Jou teaches a second N+ electrically non-contacted region (222, fig 2) [0023]. disposed in the second semiconductor region (212, fig 2) [0021].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Jou into the structure of Jeon and Ker to include a second N+ electrically non-contacted region disposed in the second semiconductor region as claimed.
The ordinary artisan would have been motivated to modify Jeon and Ker based on the teaching of Jou in the above manner for the purpose of increasing the holding voltage of the ESD protection structure [0035].
Re claim 10 Jeon in view of Ker and Jou teach the SCR of claim 9, further comprising, an SCR anode (257, fig 2A) [Ker 0052] coupled to the second N+ region (227, fig 2A) [0047], the second P+ region (225, fig 2A) [Ker, 0047] and the third P+ region (235, fig 2A) [Ker, 0047].
Re claim 11 Jeon in view of Ker and Jou teach the SCR of claim 9, further comprising, an SCR cathode (cathode, fig 11) [Jeon, 0035] coupled to the first P+ region (76’, fig 11) [Jeon , 0035] and the first N+ region (72, fig 11) [Jeon, 0060].
Re claim 12 Jeon in view of Ker and Jou teach the SCR of claim 1,
Jeon and Jou do not teach the second P+ region provides an emitter for a PNP bipolar junction transistor (BJT);
the second semiconductor region provides a base for the PNP BJT; and
the first P+ region provides a collector for the PNP BJT.
Ker fig 1A-1B teach the second P+ region (111, fig 1A-1B) [0007] provides an emitter (fig 1B) [0007] for a PNP bipolar junction transistor (BJT) (Q1, fig 1A-1B) [0007]; the second semiconductor region (103, fig 1A-1B) provides a base for the PNP BJT (Q1, fig 1A-1B) [0007]; and the first P+ region (108, fig 1A-1B) [0007] provides a collector for the PNP BJT (Q1 fig 1A-1B) [0007].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Ker into the structure of Jeon, Ker and Jou to include the second P+ region provides an emitter for a PNP bipolar junction transistor (BJT); the second semiconductor region provides a base for the PNP BJT; and the first P+ region provides a collector for the PNP BJT as claimed.
The ordinary artisan would have been motivated to modify Jeon, and Jou in the above manner for the purpose of reducing switch voltage and the turn-on time as to effectively serve as a electrostatic discharge devices and circuit [0022].
Re claim 13 Jeon, Ker and Jou in view of The SCR of claim 9,
Jeon and Jou do not teach the first N+ region provides an emitter for an NPN bipolar junction transistor (BJT); the first semiconductor region provides a base for the NPN BJT; and the second N+ region provides a collector for the NPN BJT.
Ker fig 1A-1B do teach the first N+ region (bottom N of Q2, fig 1B) [0007] provides an emitter for an NPN bipolar junction transistor (Q2, fig1B) (BJT) [0007];
the first semiconductor region (middle P in Q2 fig 1B) [0007] provides a base for the NPN BJT [0007];
the second N+ region (top N of Q2, fig 1B) provides a collector for the NPN BJT [0007].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Ker to include the first N+ region provides an emitter for an NPN bipolar junction transistor (BJT);
the first semiconductor region provides a base for the NPN BJT;
the second N+ region provides a collector for the NPN BJT as claimed.
The ordinary artisan would have been motivated to modify Jeon and Jou in the above manner for the purpose of reducing switch voltage and the turn-on time as to effectively serve as a electrostatic discharge devices and circuit [0022].
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon modified by Ker and Jou as applied to claim 1 and further in view of Vladislav et al (US 7067852 B1).
Re claim 6 Jeon in view Ker and Jou teach the SCR of claim 1,
Jeon, Ker and Jou do not tech the first P+ electrically non-contacted region, the first N+ electrically non-contacted region, and the second N+ electrically non-contacted region present linear configurations from a plan perspective.
Vladislav teaches the first P+ electrically non-contacted region (108, fig 1) [col 3, lines 48-49], the first N+ electrically non-contacted region (104, fig 1) [col 3 lines 48-49], and the second N+ electrically non-contacted region (106, fig 1) [col 3 lines 48-49] present linear configurations from a plan perspective (see fig 1).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Vladislav into the structure of Jeon , Ker and Jou to include the first P+ electrically non-contacted region, the first N+ electrically non-contacted region, and the second N+ electrically non-contacted region present linear configurations from a plan perspective as claimed.
The ordinary artisan would have been motivated to modify Jeon, Ker and Jou based on the teaching of Vladislav in the above manner for the purpose of increasing ESD protection for a device. [col 6 line 4].
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon as modified by Ker, Jou as applied to claim 1 and further in view of Noh et al (US20190319024A1).
Re claim 7 Jeon in view of Ker and Jou teach the SCR of claim 1,
Jeon, Ker and Jou do not tech a second P-type well region disposed opposite to the first P-type well region with a respect to the N-type well region, wherein the second P-type well region comprises:
a third N+ region and a fourth P+ region; and
a second P+ electrically non-contacted region.
Noh teaches a second P-type well region (14, fig 1) [0012] disposed opposite to the first P-type well region (left p well, fig 1) with a respect to the N-type well region (13, fig 1) [0008], wherein the second P-type well region (14, fig 1) [0012] comprises: a third N+ region (19, fig 1) [0009] and a fourth P+ region (20, fig 1) [0010] ; and
a second P+ electrically non-contacted region (18, fig 1) [0009].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Noh into the structure of Jeon, Ker and Jou to include a second P-type well region disposed opposite to the first P-type well region with a respect to the N-type well region , wherein the second P-type well region comprises:
a third N+ region and a fourth P+ region as claimed.
The ordinary artisan would have been motivated to modify Jeon, Ker and Jou based on the teaching of Noh in the above manner for the purpose of the gain of the ESD protection SCR device may be improved [0028].
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon modified by Ker, Jou and Noh as applied to claim 7 and further in view of Salcedo et al (US20140339601A1).
Re claim 8 Jeon in view of Ker, Jou and Noh teaches the SCR of claim 7, further comprising:
Jeon, Ker, Jou and Noh teach a P-type deep well region in which the first P-type well region, the second P-type well region and the N-type well region are formed.
Salcedo teaches a P-type deep well region (93 DPW, fig 7B) [0040] in which the first P-type well region (92a) [0043], the second P-type well region (92b) [0043] and the N-type well region (94a) [0043] are formed.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Salcedo into the structure of Jeon, Ker, Jou and Noh to include a P-type deep well region in which the first P-type well region, the second P-type well region and the N-type well region are formed.
The ordinary artisan would have been motivated to modify Jeon, Ker, Jou and Noh based on the teaching of Salcedo in the above manner for the purpose of enhancing IC latch-up immunity [0037].
Conclusion
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/PRATIKSHA JAYANT LOHAKARE/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 7/20/26
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