Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 9, 11 and 16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen et al. [US PPGUB 20220328477] (hereinafter Chen).
Regarding claim 1, Chen teaches an integrated circuit device comprising:
a base substrate layer (101, Para 75);
a sheet separation wall (119, Fig. 25) extending on the base substrate layer in a first horizontal direction (Fig. 25);
a pair of nanosheet stacked structures (106a/b, Para 35, Fig. 25) including the sheet separation wall therebetween and apart from each other in a second horizontal direction (Fig. 25), the second horizontal direction different from the first horizontal direction (Fig. 25, 3D structure, i.e., x direction and y direction), the pair of nanosheet stacked structures each including a plurality of nanosheets (Fig. 25);
a plurality of cladding patterns (126, Fig. 25) between a first end of each of the plurality of nanosheets included in each of the pair of nanosheet stacked structures and the sheet separation wall (Fig. 25); and
a pair of gate electrodes (182, Para 50) extending on the pair of nanosheet stacked structures in the second horizontal direction (Fig. 25, 3D structure).
Regarding claim 2, Chen teaches an integrated circuit device wherein the plurality of cladding patterns are apart from each other in a vertical direction, on each of both sidewalls of the sheet separation wall (Fig. 25).
Regarding claim 3, Chen teaches an integrated circuit device further comprising a pair of gate insulating layers (180, Para 73) between the plurality of nanosheets included in the pair of nanosheet stacked structures and the pair of gate electrodes (Fig. 25),
wherein, among the plurality of cladding patterns, portions of the pair of gate electrodes and portions of the pair of gate insulating layers are between two cladding patterns apart from each other in the vertical direction (Fig. 25).
Regarding claim 4, Chen teaches an integrated circuit device further comprising a base insulating layer (178, Para 75, Fig. 25) between the pair of nanosheet stacked structures and the base substrate layer, wherein the sheet separation wall extends into the base insulating layer (Fig. 25).
Regarding claim 9, Chen teaches an integrated circuit device wherein a first end of the pair of gate electrodes facing the sheet separation wall is closer to the sheet separation wall than the first end of each of the plurality of nanosheets comprised in the pair of nanosheet stacked structures (Fig. 25).
Regarding claim 11, Chen teaches an integrated circuit device comprising:
a base insulating layer (178, Para 75) on a base substrate layer (101, Para 75, Fig. 25);
a sheet separation wall (130 exclude portion 126 at ends of layer 106, Fig. 25) extending on the base insulating layer in a first horizontal direction (Fig. 25, where layer 126 in fin region 112 extends on bottom surface of the base insulating layer);
a pair of nanosheet stacked structures (106a/b, Para 35, Fig. 25) including the sheet separation wall therebetween and apart from each other in a second horizontal direction (Fig. 25), the second horizontal direction different from the first horizontal direction (Fig. 25, 3D structure, i.e., x direction and y direction), the pair of nanosheet stacked structures each including a plurality of nanosheets (Fig. 25);
a plurality of cladding patterns (126, Fig. 25) between a first end of each of the plurality of nanosheets included in each of the pair of nanosheet stacked structures and the sheet separation wall (Fig. 25);
a pair of gate electrodes (182, Para 50) extending on the pair of nanosheet stacked structures in the second horizontal direction (Fig. 25, 3D structure);
a pair of gate insulating layers (180, Para 77, Fig. 25) between the plurality of nanosheets included in each of the pair of nanosheet stacked structures and the pair of gate electrodes (Fig. 25), the pair of gate insulating layers each having a thickness less than a thickness of each of the plurality of cladding patterns (Fig. 25); and
a pair of source/drain regions (160, Para 84) connected to a second end opposite to the first end of each of the plurality of nanosheets included in each of the pair of nanosheet stacked structures (Fig. 25).
Regarding claim 16, Chen teaches an integrated circuit device wherein, among the pair of nanosheet stacked structures, the plurality of nanosheets comprised in one nanosheet stacked structure and the plurality of nanosheets comprised in another nanosheet stacked structure have an identical horizontal width in the second horizontal direction (Fig. 25).
Allowable Subject Matter
Claims 18-20 are allowed.
Claims 5-8, 10, 12-15, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 18-20 are allowed because all prior arts of record and related prior arts not of record either singularly or in combination fail to anticipate or render obvious an integrated circuit device comprising:
the sheet separation wall having a horizontal cross-section having a pair of concave portions between the pair of nanosheet stacked structures,
the plurality of cladding patterns being in the pair of concave portions, and
the plurality of gate electrodes extending into the pair of concave portions (as claimed in claim 18), in combination with the rest of claim limitations as claimed and defined by the Applicant.
Conclusion
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/ISMAIL A MUSE/ Primary Examiner, Art Unit 2812
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