Prosecution Insights
Last updated: July 17, 2026
Application No. 18/755,062

PERFORMING DATA INTEGRITY CHECKS TO IDENTIFY DEFECTIVE WORDLINES

Non-Final OA §102
Filed
Jun 26, 2024
Priority
Dec 09, 2021 — continuation of 12/062,394
Examiner
CHO, SUNG IL
Art Unit
2825
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology Inc.
OA Round
2 (Non-Final)
91%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
541 granted / 592 resolved
+23.4% vs TC avg
Moderate +8% lift
Without
With
+8.3%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
31 currently pending
Career history
619
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
65.0%
+25.0% vs TC avg
§102
26.8%
-13.2% vs TC avg
§112
2.9%
-37.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 592 resolved cases

Office Action

§102
DETAILED ACTION The Amendment filed April 14, 2026 has been entered. Claims 1-20 are pending. Claims 1, 8 and 15 are independent. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. Independent claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over independent claims 1-20 of US Patent No. 12,062,394. Although the claims at issue are not identical, they are not patentably distinct from each other. Instant Application US Patent 12,062,394 Comment Claim 1. A system comprising: a memory device; and a processing device, operatively coupled to the memory device, to perform operations comprising: performing a write operation to program first data to a first set of memory cells addressable by a first wordline of a first plurality of wordlines of a block of the memory device; performing a read operation on a second wordline of the plurality of wordlines, wherein the second wordline is adjacent to the first wordline; determining a number of bits programmed in a first logical level in the second wordline; and responsive to determining that the number of bits programmed in the first logical level fails to satisfy a threshold criterion, performing a write operation on the second wordline to program second data. Claim 1. A system comprising: a memory device; and a processing device, operatively coupled to the memory device, to perform operations comprising: performing a write operation to program first data to a first set of memory cells addressable by a first wordline of a first plurality of wordlines of a first block of the memory device; performing a read operation on a second wordline of the plurality of wordlines, wherein the second wordline is a sequentially next and unwritten to wordline in the first block and is adjacent to the first wordline; determining a number of bits programmed in a first logical level in the second wordline; and responsive to determining that the number of bits programmed in the first logical level satisfies a threshold criterion, copying second data from the first block to a second block. Note footnote1 Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Koh et al. (US 2013/0229868). Regarding independent claims 1, 8 and 15, Koh et al. disclose a system comprising: a memory device (see FIG. 1); and a processing device, operatively coupled to the memory device, to perform operations comprising: performing a write operation (e.g., Abstract: the data from a previously written) to program first data to a first set of memory cells addressable by a first wordline of a first plurality of wordlines of a block of the memory device; performing a read operation (… adjacent is word line is read back) on a second wordline of the plurality of wordlines, wherein the second wordline is a sequentially next available word line in the block (Abstract: Before writing a word line, the data from a previously written adjacent is word line is read back…, i.e., a previously written adjacent can be interpreted as claimed “a sequentially next available”; and see claimed “in the block” in FIG. 1: 200) and is adjacent to the first wordline; determining (… If a short occurs, …) a number of bits programmed in a first logical level in the second wordline (… both word lines); and responsive to determining that the number of bits programmed in the first logical level fails to satisfy a threshold criterion (… If a short occurs, …), performing a write operation on the second wordline to program second data (… it (i.e., both word lines) can be written to a new location; also see para. 0162). Further, reprogramming a defected (claimed fail to satisfy a threshold criterion) word line due to interference with adjacent word lines is a well-known technology in a memory device. For support, see for example, Hsu et al. (US 2017/0322843), para. [0004]: For example, if the failure is due to a short between word lines … both the word line being programmed …; and Kleveland et al. (US 7,212,454), Abstract: The word lines are then reprogrammed and … a defect on that word line and a previously-programmed adjacent word line. If a defect is detected on that word line, that word line and the previously-programmed adjacent word line are repaired … Regarding claims 2, 9 and 16, Koh et al. disclose retiring the block from further use by the memory device (see e.g., para. 0096: … then remove it from … usable blocks). Regarding claims 3, 10 and 17, Koh et al. disclose performing another write operation to program the first data to a third block (para. 0162: the other block, which implies a third block in multi-block structure). Regarding claims 4, 11 and 18, Koh et al. disclose the first set of memory cells comprises each memory cell associated with the first wordline (see FIGS. 1 and 4, and accompanying disclosure). Regarding claims 5, 12 and 19, Koh et al. disclose the first set of memory cells comprises a predetermined subset of memory cells associated with the first wordline (e.g., para. 0069: … the subset of cells … the entire row …). Regarding claims 6, 13 and 20, Koh et al. disclose the processing device to perform further operations comprising: the threshold criterion comprises a threshold value of set bits (see e.g., para. 0062-0063). Regarding claims 7 and 14, Koh et al. disclose determining a count of memory cells programmed in a second logical level in the second wordline (see e.g., para. 0116: … using the total program loop count to judge this failure could result in false alarms). Documents Considered but not Relied Upon The documents below were considered. Hsu et al. (US 2017/0322843), Kleveland et al. (US 7,212,454), Karr et al. (US 2020/0082890), and Shappir et al. (US 2020/0005874) Response to Arguments Applicant’s amendment filed 04/14/2026, with respect to the rejection(s) of claims 1-20 under 35 USC 102 and 103, have been fully considered but are not persuasive. See the art rejections above for more details. With regard to the examiner interview summary, since the amended claims differ from the proposed claim amendments discussed during the interview, the examiner cannot find that the grounds for rejection based on the cited references have been overcome. Therefore, it is respectfully submitted that the examiner maintains the rejection. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached on 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SUNG IL CHO/ Primary Examiner, Art Unit 2825 1 Re independent claims 1, 8 and 15, claims of US Patent recites all the claimed limitations. The various dependent claims are anticipated by/obvious in view of the conflicting patent.
Read full office action

Prosecution Timeline

Jun 26, 2024
Application Filed
Dec 09, 2025
Non-Final Rejection (signed) — §102
Jan 15, 2026
Non-Final Rejection mailed — §102
Apr 07, 2026
Examiner Interview Summary
Apr 07, 2026
Applicant Interview (Telephonic)
Apr 14, 2026
Response Filed
Apr 29, 2026
Final Rejection mailed — §102
Jun 29, 2026
Response after Non-Final Action

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
91%
Grant Probability
99%
With Interview (+8.3%)
2y 0m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 592 resolved cases by this examiner. Grant probability derived from career allowance rate.

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