DETAILED ACTION
The Amendment filed March 03, 2026 has been entered. Claims 1-20 are pending. Claim 20 has been cancelled. Claims 1, 12 and 19 are independent.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 9-15 and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nguyen et al. (US 2020/0357462).
Regarding independent claims 1 and 19, Nguyen et al. disclose a read multiplexer circuit for a multiport register file (see FIG. 1A and 9A, para. 0028: … a register file 200 (e.g., register file 100) …), comprising:
an input stage (FIG. 9A: 200, i.e., write circuit) coupled to an array of storage nodes, each storage node coupled to drive an output of a respective bitcell (FIG. 1A: 102 and FIG. 9A: 202);
a read stage (FIG. 1A: 100, i.e., read circuit) comprising control logic dividing the array of storage nodes into one or more sets and first circuitry that provides a first read word line (e.g., rwl<0>) to a first storage node (cell 102) of a first set (cells 102 through 118) for reading data from the first storage node and a second read word line (e.g., rwl<7>) to a second storage node of the first set for reading data from the second storage node (cell 118); and
a first latch stage (latches for dout0 and dout1) comprising second circuitry that provides a third read word line (r0_addr or r1_addr, i.e., to enable double read of the memory cell in one clock cycle, latch circuits coupled to read bit line are enabled by control circuit, and decodes the read address r0_addr and r1_addr, see para. 0023) to the first storage and the second storage node of the first set to latch the read from one of the first (cell 102) storage node and the second (cell 118) storage nodes (see FIGS. 1A along with 9A, and accompanying disclosure, e.g., para. 0023).
Regarding claim 4, which depends from claim 1, Nguyen et al. disclose the first circuitry that provides a first read word line to the first storage node comprises a first transistor and a second transistor coupled in series between a source voltage and a reference voltage (see FIG. 1A: 108).
Regarding claims 9 and 18, which depends from claims 1 and 15, respectively, Nguyen et al. disclose a second latch stage comprising third circuitry that provides a fourth read word line to a first and second storage node of a different set to the first set to latch the read from one of the first and second storage nodes of that different set according to an address specifying a location of the storage node in the read multiplexer circuit (see FIG. 1A: 130 latch, latch for dout0 and latch for dout1, and para. 0023, r0_addr and r1_addr).
Regarding claim 10, which depends from claim 1, Nguyen et al. disclose multiple sets and wherein each set is coupled to an individual latch circuit (FIG. 1A: dout0 and dout1 paths).
Regarding claim 11, which depends from claim 1, Nguyen et al. disclose an inverter is coupled to an output of a bitcell to drive storage node output of the bitcell (see FIG. 1A).
Regarding independent claim 12, Nguyen et al. disclose a circuit for a multiport register file comprising:
an array of multiple storage nodes, each having a bitcell (see FIG. 1A: 102-118);
a two-stage read multiplexer circuit (108) configured to receive a storage node output of each storage node in the array of multiple storage nodes,
comprising:
a read stage (dout0 / dout1) for selecting data from the storage node output; a first latch stage for storing the selected data;
control logic (146, 148, 136, 142) for coordinating read operations from multiple ports (see FIG. 1A and accompanying disclosure).
Regarding claim 13, which depends from claim 12, Nguyen et al. disclose a driver (FIG. 1A: 132 and 134) is coupled to the output of each storage node and coupled to an input of the two-stage read multiplexer circuit.
Regarding claim 14, which depends from claim 13, Nguyen et al. disclose the driver is provided by an inverter coupled to the output of a bitcell to drive storage node output of the bitcell (FIG. 1A).
Regarding claim 15, which depends from claim 13, Nguyen et al. disclose control logic dividing the array of storage nodes into sets and first circuitry that provides a first read word line to a first storage node of a first set for reading data from the first storage node and a second read word line to a second storage node of the first set for reading data from the second storage node (FIG. 1A).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 5-8 and 16-17 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Nguyen et al. (US 2020/0357462).
Regarding claims 2-3 and 16, Nguyen et al. teach the limitations of claims 1 and 15, respectively.
Nguyen et al. do not explicitly disclose the first read word line is shared with a first storage node of a second set and the second read word line is shared with a second storage node of the second set for reading data from the first and second storage nodes of the second set respectively; and the first read word line is shared with multiple sets of storage nodes and the second read word line is shared with multiple sets of storage nodes.
However, read word line shared with several storage node (claimed a first storge node and a second storage node) in a multi-bank memory device is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Tanpure et al. (US 2012/0159076), e.g., FIGS. 8-10 and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize memory word lines driving multiple memory banks because these conventional technology are well established in the art of the memory devices.
Regarding claim 5, Nguyen et al. teach the limitations of claim 4.
Nguyen et al. do not explicitly disclose the first transistor is activated by the first read word line and the second transistor is activated by a logical inversion of the first read word line.
However, the word line activation with logical gates (such as inverter, NAND or NOR) is a well-known technology for a type of memory control logic for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize logical control gates in a memory operation because these conventional technology are well established in the art of the memory devices.
Regarding claim 6, Nguyen et al. teach the limitations of claim 5.
Nguyen et al. further teach a third transistor is coupled between the second transistor and the source voltage and a fourth transistor is coupled between the second transistor and the reference voltage (FIG. 1A, further read multiplexer comprising transistor is a well-known technology).
Regarding claims 7-8, Nguyen et al. teach the limitations of claim 6.
Nguyen et al. do not explicitly disclose the first latch stage comprising second circuitry such that the first read word line is coupled between the first transistor and the second transistor; and the first latch stage is coupled to control logic that coordinates read operations provided by a read port line coupled from the first read stage to the control logic to determine an output state of stored data.
However, data latch circuit relates read word line in a memory device is a well-known technology for a type of memory control logic for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize logical control gates controlling data latch in a memory operation because these conventional technology are well established in the art of the memory devices.
Regarding claim 17, Nguyen et al. teach the limitations of claim 16.
Nguyen et al. further teach the first latch stage is coupled to control logic that coordinates read operations provided by a read port line coupled from the read stage to the control logic to determine an output state of stored data (see FIGS. 1A along with 9A, and accompanying disclosure, e.g., para. 0023).
Response to Argument
Applicant’s arguments filed 03/03/2026, with respect to the rejection(s) of claims under 35 USC 102 and 103, have been fully considered but are not persuasive.
For a compact prosecution, the examiner points out and answers the main features of the applicant’s argument.
Applicant argues that Nguyen’s write circuit includes “a first input coupled to a local write bitline” for writing data to storage nodes, not for receiving outputs from storage nodes as part of a read path. The claimed input stage receives data driven from storage nodes for reading operations, whereas Nguyen’s write circuit 200 provides data to storage nodes for writing operations. These are functionally distinct components.
In response to the applicant’s argument, as the applicant acknowledged, Nguyen’s figure 1A illustrates a register file read circuit and figure 9A illustrates a register file write circuit with some example of the disclosure. A register file is neither a read-only circuit nor write-only circuit. A register file comprises storing a data value into memory cell (i.e., write operation) and reading a data value from memory cell (i.e., read operation). Nguyen’s figure 1A illustrates an exemplary a register file read circuit in accordance with some examples of the disclosure, and figure 9 illustrates an exemplary a register file write circuit in accordance with some example of the disclosure. One of the reasons for explaining reading and writing separately is that read and write operations are performed individually. Further, the examiner examines the claimed limitations. Nguyen’s read and write register file read on all the elements of the claimed limitations.
Applicant argues that items r0_addr or r1_addr are not signals on a conductor that are dedicated to a specific memory cell are to directly access the specific memory cell for a memory operation. As such, it is submitted that any such “third wordline” is absent.
In response to the applicant’s argument, the applicant never claimed “third wordline”. The applicant claimed “a third read wordline” which is related to a first latch stage. Nguyen’s r0_addr and r1_addr decode and enable read of the memory cell and latch the read data into latch circuit. Namely, the memory cell selected by address (r0_addr or r1_adddr) stores data into latch circuit. The claimed “a third word line” is the word line decoded by address (r0_addr or r1_adddr).
Applicant argues that Nguyen disclose a single layer multiplexer rathe than the claimed two-step read stage architecture.
In reasons to the applicant’s arguments, as noted by the examiner, the examiner examines the claimed limitations. The applicant never claimed “two-step read stage architecture”. Nguyen’s read and write register file read on all the elements of the claimed limitations.
Therefore, it is respectfully submitted that the examiner maintains the rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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/SUNG IL CHO/ Primary Examiner, Art Unit 2825
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