DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/26/2024 and 3/5/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 10-13, 15 and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by John et al. US 2021/0091259.
Re claim 10, John teaches a method for inspecting a plurality of light emitting diodes (150, fig7, [50]) disposed on a temporary substrate (200, fig7, [24]), wherein each of the plurality of light emitting diodes comprises a first electrode (122, fig1, [28]), a first semiconductor layer (128, fig1, [33]), an emission layer (126, fig1, [33]), a second semiconductor layer (124, fig1, [33]), and a second electrode (116 and 112, fig1, [34]),
wherein the method comprises:
providing, on a wafer (102, fig3D, [33]), a plurality of emission structures (150, fig1, [50]), wherein each of the plurality of emission structures includes the first semiconductor layer (128, fig1, [33]), the emission layer (126, fig1, [33]) overlapping the first semiconductor layer, the second semiconductor layer (124, fig1, [33]) overlapping the emission layer, and the second electrode (116, 112, 118, fig1, [34]) overlapping the second semiconductor layer;
providing a common pad (160, 170, 180, fig1 and 3J, [30]) connected to the second electrode (116, 112, 118 fig1 and 3J, [34]) on an upper surface of the wafer (102, fig3J, [33]);
attaching the temporary substrate (200, fig3J, [24]) to the common pad (160-170-180 or 118, fig1 and 3J, [30]);
removing the wafer (fig3K);
providing the first electrodes (122, fig3L, [28]) on first surfaces of the plurality of emission structures from which the wafer is removed; and
inspecting luminous properties of the plurality of emission structures by electrically connecting probes (700A and 700B, fig7, [50]) to the common pad (160-170-180, fig1 and 3J, [30]) and the plurality of light emitting diodes (150, fig7, [50]), and wherein inspecting the luminous properties of the plurality of emission structures includes: connecting at least one of the first electrodes (122, fig3L, [28]) to a first probe (700A, fig7, [50]) and connecting the common pad (160-170-180, fig1 and 3J, [30]) to a second probe (700B, fig7, [50]).
Re claim 11, John teaches the method according to claim 10, wherein in providing the common pad (160-170-180, fig1 and 3J, [30]), the common pad is connected to all of the second electrodes (116,112, 118, fig1 and 3J, [34]) of the plurality of emission structures for electrical connection.
Re claim 12, John teaches the method according to claim 11, further comprising: providing an insulating layer (130, fig3D, [36]) enclosing side surfaces of the plurality of emission structures (150, fig1 and 3D, [50]) before providing the common pad (160-170-180, fig1 and 3H, [30]), wherein the common pad (160-170-180, fig1 and 3H, [30]) covers a surface of the insulating layer (130, fig3D, [36]) except for the second electrodes (116, 112, 118, fig1, [34]) of the plurality of emission structures.
Re claim 13, John teaches the method according to claim 12, wherein in providing the insulating layer (130, fig3D, [36]), the insulating layer is provided except for parts of the second electrodes of the plurality of emission structures (130 formed around 150 except part under 116, fig1) and has a height corresponding to a thickness of the plurality of emission structures (130 formed with a height covering 150, fig3D).
Re claim 15, John teaches the method according to claim 13, further comprising: separating the temporary substrate from the plurality of emission structures (9030, fig9, [52]) on which the first electrodes (122, fig4, [28]) are disposed by removing the common pad (160-170-180, fig1 and 3J, [30]) after inspecting the luminous properties of the plurality of emission structures (fig9).
Re claim 22, John teaches a method for manufacturing an interposer comprising a plurality of light emitting diodes (150, fig1, [50]),
wherein each of the plurality of light emitting diodes (150, fig1, [50]) comprises a first electrode (122, fig1, [28]), an emission layer (126, fig1, [33]), a second electrode (116 and 112, fig1, [34]) and a passivation layer (130, fig3D, [36]), and wherein the method comprises:
providing, on a wafer (102, fig3D, [33]), a plurality of emission structures (150, fig1 and 3D, [50]), wherein each of the plurality of emission structures includes the second electrode (116, 112, 118 , fig1, [34]) and the emission layer (126, fig1, [33]) overlapping the second electrode (116, 112, 118, fig1, [34]);
providing, on the wafer (102, fig3D, [33]), the passivation layer (130, fig3D, [36]) enclosing the emission layer (126, fig1 and 3D, [33]);
providing a common pad (160-170-180, fig1 and 3I, [30]), wherein the common pad is connected to the second electrode (116, 112, 118, fig1, [34]) of each of the plurality of emission structures through an opening in the passivation layer (130, fig3D, [36]) of each respective one of the plurality of emission structures;
attaching a substrate (200, fig3J, [24]) to the common pad (160-170-180 or 118, fig1 and 3I, [30]);
removing the wafer (fig3K); and
providing the first electrodes (122, fig3L, [28]) on surfaces of the plurality of emission structures from which the wafer is removed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 8-9, 16-17 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over John et al. US 2021/0091259 and Liu et al. US 2024/0405175.
Re claim 1, John teaches an interposer, comprising:
a temporary substrate (200, fig1, [24]);
a common pad (160-170-180 or 118, fig1, [30]) on the temporary substrate (200, fig1, [24]); and
a plurality of light emitting diodes (LEDs) (150, fig1, [28]) on the common pad (160-170-180 or 118, fig1, [30]),
wherein:
each of the plurality of light emitting diodes (150, fig1, [28]) includes a first electrode (122, fig1, [28]), a first semiconductor layer (128, fig1, [33]), an emission layer (126, fig1, [33]), a second semiconductor layer (124, fig1, [33]), a second electrode (116 and 112, fig1, [34]), and
the second electrode (116 and 112, fig1, [34]), the second semiconductor layer (124, fig1, [33]), the emission layer (126, fig1, [33]), the first semiconductor layer (128, fig1, [33]) and the first electrode (122, fig1, [28]) have a structure formed from sequential lamination (fig1, A "product by process" claim is directed to the final product per se, no matter how it is actually made. In re Hirao and Sato et al., 190 USPQ 15, 17 (CCPA 1976); see also In re Brown and Saffer, 173 USPQ 685 (CCPA 1972); In re Luck and Gainer, 177 USPQ 523 (CCPA 1973); In re Fessmann, 180 USPQ 324 (CCPA 1974); and In re Marosi et al., 218 USPQ 289 (CAFC 1983). It is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product, produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not. Id. Note that Applicant has the burden of proof in such cases. Id. Furthermore, "[e]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985));
the common pad (160-170-180 or 118, fig1, [30]) is connected to the second electrode (116 and 112, fig1, [34]) for electrical connection at a lower side of the plurality of light emitting diodes (part of 150 facing 175, fig1, [28]);
John does not explicitly show a passivation layer; the passivation layer encloses the second semiconductor layer, the emission layer and the first semiconductor layer; and the first electrode in each of the plurality of light emitting diodes extends to an upper portion of the passivation layer.
Liu teaches a passivation layer (220 or 200, fig2H, [22]); the passivation layer (220 or 200, fig2H, [22]) encloses the second semiconductor layer (130, fig2H, [19]), the emission layer (120, fig2H, [19]) and the first semiconductor layer (110, fig2H, [19]); and the first electrode (104, fig2H, [19]) in each of the plurality of light emitting diodes (100, fig2H, [21]) extends to an upper portion of the passivation layer (200, fig2H, [22]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of John and Liu to add a transparent packaging structure 200 around LED 100 as in fig2B of Liu. The motivation to do so is to protect the LED and improve light coupling efficiency (Liu, [21]).
Re claim 2, John modified above teaches the interposer according to claim 1, further comprising: an insulating layer (John, 400, fig1, [26, 46]) enclosing the plurality of light emitting diodes (John, 150, fig4) in a region between the plurality of light emitting diodes (John, 400 between 150, fig4 and 7) and exposing parts of upper portions of the plurality of light emitting diodes (John, top part of 150 with 122, fig4), wherein the insulating layer (John, 400, fig4, [26, 46]) is disposed between the temporary substrate (John, 200, fig4, [24]) and the common pad (John, 118 in layer 110, fig1, [28]).
Re claim 3, John modified above teaches the interposer according to claim 2, wherein the insulating layer includes a plurality of grooves (John, 450 in 400, fig4, [26, 46]), and the plurality of light emitting diodes is disposed in the plurality of grooves (John, 150 located in 450, fig4, [46]).
Re claim 4, John modified above teaches the interposer according to claim 3, wherein the common pad (John, 118, fig1, [28]) is disposed along a shape of the plurality of grooves (John, 450, fig4, [26, 46]).
Re claim 5, John does not explicitly show the interposer according to claim 4, further comprising: an additional insulating layer on the common pad, wherein the additional insulating layer is disposed along a shape of the common pad disposed in the plurality of grooves.
Liu teaches an additional insulating layer (300, fig2H, [24]) on the common pad (104, fig2H, [23]), wherein the additional insulating layer (300, fig2H, [24]) is disposed along a shape of the common pad (104, fig2H, [23]) disposed in the plurality of grooves (space holding 100, fig2H).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of John and Liu to add a transparent packaging structure 200 and reflective structures 300 around LED 100 as in fig2H of Liu. The motivation to do so is to protect the LED and improve light coupling efficiency and reduce crosstalk between different LEDs (Liu, [21, 26]).
Re claim 8, John modified above teaches the interposer according to claim 2, wherein the insulating layer comprises an organic material (John, 400, fig1, [26, 46]).
Re claim 9, John modified above teaches the interposer according to claim 1, wherein the common pad comprises aluminum (170 and 118 as aluminum, fig1, [29, 30]).
Re claim 16, John does not explicitly show the method according to claim 11, further comprising: providing an additional insulating layer enclosing side surfaces of the plurality of emission structures before providing the common pad, wherein the additional insulating layer is disposed along a shape of the plurality of emission structures protruding on the wafer.
Liu teaches providing an additional insulating layer (200, fig2B, [22]) enclosing side surfaces of the plurality of emission structures (100, fig2B, [21]) before providing the common pad (522, fig2E, [33]), wherein the additional insulating layer (200, fig2B, [22]) is disposed along a shape of the plurality of emission structures protruding on the wafer (TS1, fig2B, [27]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of John and Liu to add a transparent packaging structure 200 and reflective structures around LED 100 as in fig2H of Liu. The motivation to do so is to protect the LED and improve light coupling efficiency (Liu, [21, 26]).
Re claim 17, John modified above teaches the method according to claim 16, wherein the common pad (John, 160-170-180, fig1 and 3J, [30]) is disposed to cover a surface of the additional insulating layer (200 as in fig2B added around John 150) except for the second electrodes (John, 116 ,112, 118, fig1, [34]) of the plurality of emission structures.
Re claim 21, John teaches an interposer, comprising:
a substrate (200, fig1, [24]);
a common pad (160-170-180, fig1 and 3J, [30]) on the substrate; and
a plurality of light emitting diodes (LEDs) (150, fig1, [50]) on the common pad,
wherein: each of the plurality of light emitting diodes (150, fig1, [50]) includes a first electrode (122, fig1, [28]), an emission layer (126, fig1, [33]), a second electrode (116 and 112, fig1, [34]),
the emission layer (126, fig1, [33]) is disposed between the first electrode (122, fig1, [28]) and the second electrode (116, 112, 118, fig1, [34]);
the common pad (160-170-180, fig1 and 3J, [30]) is connected to the second electrode (116, 112, 118, fig1, [34]) for electrical connection;
John does not explicitly show a passivation layer; the passivation layer encloses the emission layer; the common pad is connected to the second electrode for electrical connection through an opening at a lower portion of the passivation layer; the first electrode extends to an upper portion of the passivation layer; and the passivation layer of each of the plurality of light emitting diodes is separate and isolated from one or more other passivation layers of the plurality of light emitting diodes.
Liu teaches a passivation layer (200, fig2B, [22]); the passivation layer (200, fig2B, [22]) encloses the emission layer (120, fig2B, [19]); the common pad (522, fig2E, [33]) is connected to the second electrode (104, fig2E, [19]) for electrical connection through an opening at a lower portion of the passivation layer (opening at center of 200 holding 104, fig2E); the first electrode (102, fig2E, [19]) extends to an upper portion of the passivation layer (210, fig2E, [21]); and the passivation layer (200, fig2B, [22]) of each of the plurality of light emitting diodes (100, fig2E, [21]) is separate and isolated from one or more other passivation layers of the plurality of light emitting diodes (fig2E).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of John and Liu to add a transparent packaging structure 200 around LED 100 as in fig2B of Liu. The motivation to do so is to protect the LED and improve light coupling efficiency (Liu, [21]).
Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over John et al. US 2021/0091259, Liu et al. US 2024/0405175 and Wu et al. US 2023/0343902.
Re claim 7, John does not explicitly show the interposer according to claim 5, wherein the additional insulating layer comprises an inorganic material.
Wu teaches reflective material comprises metal oxide with high reflectivity ([50]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of John, Liu and Wu to use a reflective material comprises metal oxide for the reflective layer 300 formed around LED 100 as in fig2H of Liu. The motivation to do so is to improve reflectivity (Wu, [50]).
Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over John et al. US 2021/0091259 and Wang US 2021/0233795.
Re claim 20, John does not explicitly show the method according to claim 10, wherein inspecting the luminous properties of the plurality of emission structures further includes: selectively removing, from the temporary substrate, one or more emission structures determined as being defective.
Wang teaches remove defective LED followed by refill good LED chips ([62]) and bond to the final circuit board ([62]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of John and Wang to replace defective LEDs and bond all LEDs in one process. The motivation to do so is to improve transfer efficiency and ensure high transfer yield (Wang, [40]).
Allowable Subject Matter
Claims 6, 14 and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim.
Specifically, the limitations are material to the inventive concept of the application in hand to reduce process cost and improve yield of light emitting diodes.
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812
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