DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 8 and 15 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. (US Pat pub 2024/0289018).
Regarding claims 1, 8 and 15, Kim et al. disclose a system (for example figs. 1 – 13 and all related texts), comprising:
a host system (see para 0003, “a host”); and
a memory system (for example fig. 1) comprising a memory controller (110), a dynamic random-access memory (DRAM) device (120, see also para 0029), and
a command address (CA) bus that comprises multiple CA links between the memory controller and the DRAM device (shown in fig. 1 as CA bus 132);
wherein the host system is configured to program the memory controller with a link stress pattern of bits (referred to as “predetermined bit pattern”, abstract); and
wherein the memory controller is configured to, assert the link stress pattern of bits on the CA links while the DRAM device is in a pre-operating state in which the DRAM device does not recognize memory access commands and in which a CA bus parity circuit of the DRAM device is enabled (the “command” in the abstract that comprises the predetermined bit pattern is not an “access command”, it includes only the Predetermined bit pattern for the stress test of the CA bus link),
wherein the link stress pattern of bits extends over multiple clock cycles of the DRAM device (see para 0007, 0032, and 0037, etc…), and
monitor an error output of the DRAM device for parity errors (referred to as step S440 of fig. 4, or step S740 of fig. 7), while asserting the link stress pattern of bits on the CA links (step S430 of fig. 4 or step S730 of fig. 7).
Allowable Subject Matter
Claims 2 – 7, 9 – 14 and 16 – 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior arts of record fail to teach or reasonably suggest the system and method as set forth above, further comprising, in combination, the features and limitations additionally claimed in claims 2 – 7, 9 – 14, and 16 – 20.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
See additional cited references for related disclosures to the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LY D PHAM whose telephone number is (571)272-1793. The examiner can normally be reached M-F: 8am-5pm.
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LY D. PHAM
Examiner
Art Unit 2827
/LY D PHAM/Primary Examiner, Art Unit 2827 January 18, 2026