Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDSs) submitted on 06/26/2024 and 7/30/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner.
Election/Restrictions
Applicant’s election of claims 1-9 and 19-20 without traverse in the reply filed on 8/29/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 1,
Claim 1 recites the limitation, “comprising: a passive device”. The Examiner finds that this limitation is indefinite because Applicant’s, “passive device” appears to be an active device. This is because Applicant’s passive device comprises 2 terminals which are source/drain contacts and a third terminal which is a gate electrode. This is a definition for a transistor, which is an active device. In Applicant’s paragraph [0065], Applicant writes, “By providing electrical isolation between the active regions and the backside contact, individual passive device or elements on the passive section 200B” which the Examiner interprets as stating that passive devices are defined as devices in the passive section. It is therefore not clear to the Examiner how the devices called, “passive devices” by the Applicant are in fact passive devices as understood by one of ordinary skill in the art. That is, a device which does not modify a signal. The Examiner interprets the term, “passive device” as meaning a device comprising the elements claimed by the Applicant.
Claim 1 is further rejected for reciting the limitation, “a dielectric break”. The Examiner finds this limitation to be indefinite because the Applicant describes a dielectric break as being made of silicon. Silicon is a semiconductor and not a dielectric. The dielectric break is also described as isolating a first N-Well region from a second N-Well region. A dielectric has the property of not being electrically conductive and therefore may be used to isolate conducting or semiconducting elements. It is therefore not clear to the Examiner whether or not a dielectric break is intended to be a dielectric. The Examiner interprets a dielectric break to be a semiconductor as the Applicant claims the dielectric break to be made of silicon.
Regarding Claims 2-9, these claims depend upon claim 1 and are therefore rejected for the same reasons.
Regarding Claims 19-20, these claims are rejected for the same reasons as claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Do et al US 20230335492 A1. Do et al will be referenced to as Do henceforth.
Regarding Claim 1,
Do teaches:
“A semiconductor device (FIGs. 1-3, 5, 28, comprising: a passive device comprising:
a set of P-type doped regions (source/drain region NP, [0050], FIG. 10: NP is p-type.);
a set of N-type doped regions (first well tap NN, [0054]: NN is N-type.);
a first N-well region (first well NW (the portion in FIG. 2), [0054]) and a second N-well region (first well NW (the portion in FIG. 3), [0054]) below the set of P-type doped regions and the set of N-type doped regions (FIGs. 2-3: NW is beneath both NN and NP.);
a first shallow trench isolation (STI) between the first N-well region and the second N-well region (device isolation layer 105, [0028], [0035]: The device isolation layer is along line IV-IV’. Line IV-IV’ is between lines I-I’ and II-II’ as seen in FIG. 1. Therefore 105 is between NW and NP.);
a substrate below the first STI (substrate 100, [0028]); and
a dielectric break within the substrate (dielectric break, annotated FIG. 28 #1: The dielectric break is made of silicon. The substrate is also made of silicon. Since Applicant’s dielectric break is within the substrate and is in the substrate and is made of the same material, then the dielectric break may be considered a portion of the substrate.), wherein the dielectric break is vertically extended from the first STI to a bottom interlayer dielectric (BILD) below the substrate (lower insulating layer 310, [0131], annotated FIG. 28 #1: The lower insulating layer is an interlayer because one of ordinary skill in the art would place a tap cell into a larger device.).”
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Annotated FIG. 28 #1
Regarding Claim 2,
Do teaches:
“The semiconductor device of claim 1, wherein the dielectric break and the first STI isolate the first N-well region and the second N-well region ([0028], [0035]: The device isolation layer and the dielectric break are both along line IV-IV’. Line IV-IV’ is between lines I-I’ and II-II’ as seen in FIG. 1. Therefore 105 and the dielectric break are between NW and NP and are not conductors, 105 and the dielectric break isolate NW from NP.).”
Regarding Claim 3,
Do teaches:
“The semiconductor device of claim 1, wherein the dielectric break is made of silicon (dielectric break, annotated FIG. 28 #1: The dielectric break is made of silicon. The substrate is also made of silicon. Since Applicant’s dielectric break is within the substrate and is in the substrate and is made of the same material, then the dielectric break may be considered a portion of the substrate.).”
Regarding Claim 4,
Do teaches:
“The semiconductor device of claim 1, wherein the passive device is electrically connected to a back end of line (BEOL) (connection wiring M1_I, [0024], FIG. 28) through a first via (contact via VA13, [0024], FIG. 26).”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-8 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Do as applied to claims 1-4 above, and further in view of a second embodiment of Do, Do #2 et al. Do #2 et al will be referenced to as Do #2 henceforth. Do #2 comprises the top view layout shown in FIG. 5 of US 20230335492 A1.
Regarding Claim 5,
Do teaches:
“The semiconductor device of claim 1, further comprising: source/drain regions (source/drain region NP, [0050], FIG. 10; second source/drain region PN, [0050], FIG. 11: PN is a n-type.);
gate regions (gate electrodes GE, [0048], FIG. 25); and
a backside contact (first power rail PR1, [0058], FIG. 28).”
Do doesn’t substantially teach:
“an active device,”
However, Do #2 teaches:
“an active device (Do #2: annotated FIG. 5 #1),”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Do is modifiable in view of Do #2 by using the top view design of the TC depicted in FIG. 5 instead of the top view of the TC design in FIG. 1.
This is because Do teaches a top view of a TC with a gate electrode electrically coupled to a BEOL interconnect. Do doesn’t substantively a top view of a TC wherein an active region, which doesn’t overlap with a passive region, is connected to a BEOL. Do #2 teaches a top view of a TC with a gate electrode electrically coupled to a BEOL interconnect. Do #2 further teaches a top view of a TC wherein an active region doesn’t overlap with a passive region. Because both Do and Do #2 have a top view of a TC with a gate electrode electrically coupled to a BEOL, one of ordinary skill in the art would have deemed it obvious to substitute a top view of a TC with a gate electrode electrically coupled to a BEOL interconnect of Do for a top view of a TC with a gate electrode electrically coupled to a BEOL interconnect wherein the active region does not overlap the passive region of Do #2 for the predictable result of a top view wherein a gate electrode is electrically connected to a BEOL interconnect.
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Annotated FIG. 5 #1
Regarding Claim 6,
Do/Do #2 teaches:
“The semiconductor device of claim 5, wherein the active device is a field-effect transistor (FET) (Do: [0125], FIG. 25: One of ordinary skill in the art would understand that a gate all around nanosheet transistor is a kind of FET. This is because the active device of Do has 3 terminals, that is a source contact, a drain contact, and a gate electrode. and a channel insulated with a gate dielectric. Field effect transistors are transistors with an insulated channel.).”
Regarding Claim 7,
Do/Do #2 teaches:
“The semiconductor device of claim 5, wherein the active device further comprises alternative layers extended horizontally between two adjacent source/drain regions (Do: sheet patterns NS, [0127], FIG. 25).”
Regarding Claim 8,
Do/Do #2 teaches:
“The semiconductor device of claim 5, wherein the active device is electrically connected to a back end of line (BEOL) through a second via (Do: contact via VA14, [0024], FIG. 25).”
Regarding Claim 19,
Do/Do #2 teaches:
“A semiconductor device, comprising:
a passive device comprising:
a shallow trench isolation (STI ( Do: device isolation layer 105, [0028], [0035]: The device isolation layer is along line IV-IV’. Line IV-IV’ is between lines I-I’ and II-II’ as seen in FIG. 1. Therefore 105 is between NW and NP.);
a substrate below the STI (Do: substrate 100, [0028]); and
a dielectric break within the substrate (Do: dielectric break, annotated FIG. 28 #1: The dielectric break is made of silicon. The substrate is also made of silicon. Since Applicant’s dielectric break is within the substrate and is in the substrate and is made of the same material, then the dielectric break may be considered a portion of the substrate.), wherein the dielectric break and the STI isolate a first N-well region (Do: first well NW (the portion in FIG. 2), [0054]) and a second N-well region (Do: first well NW (the portion in FIG. 3), [0054]) in the passive device (Do: [0028], [0035]: The device isolation layer and the dielectric break are both along line IV-IV’. Line IV-IV’ is between lines I-I’ and II-II’ as seen in FIG. 1. Therefore 105 and the dielectric break are between NW and NP and are not conductors, 105 and the dielectric break isolate NW from NP.); and
an active device (Do/Do #2: Do: source/drain region NP, [0050], FIG. 10; second source/drain region PN, [0050], FIG. 11: PN is a n-type; gate electrodes GE, [0048], FIG. 25; first power rail PR1, [0058], FIG. 28; Do #2: annotated FIG. 5 #1).”
Regarding Claim 20,
Do/Do #2 teaches:
“The semiconductor device of claim 19, wherein the passive device further comprises:
a set of P-type doped regions (Do: source/drain region NP, [0050], FIG. 10: NP is p-type.); and
a set of N-type doped regions (Do: first well tap NN, [0054]: NN is N-type.), wherein:
the first N-well region and the second N-well region are located below the set of P-type doped regions and the set of N-type doped regions (Do: FIGs. 2-3: NW is beneath both NN and NP.).”
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Do/Do #2 as applied to claims 5-8 and 19-20 above, and further in view of Guler et al US 20250204029 A1. Guler et al will be referenced to as Guler henceforth.
Regarding Claim 9,
Do/Do #2 teaches:
“The semiconductor device of claim 7,”
Do/Do #2 doesn’t substantially teach:
“wherein the alternative layers include silicon (Guler: [0080]: Nanoribbons may be made of silicon.)”
However, Guler teaches:
“wherein the alternative layers include silicon (Guler: [0080]: Nanoribbons may be made of silicon.)”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Do/Do #2 is modifiable in view of Guler by making the nanosheet of Do/Do #2 out of silicon.
This is because one of ordinary skill in the art would need to know what the nanosheets of Do/Do #2 are made of in order to make the device of Do/Do #2. Therefore, one of ordinary skill in the art would be motivated to find a reference teaching a material which may be used to make nanosheets. Guler teaches that nanosheets may be made of silicon.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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