Prosecution Insights
Last updated: July 17, 2026
Application No. 18/755,725

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Non-Final OA §102§103§112
Filed
Jun 27, 2024
Priority
Mar 22, 2024 — TW 113110874
Examiner
SEVEN, EVREN
Art Unit
Tech Center
Assignee
Hon Young Semiconductor Corporation
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
82%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
542 granted / 733 resolved
+13.9% vs TC avg
Moderate +9% lift
Without
With
+8.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
36 currently pending
Career history
768
Total Applications
across all art units

Statute-Specific Performance

§101
2.2%
-37.8% vs TC avg
§103
82.2%
+42.2% vs TC avg
§102
6.7%
-33.3% vs TC avg
§112
7.0%
-33.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 733 resolved cases

Office Action

§102 §103 §112
Detailed Action The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 1 and 7 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. The phrase “as being far away from the substrate” does not make sense in context and is assumed to be a translation issue. The limitation will be interpreted as a retrograde dopant profile in the JFET region. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1- are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pat. No. 10388737 to Bolotnikov et al (Bolotnikov). Regarding Claims 1 and 7, Bolotnikov teaches a semiconductor device and associated method, comprising: a substrate 12; a drift layer 16 over the substrate; a junction field-effect transistor region 29 over the drift layer, wherein a doping concentration of the junction field-effect transistor region decreases away from the substrate 8:32-56; a well region 18 over the drift layer and at a side of the junction field-effect transistor region; a source region 20 in the well region; and a gate structure 26 over the junction field-effect transistor region. Regarding Claim 2, Bolotnikov teaches the semiconductor device of claim 1, wherein a width of the junction field-effect transistor region decreases away from the substrate (see Fig. 6). Regarding Claim 3, Bolotnikov teaches the semiconductor device of claim 1, wherein the junction field-effect transistor region has a conductivity type same as a conductivity type of the source region 7:16-18, and the doping concentration of the junction field-effect transistor region 8E15 cm-3 is lower than a doping concentration of the source region N+. Regarding Claim 4, Bolotnikov teaches the semiconductor device of claim 3, wherein the drift layer has a conductivity type same as the conductivity type of the junction field-effect transistor region (N-type), and the doping concentration of the drift layer is lower than a doping concentration of the junction field-effect transistor region 10:39-48. Regarding Claim 7, Bolotnikov teaches a method of manufacturing a semiconductor device, comprising: forming a drift layer over a substrate; forming a junction field-effect transistor region in the drift layer, wherein a doping concentration of the junction field-effect transistor region decreases as being far away from the substrate; forming a well region in the drift layer and at a side of the junction field-effect transistor region; forming a source region in the well region; and forming a gate structure over the junction field-effect transistor region and the well region. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Bolotnikov in view of CN 117317019 to Xu. Regarding Claim 5, Bolotnikov teaches the semiconductor device of claim 1, but does not explicitly teach: a shielding region between the well region and the junction field-effect transistor region. However, in analogous art, Xu teaches a shielding region between a JFET and well throughout. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Xu for excellent clamping effect among other benefits (abstract and throughout). Regarding Claim 5, Bolotnikov and Xu teach the semiconductor device of claim 5, wherein the shielding region has a conductivity type same as a conductivity type of the well region (P), and the doping concentration of the shielding region is higher than a doping concentration of the well region (although not explicit, obvious for the clamping effect described by Xu). Allowable Subject Matter Claims 8-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: the cited prior art does not show the method steps required. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVREN SEVEN whose telephone number is (571)270-5666. The examiner can normally be reached Mon-Fri 8:00- 5:00 Pacific. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EVREN SEVEN/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Jun 27, 2024
Application Filed
Jul 01, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12684789
SEMICONDUCTOR DEVICE INCLUDING ACTIVE DIODE AREA
2y 8m to grant Granted Jul 14, 2026
Patent 12684765
SEMICONDUCTOR DEVICE
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Patent 12666712
INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME
3y 1m to grant Granted Jun 23, 2026
Patent 12666838
Light Emitting Display Device
2y 6m to grant Granted Jun 23, 2026
Patent 12666971
HIGH-FREQUENCY SEMICONDUCTOR PACKAGE
2y 7m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
82%
With Interview (+8.6%)
2y 3m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 733 resolved cases by this examiner. Grant probability derived from career allowance rate.

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