DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
1. Claims 1-3, 5, 6, 10, 11 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Mertens et al (USPN 2018/0083443).
Regarding claim 1, Mertens discloses a power clamp device (see figure 3), comprising:
a delay element (304) having an input terminal and an output terminal;
an electrostatic discharge (ESD) bypass element (an ESD bypass element includes 328, 112) having a first terminal (a gate terminal of the device 328 ) and a second terminal, wherein the first terminal is electrically connected to the output terminal of the delay element (the gate terminal of the device 328 is electrically coupled to the output of the delay element 304, see figure 3); and
a gate control circuit (a gate control circuit 308) having a first terminal (a gate of transistor 326 as a first terminal of the gate control circuit 308) electrically connected to the input terminal of the delay element (314), a second terminal (a gate of a transistor 322 of the gate control circuit 308) electrically connected to the output terminal of the delay element (304), and a third terminal (a common terminal of the transistors 322 and 326) electrically connected to the second terminal of the ESD bypass element (a gate terminal of device 112).
Regarding claim 2, Mertens discloses wherein the ESD bypass element (328, 112) is electrically connected between a first supply voltage (VDD) and a second supply voltage (VSS), and wherein, in the case that an ESD event occurs, the ESD bypass element is configured to discharge an ESD current between the first supply voltage and the second supply voltage (in response to the ESD event, the transistor 328 is switched on to trigger the transistor 112 to discharge the ESD event, e.g. see par. 0019).
Regarding claim 3, Mertens discloses wherein the gate control circuit (308) comprises a third transistor (326) having a gate acting as the first terminal of the gate control circuit, and a fourth transistor (322) having a gate acting as the second terminal of the gate control circuit, wherein the third transistor (326) is connected to the fourth transistor (322) at the third terminal of the gate control circuit (a common terminal of the transistors 322 and 326).
Regarding claim 5, Mertens discloses wherein, in the case that an ESD event occurs, the third transistor (the transistor 326 is turned on by the triggered signal VRC) of the gate control circuit (308) is on and the fourth transistor (the transistor 322 is off by the transistor 318) of the gate control circuit is off (see par. 0019).
Regarding claim 6, Mertens discloses in the case that no ESD event occurs, the third transistor (326) of the gate control circuit is off and the fourth transistor (322) of the gate control circuit is on (see par. 0019).
Regarding claim 10, Mertens discloses a transient detector (an RC detector 310, 312, see figure 3) electrically connected to the input terminal of the delay element.
Regarding claim 11, Mertens discloses wherein the delay element includes at least one inverter (314).
2. Claims 1-3, 10-11 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Ker et al (USPN 2009/0086392).
Regarding claim 1, Ker discloses a power clamp device (see figure 6b), comprising:
a delay element (e.g. inverters 630, 640) having an input terminal and an output terminal;
an electrostatic discharge (ESD) bypass element (an ESD bypass element 123) having a first terminal (a gate terminal of the device 123 ) and a second terminal, wherein the first terminal is electrically connected to the output terminal of the delay element (the gate terminal of the device 123 is electrically coupled to the output of the delay element 630, 640, see figure 6c); and
a gate control circuit (a gate control circuit includes 650, MNR1, MPFB) having a first terminal (a gate terminal of MNR1) electrically connected to the input terminal of the delay element (at node 660 of the delay element 630, 640), a second terminal (such as a drain terminal of the transistor MPFB) electrically connected to the output terminal of the delay element (630, 340), and a third terminal (a third terminal at a common point between a gate terminal of the transistor MPFB and a drain terminal of the transistor MNR1) electrically connected to the second terminal of the ESD bypass element (a gate terminal of device 123).
Regarding claim 2, Ker discloses wherein the ESD bypass element (123) is electrically connected between a first supply voltage (131) and a second supply voltage (132), and wherein, in the case that an ESD event occurs, the ESD bypass element is configured to discharge an ESD current between the first supply voltage and the second supply voltage (e.g. see par. 0021).
Regarding claim 3, Ker discloses wherein the gate control circuit (650, MNR1, MPFB) comprises a third transistor (MNR1) having a gate acting as the first terminal of the gate control circuit, and a fourth transistor (MPFB) having a gate acting as the second terminal of the gate control circuit, wherein the third transistor (MNR1) is connected to the fourth transistor (MPFB) at the third terminal of the gate control circuit (the third terminal at a common point between a gate terminal of the transistor MPFB and a drain terminal of the transistor MNR1) electrically connected to the second terminal of the ESD bypass element (a gate terminal of device 123).
Regarding claim 10, Ker discloses a transient detector (an RC detector shown in figure 6b) electrically connected to the input terminal of the delay element.
Regarding claim 11, Ker discloses wherein the delay element includes at least one inverter (630, 640, figure 6b).
3. Claims 12-14 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lee et al (USPN 2007/0171587).
Regarding claim 12, Lee discloses a power clamp device (500 shown in figure 5), comprising:
a delay element (532) having an input terminal (at node N1), an output terminal (at node N2), and a bulk terminal (bulk terminals of 532 shown in figure 5);
an ESD bypass element (540) electrically connected to the output terminal of the delay element (532); and
a well control circuit (534, 350) has a first terminal (at node N2) electrically connected to the ESD bypass element (340), and a second terminal (N3) electrically connected to the bulk terminal of the delay element (via a control element 350).
Regarding claim 13, Lee discloses wherein the ESD bypass element (540) is electrically connected to a first supply voltage (VDD) and a second supply voltage (VSS), and wherein, in the case that an ESD event occurs, the ESD bypass element is configured to discharge an ESD current between the first supply voltage and the second supply voltage (see par. 0019).
Regarding claim 14, Lee discloses wherein the delay element includes a first transistor (a PMOS transistor of the delay element 532) having a gate connected to the input terminal of the delay element (N1), a drain connected to the output terminal of the delay element (N2), a source connected to a second supply voltage (VDD), and a bulk (a substrate terminal of 532) connected to the bulk terminal of the delay element (532).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Ker et al (USPN 2009/0086392) in view of Rice (USPN 2006/0274466).
Regarding claim 7, Ker does not explicitly disclose a first terminal and a second terminal of the ESD bypass element as claimed.
Rice discloses an ESD protection device (see figure 2) comprises an ESD bypass element (206), in a case that an ESD occurs, a first terminal (208) and a second terminal (210) of the ESD bypass element (206) have the same potential (such as same VSS potential, e.g. see par. 0033).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have modified the ESD bypass element of Ker to incorporate an ESD bypass element as disclosed by Rice in order to conduct stronger current during ESD event so that enhancing an ESD protection.
5. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Ker et al (USPN 2009/0086392) in view of Kato et al (USPN 2015/0229125).
Regarding claim 8, Ker does not explicitly disclose a first terminal and a second terminal of the ESD bypass element as claimed.
Kato discloses an ESD protection device (see figure 2) comprises an ESD bypass element (9), in a case that no ESD occurs, a first terminal (a gate terminal of a PMOS transistor 81) and a second terminal (a gate terminal of a NMOS transistor 51) of the ESD bypass element (206) have a different potential (such as a different potential applied to the gates of 81, 51 under normal operation, e.g. see par. 0013).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have modified the ESD bypass element of Ker to incorporate an ESD bypass element as disclosed by Rice in order to prevent unintentional operation and sufficiently discharge ESD surge.
6. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (USPN 2007/0171587) in view of Rice (USPN 2006/0274466).
Regarding claim 16, Lee discloses the ESD bypass element (540), in the case that an ESD event occurs, the ESD discharge element is configured to discharge an ESD current between the first supply voltage and the second supply voltage (see par. 0019), but Lee does not explicitly disclose the ESD discharge element as claimed.
Rice discloses an ESD protection device (see figure 2) comprises an ESD bypass element (206) comprises a cascaded structure (224, 226, see figure 2).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have modified the ESD bypass element of Ker to incorporate an cascaded ESD bypass structure as disclosed by Rice in order to conduct stronger current during ESD event so that enhancing an ESD protection.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
7. Claims 17-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 17-19 of U.S. Patent No. 12,068,597 (also see a matching table shown below). Although the claims at issue are not identical, they are not patentably distinct from each other because both sets of claims are drawn to a power clamp device, comprising: a lateral diffusion metal-oxide-semiconductor field-effect transistor (LDMOSFET) having a gate, a drain electrically connected to a first supply voltage, and a source electrically connected to a second supply voltage, wherein, in the case that an ESD event occurs, the LDMOSFET is configured to discharge an ESD current between the first supply voltage and the second supply voltage; and a capacitance component electrically connected between the gate and the drain of the LDMOSFET, wherein the capacitance component includes a plurality of metal-oxide-metal (MOM) capacitors, wherein the MOM capacitors have a first metal layer, a second metal layer at the same elevation level of the first metal layer, and a third metal layer disposed above the first metal layer and the second metal layer.
USPN 12,068,597
Current application 18/755,747
Claims
Claims
17
17, 18
18
19
19
20
Allowable Subject Matter
8. Claims 4, 9, 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANNY NGUYEN whose telephone number is (571)272-2054. The examiner can normally be reached M-F 8:00AM-4:30PM.
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/DANNY NGUYEN/ Primary Examiner, Art Unit 2838