DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-8 are objected to because of the following informalities:
Claim 1 recites “a BEOL” which should be replaced with “a back end of the line (BEOL)”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 (claim 3) recites limitation “the metal bonds” that lacks antecedent basis in the claims.
Claim 4 (claim 5 and claim 7) recites limitation “the material”. There is insufficient antecedent basis for this limitation in the claim because it is unclear whether “the material” relates back to “the material of the first interposer”, “the material of the second interposer”, or to set forth an additional material.
Claim 6 recites limitations “the nonconducting state” and “the conducting state” that lack antecedent basis in the claims.
Claim 7 recites limitation “the phase change material” that lacks antecedent basis in the claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 9-11 and 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2008/0277644 to Chen et al. (hereinafter Chen).
With respect to claim 9, Chen discloses an apparatus (e.g., switch unit structure) (Chen, Fig. 2, ¶0009- ¶0013, ¶0037, ¶0051-¶0065) comprising:
a phase change material (e.g., PCM 24/32) (Chen, Fig. 2, ¶0051, ¶0054, ¶0059, ¶0062) positioned between first and second metal regions (T3 and T4) (Chen, Fig. 2, ¶0043-¶0044, ¶0059), the first and second metal regions (T3 and T4) coupled to first and second respective electrical terminals (e.g., terminals connected to the circuits A and B), and
first resistive heat element (26) (Chen, Fig. 2, ¶0052, ¶0059) positioned for transferring heat to the phase change material (PCM 24/32), the first resistive heat element (26) coupled to third (T1) and fourth (T2) terminals for passing electrical current through the resistive heat element (26) for changing the phase of the phase change material from a nonconductive state (OFF-amorphous state) (Chen, Fig. 2, ¶0058, ¶0062-¶0065) to a conductive state (ON-crystalline state).
Regarding claim 10, Chen discloses the apparatus of claim 9. Further, Clark discloses the apparatus wherein the phase change material (PCM 24/32) is selected from the group consisting of Chalcogenide glasses (e.g., Ge2Sb2Te5 is a germanium-antimony-tellurium glass material) (Chen, Fig. 2, ¶0051, ¶0054).
Regarding claim 11, Chen discloses the apparatus of claim 9. Further, Clark discloses the apparatus wherein the phase change material (PCM 24/32) changes from a conductive state (ON-crystalline state) to a nonconductive state (OFF-amorphous state) (Chen, Fig. 2, ¶0058, ¶0062-¶0065) by passing electrical current through the resistive heat element for a selected time period (e.g., abrupt high-current pulse or longer lower current pulse for switching Off and On) (Chen, Fig. 2, ¶0058, ¶0063-¶0064).
Regarding claim 15, Chen discloses the apparatus of claim 9. Further, Clark discloses the apparatus, further including a power source (e.g., an external power source coupled to the PCM material through the terminals T1/T2 connecting to the heating element 26) (Chen, Fig. 2, ¶0037, ¶0058-¶0065) coupled to the first resistive heat element (26) to cause the electrical current.
Regarding claim 16, Chen discloses the apparatus of claim 15. Further, Clark discloses the apparatus, further including a controller (e.g., two FET transistors to control switching of the PCM material by providing a specific current pulse: abrupt high-current pulse or longer lower current pulse for switching Off and On through the heating element 26 to the PCM material) (Chen, Fig. 2, ¶0059-¶0064) coupled to the power source to control the supplying of the electrical current.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0058704 to Clark in view of Agarwal et al. (US 2024/0395787, hereinafter Agarwal).
With respect to claim 1, Clark discloses an interconnect structure (e.g., a semiconductor package including interconnect structures 204/404 of two wafers/dies) (Clark, Fig. 7, ¶0002, ¶0005-¶0014, ¶0023-¶0051) comprising:
a first substrate (e.g., a semiconductor die 202) (Clark, Fig. 7, ¶0027-¶0029) having a first surface comprising a layer of insulation (e.g., a thin topmost layer of the dielectric material 208 over the interconnect structures 210A-210D) (Clark, Fig. 7, ¶0030-¶0029) and a metallization (e.g., metallization layer 204 including the interconnect structures 210A-210D) below the layer of insulation (208), the layer of insulation (e.g., the topmost layer of the dielectric material 208) having a first recess (e.g., a number of recesses filled with PCM to form pads 310A-310D) (Clark, Fig. 7, ¶0032) in the layer exposing a metal conductor (e.g., 210A-210D) of the metallization, the first recess filled with a material (PCM) (Clark, Fig. 7, ¶0023, ¶0032, ¶0034) changing from nonconducting (HRS) to conducting (LRS) upon being heated above a predetermined temperature (Clark, Fig. 7, ¶0050, ¶0051), the layer of insulation having a second recess (e.g., a number of recesses filled with metal to form metal-to-metal bonds 604) (Clark, Fig. 7, ¶0046) in the layer exposing a metal conductor (e.g., one of the interconnects 210A-210D) of the metallization, the second recess filled with metal (e.g., to form metal-to-metal bonds 604),
a second substrate (e.g., a semiconductor die 402) (Clark, Fig. 7, ¶0035-¶0037) having a first surface comprising a layer of insulation (e.g., a thin topmost layer of the dielectric material 408 over the interconnect structures 410A-410D) (Clark, Fig. 7, ¶0038-¶0040) and a metallization (404) below the layer of insulation (408), the layer of insulation having a first recess (e.g., a number of recesses filled with PCM to form pads 510A-510D) (Clark, Fig. 7, ¶0040) in the layer exposing a metal conductor (410A-410D) of the metallization (404), the first recess filled with a material (PCM) (Clark, Fig. 7, ¶0040) changing from nonconducting to conducting upon being heated above a predetermined temperature, the layer of insulation having a second recess (e.g., a number of recesses filled to form pads 510A-510D) (Clark, Fig. 7, ¶0040) in the layer exposing a metal conductor (e.g., one of the interconnects 410A-410D) of the metallization (404), the second recess filled with metal (e.g., to form metal-to-metal bonds 604), and
wherein the material (e.g., pads 310A-310D including PCM) (Clark, Fig. 7, ¶0044-¶0048) of the first substrate (202) is bonded to the material (e.g., pads 510A-510D including PCM) of the second substrate (402) and wherein the metal (e.g., one metal of the metal-to-metal bonds 604) of the first substrate (202) is bonded to the metal (e.g., another metal of the metal-to-metal bonds 604) of the second substrate (402).
Further, Clark does not specifically disclose a first interposer having a BEOL; a second interposer having a BEOL, and wherein the material of the first interposer is bonded to the material of the second interposer and wherein the metal of the first interposer is bonded to the metal of the second interposer.
However, Agarwal teaches forming an integrated circuit (Agarwal, Figs. 1, 2A, ¶0012-¶0014) with stacked interposer (150) comprising a first interposer (101) (Agarwal, Figs. 1, 2A, ¶0012) having a BEOL (102), and a second interposer (110) having a BEOL (111), wherein a material of the first bond pads (210) (Agarwal, Figs. 1, 2A, ¶0014) of the first interposer (101) is bonded to a material of the second bond pads (211) of the second interposer (110), to provide stacked interposers to obtain more electrical connections, more routine layers to enable higher bandwidth for device-to device and high bandwidth memories.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the interconnect structure of Clark by configuring the first and second substrates of Clark including the first metallization and the second metallization, respectively as stacked interposers including BEOLs as taught by Agarwal, wherein the stacked interposers are bonded with respective bonding pads including PCM material and metal material of Clark to have a first interposer having a BEOL; a second interposer having a BEOL, and wherein the material of the first interposer is bonded to the material of the second interposer and wherein the metal of the first interposer is bonded to the metal of the second interposer, in order to provide an integrated circuit including stacked interposers to obtain more electrical connections and more routine layers to improve performance of the integrated circuit (e.g., to enable higher bandwidth for device-to device and high bandwidth memories) (Agarwal, ¶0002, ¶0004, ¶0012-¶0014, ¶0017).
Regarding claim 2, Clark in view of Agarwal discloses the interconnect structure of claim 1. Further, Clark discloses the interconnect structure, wherein the metal bonds (e.g., bonds 604 between pads 310A-310D and 510A-510D) are hybrid bonds (Clark, Fig. 7, ¶0044-¶0046).
Regarding claim 3, Clark in view of Agarwal discloses the interconnect structure of claim 1. Further, Clark discloses the interconnect structure, wherein the metal bonds (e.g., bonds 604 comprise metal-to-metal bonds, such as a copper-to-copper bond) (Clark, Fig. 7, ¶0046) comprise copper.
Regarding claim 4, Clark in view of Agarwal discloses the interconnect structure of claim 1. Further, Clark discloses the interconnect structure, wherein the material (PCM) is subject to phase change (e.g., between HRS and LRS) (Clark, Fig. 7, ¶0050-¶0051) upon being heated above a predetermined temperature.
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0058704 to Clark in view of Agarwal (US 2024/0395787) as applied to claim 1, and further in view of Cheng et al. (US 2022/0310913, hereinafter Cheng).
Regarding claim 5, Clark in view of Agarwal discloses the interconnect structure of claim 1. Further, Clark does not specifically disclose the interconnect structure wherein the material comprises silicon.
However, Cheng teaches forming a phase change memory comprising phase change (PCM) materials (Cheng, ¶0030-¶0031) including GST material or silicon alloy (Si-Sb) or silicon-antimony-tellurium (Si-Sb-Te) alloys, to provide PCM memory cell with tunable conductivities and minimized energy consumption.
It would have been obvious to one having ordinary skill to have substituted the PCM material of Clark with the PCM material of Cheng including silicon alloy such that the PCM material comprises silicon. All the claimed elements were known in the prior art and one skilled in the art could have substituted the elements as claimed by known methods with no change in their respective functions, and the substitution would have yielded predictable results to one of ordinary skill in the art at the time of the invention.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the interconnect structure of Clark/Agarwal by forming the PCM material including silicon alloy as taught by Cheng to have the interconnect structure wherein the material comprises silicon, in order to provide PCM memory cell with tunable conductivities and minimized energy consumption (Cheng, ¶0030-¶0031).
Regarding claim 6, Clark in view of Agarwal and Cheng discloses the interconnect structure of claim 5. Further, Clark discloses that the PCM material (Clark, Fig. 7, ¶0023-¶0024, ¶0050-¶0051) is substantially amorphous in the nonconducting state (e.g., high-resistance state HRS) and substantially crystalline in the conducting state (e.g., low-resistance state LRS), but does not specifically disclose that the silicon is substantially amorphous in the nonconducting state and substantially polycrystalline in the conducting state.
However, Cheng teaches forming a phase change memory comprising phase change (PCM) materials (Cheng, ¶0030-¶0031) including GST material or silicon alloy (Si-Sb) or silicon-antimony-tellurium (Si-Sb-Te) alloys having a polycrystalline configuration or amorphous configuration by applying appropriate voltage to the heater, to provide PCM memory cell with tunable conductivities and minimized energy consumption.
It would have been obvious to one having ordinary skill to have substituted the PCM material of Clark with the PCM material of Cheng including silicon alloy such that the PCM material comprises silicon. All the claimed elements were known in the prior art and one skilled in the art could have substituted the elements as claimed by known methods with no change in their respective functions, and the substitution would have yielded predictable results to one of ordinary skill in the art at the time of the invention.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the interconnect structure of Clark/Agarwal/Cheng by forming the PCM material including silicon alloy as taught by Cheng to have the interconnect structure wherein the silicon is substantially amorphous in the nonconducting state and substantially polycrystalline in the conducting state, in order to provide PCM memory cell with tunable conductivities and minimized energy consumption (Cheng, ¶0030-¶0031).
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0058704 to Clark in view of Agarwal (US 2024/0395787) as applied to claim 1, and further in view of Chen (US 2008/0277644).
Regarding claim 7, Clark in view of Agarwal discloses the interconnect structure of claim 1. Further, Clark discloses the interconnect structure, wherein an electrical current is supplied for heating the phase change material above a predetermined temperature (e.g., above the crystallization temperature of the PCM pad 610A-610D but below the melting point pf the material) (Clark, Fig. 7, ¶0050-¶0051), but does not specifically disclose the interconnect structure, further includes a power source coupled to the material.
However, Chen teaches forming a switch unit (Chen, Fig. 2, ¶0037, ¶0058-¶0065) capable of switching the PCM material between resistive (OFF-amorphous state) and conductive (ON-crystalline state) by controlling switch signals from an external power source coupled to the PCM material through the terminals (T1/T2) connecting to the heating element (26), to provide better performance of the PCM switching (Chen, ¶0009- ¶0013, ¶0037, ¶0058-¶0065).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the interconnect structure of Clark/Agarwal by controlling the switch signals provided to the heating element as taught by Chen to have the interconnect structure, further includes a power source coupled to the material, in order to provide better performance of the PCM switching (Chen, ¶0009- ¶0013, ¶0037, ¶0058-¶0065).
Regarding claim 8, Clark in view of Agarwal and Chen discloses the interconnect structure of claim 7. Further, Clark does not specifically disclose the interconnect structure, further includes a controller coupled to the power source to control the supplying of the electrical current for heating the phase change material above the predetermined temperature.
However, Chen teaches forming a switch unit (Chen, Fig. 2, ¶0037, ¶0058-¶0065) capable of switching the PCM material between resistive (OFF-amorphous state) and conductive (ON-crystalline state) by controlling switch signals from an external power source coupled to the PCM material through the terminals (T1/T2) connecting to the heating element (26), and two FET transistors (Chen, Fig. 2, ¶0059-¶0064) to control switching of the PCM material by providing a specific current pulse (e.g., abrupt high-current pulse or longer lower current pulse for switching Off and On) through the heating element (26) to the PCM material (24/32), to provide better performance of the PCM switching (Chen, ¶0009- ¶0013, ¶0037, ¶0058-¶0065).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the interconnect structure of Clark/Agarwal/Chen by controlling the switch signals provided to the heating element as taught by Chen to have the interconnect structure, further includes a controller coupled to the power source to control the supplying of the electrical current for heating the phase change material above the predetermined temperature, in order to provide better performance of the PCM switching (Chen, ¶0009- ¶0013, ¶0037, ¶0058-¶0065).
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US 2008/0277644 to Chen in view of Clark (US 2023/0058704) and Agarwal (US 2024/0395787).
Regarding claims 12 and 13, Chen discloses the apparatus of claim 9. Further, Chen discloses the apparatus wherein the phase change material (PCM 24/32) (Chen, Figs. 1-2, ¶0043, ¶0059) is positioned in one or more insulation layers (e.g., dielectric layers insulating PCM material 24/32 and terminals T1-T4) (as claimed in claim 12); and wherein the first resistive heat element (26) is positioned in one or more insulation layers (as claimed in claim 13), but does not specifically disclose a back end of the line (BEOL) of a semiconductor interconnect structure (as claimed in claim 12); a back end of the line (BEOL) of a semiconductor build (as claimed in claim 13).
However, Clark teaches forming an interconnect structure (e.g., a semiconductor package including interconnect structures 204/404 of two wafers/dies) (Clark, Fig. 7, ¶0002, ¶0005-¶0014, ¶0023-¶0051) comprising a first metallization (e.g., metallization layer 204 including the interconnect structures 210A-210D) and one or more layers of the dielectric material (208) having a number of recesses filled with PCM to form pads (310A-310D) (Clark, Fig. 7, ¶0032), and a second metallization (404) including one or more layers of insulation material having a number of recesses filled with PCM to form pads (510A-510D) (Clark, Fig. 7, ¶0040), wherein the PCM material (e.g., pads 310A-310D including PCM) (Clark, Fig. 7, ¶0044-¶0048) of the first interconnect structure (202/204/208) is bonded to the PCM material (e.g., pads 510A-510D including PCM) of the second interconnect structure (402/404/408), wherein the interconnect structure is configured to provide Joule heating (Clark, Fig. 7, ¶0050-¶0051) to the connection pad interposed between the first metallization layer and the second metallization layer to switch PMC between the resistive (HRS) and conductive (LRS) states.
Further, Agarwal teaches forming an integrated circuit (Agarwal, Figs. 1, 2A, ¶0012-¶0014) with stacked interposer (150) comprising a first interposer (101) (Agarwal, Figs. 1, 2A, ¶0012) having a first BEOL (102), and a second interposer (110) having a second BEOL (111), wherein a material of the first bond pads (210) (Agarwal, Figs. 1, 2A, ¶0014) of the first interposer (101) is bonded to a material of the second bond pads (211) of the second interposer (110), to provide stacked interposers to obtain more electrical connections, more routine layers to enable higher bandwidth for device-to device and high bandwidth memories.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the apparatus of Chen by forming an interconnect structure including the first and second metallization layers and PCM material in the bonding pads between the first and second metallization layers as taught by Clark, wherein the first and second metallization layers include first and second BEOLs respectively as taught by Agarwal to have a back end of the line (BEOL) of a semiconductor interconnect structure (as claimed in claim 12); a back end of the line (BEOL) of a semiconductor build (as claimed in claim 13), in order to provide improved integrated circuit comprising a reconfigurable interconnect utilizing PCM material; and stacked interposers to obtain more electrical connections and more routine layers to improve performance of the integrated circuit (e.g., to enable higher bandwidth for device-to device and high bandwidth memories) (Clark, ¶0003-¶0010, ¶0023; Agarwal, ¶0002, ¶0004, ¶0012-¶0014, ¶0017).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over US 2008/0277644 to Chen in view of Li (US 2010/0258776).
Regarding claim 14, Chen discloses the apparatus of claim 9. Further, Chen does not specifically disclose the apparatus further including a second resistive heat element positioned for transferring heat to set phase change material, the second resistive heat element coupled to 5th and 6th terminals for passing electrical current through the second resistive heat element.
However, Li teaches forming phase-change memory cell structure (Li, Figs. 4-5, ¶0012-¶0014, ¶0017-¶0018, ¶0036-¶0044) comprising a first resistive heat element (e.g., a heater element 402 on top/bottom side of the PCM 404 in Fig. 4) coupled to 3th and 4th terminals (e.g., vias 416) and a second resistive heat element (e.g., a heater element 402 on right/left side of the PCM 404) positioned for transferring heat to set phase change material (PCM 404), the second resistive heat element coupled to 5th and 6th terminals (e.g., vias 416) for passing electrical current through the second resistive heat element, to reduce the size of the overall phase change resistor/heater, and thus to reduce the current needed to program PRAM cell structure (Li, ¶0037, ¶0044).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the apparatus of Chen by forming phase-change memory cell structure including a second resistive heat element as taught by Li to have the apparatus further including a second resistive heat element positioned for transferring heat to set phase change material, the second resistive heat element coupled to 5th and 6th terminals for passing electrical current through the second resistive heat element, in order to reduce the size of the overall phase change resistor/heater, and thus to reduce the current needed to program PRAM cell structure (Li, ¶0037, ¶0044).
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over US 2025/0210101 to Simsek-Ege et al. (hereinafter Simsek-Ege).
With respect to claim 17, Simsek-Ege discloses an anti-fuse apparatus (e.g., microelectronic device comprising fuse/antifuse circuitry 132) (Simsek-Ege, Fig. 1, ¶0031, ¶0046, ¶0077) comprising:
a plurality of anti-fuses (e.g., an array of fuses of the antifuse circuitry) (Simsek-Ege, Fig. 1, ¶0046, ¶0077), and
a voltage/current controller (e.g., voltage generator circuitry 134) (Simsek-Ege, Fig. 1, ¶0049), each respective anti-fuse to be “on” (Simsek-Ege, Fig. 1, ¶0046) or in a conductive state (low-resistance state) from an original “off” or non-conductive state, the voltage/current controller (134) having an input terminal (e.g., power supply terminal 152) (Simsek-Ege, Fig. 1, ¶0049).
Note that limitations “for causing each respective anti-fuse to be “on” or in a conductive state from an original “off” or non-conductive state” and “for receiving anti-fuse data indicating the anti-fuses that should be “on” or in a conducting state” are intended-use limitations. Note that a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. See MPEP §2114. The recitations of “for causing each respective anti-fuse to be “on” or in a conductive state from an original “off” or non-conductive state” and “for receiving anti-fuse data indicating the anti-fuses that should be “on” or in a conducting state” do not distinguish the present invention over the prior art of Simsek-Ege who teaches the structure as claimed.
Further, Simsek-Ege does not specifically disclose a voltage/current controller coupled to the plurality of anti-fuses for causing each respective anti-fuse to be “on” or in a conductive state from an original “off” or non-conductive state, the voltage/current controller having an input terminal for receiving anti-fuse data indicating the anti-fuses that should be “on” or in a conducting state; the voltage/current controller having an input terminal for receiving anti-fuse data indicating the anti-fuses that should be “on” or in a conducting state.
However, Simsek-Ege teaches that the voltage generator circuitry (134) (Simsek-Ege, Fig. 1, ¶0049) is coupled to power terminal (152) which receive various potentials from the external circuitry including potentials for the fuse circuitry (132), to provide microelectronic device with improved performance, increased miniaturization of components, and greater packaging density; and with improved scalability, efficiency, and simplicity (Simsek-Ege, ¶0166).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the anti-fuse apparatus of Simsek-Ege by coupling voltage generator circuitry to the fuse circuitry to receive respective voltages/potentials as taught by Simsek-Ege to have a voltage/current controller coupled to the plurality of anti-fuses for causing each respective anti-fuse to be “on” or in a conductive state from an original “off” or non-conductive state, the voltage/current controller having an input terminal for receiving anti-fuse data indicating the anti-fuses that should be “on” or in a conducting state; the voltage/current controller having an input terminal for receiving anti-fuse data indicating the anti-fuses that should be “on” or in a conducting state, in order to provide microelectronic device with improved performance, increased miniaturization of components, and greater packaging density; and with improved scalability, efficiency, and simplicity (Simsek-Ege, ¶0166).
Regarding claim 18, Simsek-Ege discloses the anti-fuse apparatus of claim 17. Further, Simsek-Ege discloses the anti-fuse apparatus further including a temperature sensor (Simsek-Ege, Figs. 1, 2A-2E, ¶0078, ¶0081), but does not specifically disclose a temperature sensor for indicating the ambient temperature of at least one anti-fuse.
Note that limitations “for indicating the ambient temperature of at least one anti-fuse” are intended-use limitations. Note that a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. See MPEP §2114. The recitations of “for indicating the ambient temperature of at least one anti-fuse” do not distinguish the present invention over the prior art of Simsek-Ege who teaches the structure as claimed.
However, Simsek-Ege teaches forming a temperature sensor to control one or more of a heating element and a cooling element to maintain a desired temperature of the microelectronic device (Simsek-Ege, Figs. 1, 2A-2E, ¶0081).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the anti-fuse apparatus of Simsek-Ege by forming a temperature sensor to control a heating element as taught by Simsek-Ege, wherein the temperature sensor is configured to control the anti-fuse element to have a temperature sensor for indicating the ambient temperature of at least one anti-fuse, in order to provide microelectronic device with improved performance, increased miniaturization of components, and greater packaging density; and with improved scalability, efficiency, and simplicity (Simsek-Ege, ¶0166).
Regarding claim 19, Simsek-Ege discloses the anti-fuse apparatus of claim 17. Further, Simsek-Ege discloses the anti-fuse apparatus further including a memory (e.g., memory array 102) (Simsek-Ege, Figs. 1, 2A-2E, ¶0031-¶0032), but does not specifically disclose a memory for holding anti-fuse data coupled between an anti-fuse data input and the input terminal of the voltage/ current controller.
Note that limitations “for holding anti-fuse data coupled between an anti-fuse data input and the input terminal of the voltage/ current controller” are intended-use limitations. Note that a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. See MPEP §2114. The recitations of “for holding anti-fuse data coupled between an anti-fuse data input and the input terminal of the voltage/ current controller” do not distinguish the present invention over the prior art of Simsek-Ege who teaches the structure as claimed.
However, Simsek-Ege teaches that the fuse circuitry is configured as nonvolatile memory elements and includes an array of PCM cells to store various operational information such as timing and voltage conditions and control bits to enable or disable specific features or functionality, and information used for repairing the memory array (102) (Simsek-Ege, Figs. 1, 2A-2E, ¶0046).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the anti-fuse apparatus of Simsek-Ege by configuring the fuse circuitry as nonvolatile memory elements including an array of PCM cells to store various operational information as taught by Simsek-Ege to have a memory for holding anti-fuse data coupled between an anti-fuse data input and the input terminal of the voltage/ current controller, in order to provide microelectronic device with improved performance, increased miniaturization of components, and greater packaging density; and with improved scalability, efficiency, and simplicity (Simsek-Ege, ¶0166).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over US 2025/0210101 to Simsek-Ege in view of Clark (US 2023/0058704) and Agarwal (US 2024/0395787).
Regarding claim 20, Simsek-Ege discloses the anti-fuse apparatus of claim 17. Further, Simsek-Ege discloses the anti-fuse apparatus wherein the plurality of anti-fuses are memory bits comprising phase change material (e.g., the fuse circuitry 132 is configured as nonvolatile memory elements and includes an array of PCM cells), but does not specifically disclose phase change material enclosed within an interposer.
However, Clark teaches forming an interconnect structure (e.g., a semiconductor package including interconnect structures 204/404 of two wafers/dies) (Clark, Fig. 7, ¶0002, ¶0005-¶0014, ¶0023-¶0051) comprising a number of recesses filled with PCM to form pads (610A-610D) (Clark, Fig. 7, ¶0032), wherein at least one of the pads of the interconnect (e.g., pads 610A-610D including PCM) (Clark, Fig. 7, ¶0044-¶0048) is configured to provide Joule heating (Clark, Fig. 7, ¶0050-¶0051) to switch PMC between the resistive (HRS) and conductive (LRS) states.
Further, Agarwal teaches forming an integrated circuit (Agarwal, Figs. 1, 2A, ¶0012-¶0014) with stacked interposer (150) comprising a first interposer (101) (Agarwal, Figs. 1, 2A, ¶0012) having a first BEOL (102), and a second interposer (110) having a second BEOL (111), wherein a material of the first bond pads (210) (Agarwal, Figs. 1, 2A, ¶0014) of the first interposer (101) is bonded to a material of the second bond pads (211) of the second interposer (110), to provide stacked interposers to obtain more electrical connections, more routine layers to enable higher bandwidth for device-to device and high bandwidth memories.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the anti-fuse apparatus of Simsek-Ege by configuring the fuse circuitry as nonvolatile memory elements including an array of PCM cells as taught by Simsek-Ege, and forming an interconnect structure including the first and second metallization layers and PCM material in the bonding pads between the first and second metallization layers as taught by Clark, wherein the first and second metallization layers include first and second BEOLs of the stacked interposer respectively as taught by Agarwal to have phase change material enclosed within an interposer, in order to provide microelectronic device with improved performance, increased miniaturization of components, and greater packaging density;; and to provide improved integrated circuit comprising a reconfigurable interconnect utilizing PCM material; and stacked interposers to obtain more electrical connections and more routine layers to improve performance of the integrated circuit (e.g., to enable higher bandwidth for device-to device and high bandwidth memories) (Simsek-Ege, ¶0166; Clark, ¶0003-¶0010, ¶0023; Agarwal, ¶0002, ¶0004, ¶0012-¶0014, ¶0017).
Conclusion
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/NATALIA A GONDARENKO/ Primary Examiner, Art Unit 2891
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