DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the feature of “a bottom surface of the top portion of the top electrode layer is lower than a top surface of the middle insulating layer” of claim 3 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Nitayama et al. (US Pat. 6236079).
Regarding claim 1, Nitayama et al. discloses in Fig. 4A, Fig. 4B a semiconductor device, comprising:
a substrate [114];
a peripheral impurity region [116 or 118] positioned in the substrate [114];
a top electrode layer [120, 124 and 112] positioned in the peripheral impurity region [116 or 118] and protruding upwardly from the substrate [114]; and
a middle insulating layer [146, 130, 128] inwardly positioned in the peripheral impurity region [118] and partially surrounding the top electrode layer [120, 124 and 112] to separate the peripheral impurity region [118] and the top electrode layer [124 and 112];
wherein the top electrode layer [120, 124 and 112] comprises:
a bottom portion [120 and 124] positioned in the peripheral impurity region [116 or 118] and extended into the middle insulating layer [146, 130, 128];
a middle portion [lower portion of 112] positioned on the bottom portion [124] and disposed within the middle insulating layer [146, 130, 128]; and
a top portion [upper portion of 112] positioned on the middle portion [lower portion of 112] and protruded out of the middle insulating layer [146, 130, 132];
wherein the peripheral impurity region [118], the middle insulating layer [146, 130, 128], and the top electrode layer [120, 124 and 112] together configure a programmable structure [storage nodes]"[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See MPEP 2114 II. Further, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.]
Regarding claim 2, Nitayama et al. discloses in Fig. 4B
a first inter-dielectric layer [126] disposed between the substrate [114] and the middle insulating layer [146, 130, 128], wherein the bottom portion [12, 124] of the top electrode layer [120, 124 and 112] is extended from the peripheral impurity region [116 or 118] into the middle insulating layer [146, 130, 128] through the first inter-dielectric layer [126]; and
a second inter-dielectric layer [108, 138, 140, 142] disposed on the middle insulating layer [146, 130, 128],
wherein the top portion [upper portion of 112] of the top electrode layer [120, 124 and 112] is surrounded by the second inter-dielectric layer [108, 138, 140, 142] and the middle insulating layer [146, 130, 128].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-10 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Nitayama et al. (US Pat. 6236079) as applied to claim 2 above and further in view of Kim et al. (KR0123752B1).
Regarding claims 3-7, and 15 Nitayama et al. discloses in Fig. 4A, Fig. 4B
wherein the middle portion [lower portion of 112] and the bottom portion [120 and 124] of the top electrode layer [120, 124 and 112] are surrounded by the middle insulating layer [146, 130, 128].
Nitayama et al. fails to disclose
wherein a bottom surface of the top portion of the top electrode layer is lower than a top surface of the middle insulating layer;
wherein a width of the middle portion of the top electrode layer is less than a width of the bottom portion of the top electrode layer;
wherein a width of the middle portion of the top electrode layer is less than a width of the top portion of the top electrode layer;
wherein a width of the bottom portion of the top electrode layer and a width of the top portion of the top electrode layer are substantially the same;
wherein a width of the top portion of the top electrode layer is greater than a width of the bottom portion of the top electrode layer;
wherein the bottom portion of the top electrode layer has a bottle-shaped profile in a cross-sectional perspective.
Kim et al. discloses in Fig. 12
wherein a bottom surface of the top portion [27b] of the top electrode layer [28] is lower than a top surface of the middle insulating layer [24];
wherein a width of the middle portion [upper portion of 27a] of the top electrode layer [28] is less than a width of the bottom portion [lower portion of 27a] of the top electrode layer [28];
wherein a width of the middle portion [upper portion of 27a] of the top electrode layer [28] is less than a width of the top portion [27b] of the top electrode layer [28];
wherein a width of the bottom portion [lower portion of 27a] of the top electrode layer [28] and a width of the top portion [27b] of the top electrode layer [28] are substantially the same;
wherein a width of the top portion [27b] of the top electrode layer [28] is greater than a width of the bottom portion [lower portion of 27a] of the top electrode layer [28];
wherein the bottom portion [lower portion of 27a] of the top electrode layer has a bottle-shaped profile in a cross-sectional perspective.
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Kim et al. into the method of Nitayama et al. to include wherein a bottom surface of the top portion of the top electrode layer is lower than a top surface of the middle insulating layer; wherein a width of the middle portion of the top electrode layer is less than a width of the bottom portion of the top electrode layer; wherein a width of the middle portion of the top electrode layer is less than a width of the top portion of the top electrode layer; wherein a width of the bottom portion of the top electrode layer and a width of the top portion of the top electrode layer are substantially the same; wherein a width of the top portion of the top electrode layer is greater than a width of the bottom portion of the top electrode layer; wherein the bottom portion of the top electrode layer has a bottle-shaped profile in a cross-sectional perspective. The ordinary artisan would have been motivated to modify Nitayama et al. in the above manner for the purpose of providing suitable shape of the capacitor top electrode having desired capacitance.
Regarding claim 8, Nitayama et al. discloses in Fig. 4B, column 4, lines 33-36
wherein the peripheral impurity region [116 or 118] comprises n-type dopants or p-type dopants.
Regarding claims 9-10, Nitayama et al. discloses in Fig. 4A
a peripheral gate structure positioned on the substrate [114] and distant from the programmable structure;
two gate impurity regions [134 and 132] formed in the substrate [114], wherein the peripheral gate structure comprises:
a gate dielectric layer [138] positioned on the substrate [114];
a gate bottom conductive layer [POLY 136a] positioned on the gate dielectric layer [138];
a gate top conductive layer [WSi 136b] positioned on the gate bottom conductive layer [POLY 136a]; and
a top capping layer [SiN] positioned on the gate top conductive layer [WSi 136b];
wherein a distance between the gate impurity regions [132 and 134] is equal to a width of the peripheral gate structure.
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Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Nitayama et al. (US Pat. 6236079) in view of Kim et al. (KR0123752B1) as applied to claim 10 above and further in view of Wang et al. (US Pub. 20180226409).
Regarding claim 11, Nitayama et al. fails to disclose
wherein the top electrode layer and the gate top conductive layer comprise the same material.
Wang et al. discloses in Fig. 9, paragraph [0026]-[0027]
wherein the top electrode layer [62 and 73] and the gate top conductive layer [44 and 72] comprise the same material.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Wang et al. into the method of Nitayama et al. to include wherein the top electrode layer and the gate top conductive layer comprise the same material. The ordinary artisan would have been motivated to modify Nitayama et al. in the above manner for the purpose of providing suitable material of the top electrode layer and the gate top conductive layer so that the top electrode layer and the gate top conductive layer can be formed together by the same process, so as to achieve the effect of process simplification [paragraph [0026]-[0027] of Wang et al.].
Regarding claim 12, Nitayama et al. discloses in column 4, lines 33-67] wherein the middle insulating layer [146, 130, 128] comprises oxides, nitrides, oxynitrides, silicates, aluminates, titanates, nitrides, high-k dielectric materials, or a combination thereof [silicon dioxide and a silicon nitride].
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Nitayama et al. (US Pat. 6236079) in view of Kim et al. (KR0123752B1) and Wang et al. (US Pub. 20180226409) as applied to claim 12 above and further in view of Yang (US Pat. 5306657).
Regarding claim 13, Nitayama et al. discloses in the substrate [114] comprises a silicon substrate.
Nitayama et al. fails to disclose
wherein a crystal orientation of the substrate is <110>, <100>, or <111>.
Yang discloses in column 2, lines 53-56
wherein a crystal orientation of the silicon substrate is <100>.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Yang into the method of Nitayama et al. to include wherein a crystal orientation of the substrate is <100>. The ordinary artisan would have been motivated to modify Nitayama et al. in the above manner for the purpose of providing suitable crystal orientation of the silicon substrate.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Nitayama et al. (US Pat. 6236079) in view of Kim et al. (KR0123752B1) and Wang et al. (US Pub. 20180226409) as applied to claim 11 above and further in view of Wang et al. (US Pub. 20140159129), hereafter Wang129.
Regarding claim 14, Nitayama et al. fails to disclose
wherein the top electrode layer comprises tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminides, or a combination thereof.
Wang129 discloses in Fig. 12, paragraph [0043]
wherein the top electrode layer [209] comprises tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminides, or a combination thereof [tungsten or titanium nitride].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Wang129 into the method of Nitayama et al. to include wherein the top electrode layer comprises tungsten or titanium nitride. The ordinary artisan would have been motivated to modify Nitayama et al. in the above manner for the purpose of providing suitable material of the top electrode layer [paragraph [0043] of Wang129].
Response to Arguments
Applicant’s arguments with respect to claims 1-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Overall, Applicant’s arguments are not persuasive. The claims stand rejected, and the Action is made FINAL.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA T NGUYEN whose telephone number is (571)272-1686. The examiner can normally be reached 9:00am -5:00 pm, Monday-Friday.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893
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