DETAILED ACTION
This action is responsive to the application No. 18/755,987 filed on June 27, 2024.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 11-12, and 14-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2019/0164815).
(Re Claim 1) Lin teaches a circuit structure, comprising (see Fig. 2E and supporting text):
an inter-layer dielectric (ILD) layer (202/224); and
a plurality of unidirectional wires in the ILD layer (226); and one or more additional wires (230) in the ILD layer, the one or more additional wires along a direction different than a direction of the plurality of unidirectional wires, and the one or more additional wires are each continuous with a corresponding one of the plurality of unidirectional wires at a location between ends of the corresponding one of the plurality of unidirectional wires (Fig. 2E).
(Re Claim 2) wherein the one or more additional wires are along a direction orthogonal to the direction of the plurality of unidirectional wires (Fig. 2E)
(Re Claim 3) further comprising: a device layer, wherein the ILD layer is above the device layer, and wherein the plurality of unidirectional wires and the one or more additional wires are electrically coupled to the device layer (¶72).
(Re Claim 11) Lin teaches a computing device, comprising (see Figs. 2E and 9, ¶¶79-86): a board (902); and a component coupled to the board (¶¶79-81,85), the component including an integrated circuit structure, comprising: an inter-layer dielectric (ILD) layer (202/224); and a plurality of unidirectional wires (226) in the ILD layer; and wherein the integrated circuit structure comprises one or more additional wires (230) in the ILD layer, the one or more additional wires along a direction different than a direction of the plurality of unidirectional wires (Fig. 2E), and the one or more additional wires are each continuous with a corresponding one of the plurality of unidirectional wires at a location between ends of the corresponding one of the plurality of unidirectional wires (Fig. 2E), or wherein one or more of the plurality of unidirectional wires have a line width transition therein.
(Re Claim 12) wherein the integrated circuit structure comprises the one or more additional wires in the ILD layer (Fig. 2E).
(Re Claim 14) further comprising: a memory coupled to the board (Fig. 9: DRAM, ROM, etc).
(Re Claim 15) further comprising: a communication chip coupled to the board (Fig. 9, 906).
(Re Claim 16) further comprising: a battery coupled to the board (Fig. 9).
(Re Claim 17) further comprising: a camera coupled to the board (Fig. 9).
(Re Claim 18) further comprising: a display coupled to the board (Fig. 9).
(Re Claim 19) wherein the component is a packaged integrated circuit die (¶¶83-84).
(Re Claim 20) wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (¶¶83-84).
Claims 6-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shimizu (US 2012/0299065).
(Re Claim 6) Shimizu teaches a circuit structure, comprising: an inter-layer dielectric (ILD) layer (see Figs. 6-9, IL1); and a plurality of unidirectional wires in the ILD layer, wherein one or more of the plurality of unidirectional wires have a line width transition therein (see wiring in Figs. 14-15, several wires have a line width transition).
(Re Claim 7) wherein the linewidth transition includes a narrower region between two wider ends (see second wire from top in the middle, see also wire extending in y direction at right side)
(Re Claim 8) further comprising: a device layer, wherein the ILD layer is above the device layer, and wherein the plurality of unidirectional wires are electrically coupled to the device layer (the via plugs PLG connect the wiring L1 layer to the device layer, not shown in Figs. 13-14, refer to Figs. 2, 4B, 6-10B, and 19 showing each wire has one or more via plugs).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. as applied above, and further in view of Hsu et al. (US 2022/0415780).
(Re Claim 4) wherein the device layer comprises nanowire-based devices.
(Re Claim 5) wherein the device layer comprises fin-based devices.
Lin is silent regarding the device layer comprising nanowire-based or fin-based devices. A PHOSITA desiring to make and use Lin’s device would be motivated to look to related art to teach various types of devices used in integrated circuit device layers connected to interconnect wiring. Related art from Hsu teaches the device layer connected to the interconnect wiring may be use fin-based or nanowire-based devices (see Figs. 6A-6B and ¶¶44-49). In view of Hsu, a PHOSITA would find it obvious to use modern transistor types such as fin-based or nanowire-based devices as these offer several well-known advantages. FinFETs and Nanowire FETs wrap the gate around the channel on multiple sides to provide superior electrostatic control, which drastically reduces unwanted power leakage and allows for much smaller, more efficient chip designs than traditional planar transistors.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Shimizu, as applied above, and further in view of Peng et al. (US 2021/0375851).
(Re Claim 9) wherein the device layer comprises nanowire-based devices.
(Re Claim 10) wherein the device layer comprises fin-based devices.
Shimizu is silent regarding the device layer comprising nanowire-based or fin-based devices. A PHOSITA desiring to make and use Shimizu’s device would be motivated to look to related art to teach various types of devices used in integrated circuit device layers for standard cells connected to interconnect wiring. Related art from Peng teaches standard cells may be use standard planar transistors or fin-based or nanowire-based devices (¶23). In view of Peng, a PHOSITA would find it obvious to use modern transistor types such as fin-based or nanowire-based devices as these offer several well-known advantages. FinFETs and Nanowire FETs wrap the gate around the channel on multiple sides to provide superior electrostatic control, which drastically reduces unwanted power leakage and allows for much smaller, more efficient chip designs than traditional planar transistors.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al., as applied above, and further in view of Shin et al. (US 2022/0216150), Chung et al. (US 2023/0075320), and Shimizu (US 2012/0299065).
(Re Claim 13) wherein the one or more of the plurality of unidirectional wires have the line width transition therein.
Lin is silent regarding a line width transition. A PHOSITA would recognize Lin only shows a very small region of an interconnect wiring and would be motivated to look to related art to teach larger areas of representative interconnect wiring. Related art from Shin teaches interconnect wiring includes line width transitions (e.g. see Fig. 4). Related art from Chung also teaches interconnect wiring includes line width transitions (e.g. see Figs. 1 and 4). Related art from Shimizu also teaches interconnect wiring includes line width transitions (see Figs. 2, 4B, 10B, 11B, 12, 13B-14). In view of the prior art, a PHOSITA would find that it is well known and common practice to form interconnect wiring having line width transitions as needed. The reasons and advantages for incorporating a line width transition are numerous including maintaining a minimum distance from adjacent lines to avoid or mitigate capacitances, wiring lines may be made wider or narrower in different regions to maintain uniform density or fill factor to improve uniformity in CMP processes, line width transitions may simply be an artifact of advantageously employing spacer sidewall double patterning techniques, line width transitions may also be advantageously used to form fuses in interconnects. In view of the prior art, incorporating line width transitions, as needed, in Lin’s wiring would be obvious to a PHOSITA for a variety of reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches interconnect wiring having line width transitions and wiring extending in different directions in ILD layers, fin-based and nanowire-based devices, and several from Intel identically teaching Figs. 4A-15 and corresponding text of the instant application (noting Applicant repeats these portions of the disclosure in numerous patents and applications over many years).
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/ERIK T. K. PETERSON/Primary Examiner, Art Unit 2898
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