DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (U.S. 2024/0178128 A1, hereinafter refer to Chen) in view of Guler et al. (U.S. 2023/0275124 A1, hereinafter refer to Guler).
Regarding Claim 1: Chen discloses a semiconductor device (see Chen, Figs.20-26 as shown below and ¶ [0024]), comprising:
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at least a first field-effect transistor (FET1) (155/153) and a second FET (FET2) (157), adjacent to one another on a wafer (see Chen, Figs.20-24 as shown above);
a dielectric bar (119) between gates (163/165) of the FET1 (155/153) and the FET2 (157), and between source/drain regions (160) of the FET1 (155) and the FET2 (157) (see Chen, Figs.20-24 as shown above, Fig.12, ¶ [0049], and ¶ [0058]).
Chen is silent upon explicitly disclosing wherein wrap around source/drain contacts that at least partially surround the source/drain regions of the FET1 and the FET2.
For support see Guler, which teaches wherein wrap around source/drain contacts (114) that at least partially surround the source/drain regions (102) of the FET1 and the FET2 (see Guler, Figs.1 and 15 as shown below, ¶ [0022], and ¶ [0039]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Chen and Guler to enable the Chen’s source/drain contacts to be wrap around source/drain the source/drain regions as taught by Guler in order to improve ohmic contact and lower overall contact resistance.
Regarding Claim 2: Chen as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Chen and Guler further teaches wherein a portion of the dielectric bar (119-1/119-3) between the gates of the FET1 (155/153) and the FET2 (157) has a height H1, wherein another portion of the dielectric bar (119-2) between the source/drain regions (160) of the FET1 (153/155) and the FET2 (157) has a height H2, and wherein H1 > H2 (note: the height of dielectric bar (119-2) is less than the height of dielectric bar (119-2) by a height H5) (see Chen, Figs.23-26 as shown above).
Regarding Claim 3: Chen as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Chen and Guler further teaches wherein a portion of the dielectric bar (119-1/119-3) between the gates of the FET1 (153/155) and the FET2 (157) has a width W1, wherein another portion of the dielectric bar (119-2) between the source/drain regions (160) of the FET1 (153/155) and the FET2 (157) has a width W2 (see Chen, Figs.23-26 as shown above).
The combination of Chen and Guler is silent upon explicitly disclosing wherein W1 > W2.
However, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the width of dielectric bar through routine experimentation and optimization to obtain optimal or desired device performance because the width of dielectric bar is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation (note: for support see Chen et al. (U.S. 2024/0088148 A1, hereinafter refer to Chen ‘148, which teaches the width the of dielectric bar 102/104 is greater than the width of dielectric bar 110) see Chen ‘148, Fig.1C). See MPEP § 2144.05
Regarding Claim 4: Chen as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Chen and Guler further teaches wherein the wrap around source/drain contacts (114) directly contact a bottom, a top, and at least one sidewall of the source/drain regions (102) of the FET1 and the FET2 (see Guler, Figs.1 and 15 as shown above).
Regarding Claim 5: Chen as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Chen and Guler further teaches wherein the wrap around source/drain contacts (114) fully surround the source/drain regions (102) of the FET1 and the FET2 (see Guler, Figs.1 and 15 as shown above).
Regarding Claim 6: Chen as modified teaches a semiconductor device as set forth in claim 5 as above. The combination of Chen and Guler further teaches wherein the wrap around source/drain contacts (114) directly contact a bottom, a top, and opposing sidewalls of the source/drain regions (102) of the FET1 and the FET2 (see Guler, Figs.1 and 15 as shown above).
Regarding Claim 7: Chen as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Chen and Guler further teaches wherein a contact divider (110) in contact with the dielectric bar (118) , wherein the contact divider (110) and the dielectric bar (118) separate adjacent ones of the wrap around source/drain contacts (114) between the source/drain regions (102) of the FET1 and the FET2 (see Guler, Figs.1 and 15 as shown above).
Regarding Claim 8: Chen as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Chen and Guler further teaches wherein a backside power delivery network (1404) (see Guler, Figs.1 and 15 as shown above); and
a backside source/drain contact (1508) that connects one of the wrap around source/drain contacts (1506) to the backside power delivery network (1404) (see Guler, Figs.1 and 15 as shown above).
Regarding Claim 9: Chen discloses a semiconductor device (see Chen, Figs.20-26 as shown above and ¶ [0024]), comprising:
at least a first field-effect transistor (FET1) (153/155) and a second FET (FET2) (157), adjacent to one another on a wafer (101) (see Chen, Figs.20-26 as shown above);
a shallow trench isolation (STI) region (119 bottom portion) between the FET1 (153/155) and the FET2 (157) (see Chen, Figs.20-26 as shown above);
a dielectric bar (119 top portion, note: the claimed separable “shallow trench isolation (STI) region” and “dielectric bar” is equivalent to the integral dielectric layer 119 because making separable dielectric layer is not sufficient by itself to patentably distinguish over the integral dielectric layer unless there are new or unexpected results) between gates (163/165) of the FET1 (153/155) and the FET2 (157), and between source/drain regions (160) of the FET1 (153/155) and the FET2 (1157) (see Chen, Figs.20-26 as shown above),
wherein the dielectric bar (119 top portion) is centered over, and directly contacts the STI region (119 bottom portion) (see Chen, Figs.20-26 as shown above),
wherein a portion of the dielectric bar (119-1/119-3 top portion) between the gates (163/165) of the FET1 (153/155) and the FET2 (157) has a height H1, wherein another portion of the dielectric bar (119-2 top portion) between the source/drain regions (160) of the FET1 (153/155) and the FET2 (157) has a height H2, and wherein H1 > H2 (note: the height of dielectric bar (119-2) is less than the height of dielectric bar (119-2) by a height H5) (see Chen, Figs.23-26 as shown above).
Chen is silent upon explicitly disclosing wherein wrap around source/drain contacts that at least partially surround the source/drain regions of the FET1 and the FET2.
For support see Guler, which teaches wherein wrap around source/drain contacts (114) that at least partially surround the source/drain regions (102) of the FET1 and the FET2 (see Guler, Figs.1 and 15 as shown above, ¶ [0022], and ¶ [0039]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Chen and Guler to enable the Chen’s source/drain contacts to be wrap around source/drain the source/drain regions as taught by Guler in order to improve ohmic contact and lower overall contact resistance.
Regarding Claim 10: Chen as modified teaches a semiconductor device as set forth in claim 9 as above. The combination of Chen and Guler further teaches wherein the portion of the dielectric bar (119-1/119-3 top portion) between the gates (163/165) of the FET1 (153/155) and the FET2 (157) has a width W1, wherein the another portion of the dielectric bar (119-2 top portion) between the source/drain regions (160) of the FET1 and the FET2 has a width W2 (see Chen, Figs.23-26 as shown above).
The combination of Chen and Guler is silent upon explicitly disclosing wherein W1 > W2.
However, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the width of dielectric bar through routine experimentation and optimization to obtain optimal or desired device performance because the width of dielectric bar is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation (note: for support see Chen et al. (U.S. 2024/0088148 A1, hereinafter refer to Chen ‘148, which teaches the width the of dielectric bar 102/104 is greater than the width of dielectric bar 110) see Chen ‘148, Fig.1C). See MPEP § 2144.05
Regarding Claim 11: Chen as modified teaches a semiconductor device as set forth in claim 9 as above. The combination of Chen and Guler further teaches wherein the wrap around source/drain contacts (114) directly contact a bottom, a top, and at least one sidewall of the source/drain regions (102) of the FET1 and the FET2 (see Guler, Figs.1 and 15 as shown above).
Regarding Claim 12: Chen as modified teaches a semiconductor device as set forth in claim 9 as above. The combination of Chen and Guler further teaches wherein the wrap around source/drain contacts (114) fully surround the source/drain regions (102) of the FET1 and the FET2 (see Guler, Figs.1 and 15 as shown above).
Regarding Claim 13: Chen as modified teaches a semiconductor device as set forth in claim 12 as above. The combination of Chen and Guler further teaches wherein the wrap around source/drain contacts (114) directly contact a bottom, a top, and opposing sidewalls of the source/drain regions (102) of the FET1 and the FET2 (see Guler, Figs.1 and 15 as shown above).
Regarding Claim 14: Chen as modified teaches a semiconductor device as set forth in claim 9 as above. The combination of Chen and Guler further teaches wherein a contact divider (110) in contact with the dielectric bar (118), wherein the contact divider (110) and the dielectric bar (118) separate adjacent ones of the wrap around source/drain contacts (114) between the source/drain regions (102) of the FET1 and the FET2 (see Guler, Figs.1 and 15 as shown above).
Regarding Claim 15: Chen as modified teaches a semiconductor device as set forth in claim 9 as above. The combination of Chen and Guler further teaches wherein a backside power delivery network (1404) (see Guler, Figs.1 and 15 as shown above); and
a backside source/drain contact (1508) that connects one of the wrap around source/drain contacts (1506) to the backside power delivery network (1405) (see Guler, Figs.1 and 15 as shown above).
Regarding Claim 16: Chen discloses a method of fabricating a semiconductor device (see Chen, Figs.20-26 as shown above and ¶ [0024]), the method comprising:
forming at least a first device stack (112c/112d/112e) corresponding to a first field-effect transistor (FET1) (153/155) and a second device stack (112a/112b) corresponding to a second FET (FET2) (157), adjacent to one another on a wafer (101) (see Chen, Figs.20-26 as shown above and Figs.8-15),
wherein the first device stack (112c/112d/112e) and the second device stack (112a/112b) each comprises sacrificial layers (108) and active layers (106) (see Chen, Figs.20-26 as shown above and Figs.8-15);
forming a dielectric bar (119) between the first device stack (112c/112d/112e) and the second device stack (112a/112b) (see Chen, Figs.20-26 as shown above and Figs.8-16);
removing the sacrificial layers (108) from the first device stack (112c/112d/112e) and the second device stack (112a/112b) (see Chen, Figs.20-26 as shown above and Figs.8-16);
forming gates (163/165) of the FET1 (153/155) and the FET2 (157) that surround a portion of each of the active layers (106) in a gate-all-around configuration (see Chen, Figs.20-26 as shown above); and
wherein the dielectric bar (119) is present between the gates (163/165) of the FET1 (153/155) and the FET2 (157), and between the source/drain regions (160) of the FET1 (153/155) and the FET2 (157) (see Chen, Figs.20-26 as shown above).
Chen is silent upon explicitly disclosing wherein depositing a sacrificial placeholder in a source/drain area adjacent to the first device stack and the second device stack;
forming source/drain regions of the FET1 and the FET2 in the sacrificial placeholder;
replacing the sacrificial placeholder with wrap around source/drain contacts that at least partially surround the source/drain regions of the FET1 and the FET2.
For support see Guler, which teaches wherein depositing a sacrificial placeholder (902/602) in a source/drain area adjacent to the first device stack and the second device stack (see Guler, Figs.8-9 as shown below, ¶ [0022], and ¶ [0039]);
forming source/drain regions (702) of the FET1 and the FET2 in the sacrificial placeholder (902/602) (see Guler, Figs.8-9 as shown below, ¶ [0022], and ¶ [0039]);
replacing the sacrificial placeholder (902/602) with wrap around source/drain contacts (1202/1204) that at least partially surround the source/drain regions (702) of the FET1 and the FET2 (see Guler, Figs.11-12 as shown below, ¶ [0022], and ¶ [0039]).
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Thus, it would have been within the scope of one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Chen and Guler to enable the known processing condition of Guler to be perform wrap around source/drain contacts that at least partially surround the source/drain regions of Chen because one of ordinary skill in the art before effective filing date of the claimed invention would have been motivated to look to alternative suitable methods of performing the disclosed source/drain contacts of Chen and art recognized suitability for improving ohmic contact and lowering overall contact resistance has been recognized to be motivation to combine. MPEP § 2144.07.
Regarding Claim 18: Chen as modified teaches a method of fabricating a semiconductor device as set forth in claim 16 as above. The combination of Chen and Guler further teaches wherein a portion of the dielectric bar (119-1/119-3) between the gates (163/165) of the FET1 (153/155) and the FET2 (157) has a height H1, wherein another portion of the dielectric bar (119-2) between the source/drain regions (160) of the FET1 (153/155) and the FET2 (127) has a height H2, and wherein H1 > H2 (note: the height of dielectric bar (119-2) is less than the height of dielectric bar (119-2) by a height H5) (see Chen, Figs.23-26 as shown above).
Regarding Claim 19: Chen as modified teaches a method of fabricating a semiconductor device as set forth in claim 16 as above. The combination of Chen and Guler further teaches wherein a portion of the dielectric bar (119-1-119-3) between the gates (163/165) of the FET1 (153/155) and the FET2 (157) has a width W1, wherein another portion of the dielectric bar (119-2) between the source/drain regions (160) of the FET1 and the FET2 has a width W2 (see Chen, Figs.23-26 as shown above).
The combination of Chen and Guler is silent upon explicitly disclosing wherein W1 > W2.
However, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the width of dielectric bar through routine experimentation and optimization to obtain optimal or desired device performance because the width of dielectric bar is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation (note: for support see Chen et al. (U.S. 2024/0088148 A1, hereinafter refer to Chen ‘148, which teaches the width the of dielectric bar 102/104 is greater than the width of dielectric bar 110) see Chen ‘148, Fig.1C). See MPEP § 2144.05
Regarding Claim 20: Chen as modified teaches a method of fabricating a semiconductor device as set forth in claim 16 as above. The combination of Chen and Guler further teaches wherein the wrap around source/drain contacts (114) directly contact a bottom, a top, and at least one sidewall of the source/drain regions (102) of the FET1 and the FET2 (see Guler, Figs.1 and 15 as shown above).
Claim(s) 17 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (U.S. 2024/0178128 A1, hereinafter refer to Chen) and Guler et al. (U.S. 2023/0275124 A1, hereinafter refer to Guler) as applied to claim 16 above, and further in view of Pan et al. (U.S. 2025/0063808 A1, hereinafter refer to Pan).
Regarding Claim 17: Chen as modified teaches a method of fabricating a semiconductor device as applied to claim 16 above. The combination of Chen and Guler is silent upon explicitly disclosing wherein forming sacrificial spacers along a top and sidewalls of the first device stack and the second device stack;
forming the dielectric bar in a space between the sacrificial spacers; and
removing the sacrificial spacers along with the sacrificial layers prior to forming the gates of the FET1 and the FET2.
For support see Pan, which teaches wherein forming sacrificial spacers (208) along a top and sidewalls of the first device stack (202) and the second device stack (202) (see Pan, Fig.11B as shown below and ¶ [0010] -¶ [0012]);
forming the dielectric bar (230) in a space between the sacrificial spacers (208) (see Pan, Fig.11B as shown below and ¶ [0010] -¶ [0012]); and
removing the sacrificial spacers (208) along with the sacrificial layers (205) prior to forming the gates (240) of the FET1 and the FET2 (see Pan, Figs.14-19 as shown below and ¶ [0010] -¶ [0012]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Chen, Guler, and Pan to enable forming sacrificial spacers along a top and sidewalls of the first device stack and the second device stack, forming the dielectric bar in a space between the sacrificial spacers, and removing the sacrificial spacers along with the sacrificial layers prior to forming the gates of the FET1 and the FET2 as taught by Pan in order to mitigate issues of overlay shift and variation in CD.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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