Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 12 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Claim 12 recites wherein a channel width of the first driving transistor is greater than a size of the gap in the extension direction of the sub-portion. However, no written support can be found in the specification that teaches or suggests the claimed limitation.
Claim 15 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. The claim recites a second connection portion that is arranged in the same layer as the second power signal line and is connected to the first connection portion through a via hole. The specification and figures 9C-9D show a second connection portion 342 in the same layer as the first power signal line VDD1. Shielding portion is in the same layer as second power signal line VDD2 but no connection to the first connection portion 341 is shown or described.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites a plurality of sub-pixels comprising an organic light emitting element and a pixel circuit. Claim 1 already recites a first, second, and third sub-pixel, each with an organic light emitting element and pixel circuit. It is not clear if the elements claimed in claim 13 are the same or different from those of claim 1. For purposes of examination, the sub-pixels and their organic light emitting elements and their pixel circuits in claim 13 will be interpreted to correspond to those in claim 1.
Claim 14 is rejected based on its dependency on claim 13.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over Shibusawa US 20190197950 A1 (hereinafter referred to as Shibusawa), in view of Yamada US 7091936 B1 (hereinafter referred to as Yamada), in view of Ishizuka US 20030052618 A1 (hereinafter referred to as Ishizuka), and in view of Cheng et al. US 20180157099 A1 (hereinafter referred to as Cheng).
Regarding claim 1, Shibusawa teaches
An array substrate (“substrate 502” with “pixels 120”, para. 0047 FIG. 1), comprising:
a base substrate (“substrate 502”) and a plurality of repeating units (“pixels 120”) in an array along a first direction (Y direction in FIG. 1) and a second direction (X direction in FIG. 1) on the base substrate, the first direction being intersected with the second direction,
wherein each of the plurality of repeating units comprises a first color sub-pixel (“sub-pixel 134” para. 0113 FIG. 33) and a second color sub-pixel (“sub-pixel 130” para. 0113), each sub-pixel comprises an organic light emitting element (“light emitting element 160” para. 0120 FIG. 33) and a pixel circuit (pixel diagram as shown in FIG. 3) for driving the organic light emitting element, and
the pixel circuit comprises a driving circuit (“drive transistor DRT” in FIG. 3 para. 0061 and “drive transistor 434” in FIG. 33 para. 0112), the driving circuit of the first color sub-pixel comprises a first driving transistor, and the driving circuit of the second color sub-pixel comprises a second driving transistor (each of “sub-pixel 130” and “sub-pixel 132” have a corresponding “drive transistor 434” below, para. 0113).
the array substrate further includes a third color sub-pixel (“sub-pixel 132” para. 0113).
However, Shibusawa fails to teach a channel width-length ratio of the first driving transistor is greater than a channel width-length ratio of the second driving transistor; current efficiency of the first color sub-pixel is less than current efficiency of the second color sub-pixel; a ratio of channel width-length ratios of driving transistors of the second color sub-pixel, the third color sub-pixel and the first color sub-pixel is about 1: 1: 2.
Nevertheless, Yamada teaches
a channel width-length ratio of the first driving transistor is greater than a channel width-length ratio of the second driving transistor (“the largest value is assigned for the W/L of an EL driving TFT connected to a blue display pixel” while “the smallest value is assigned for the transistor size W/L of an EL driving TFT connected to a green display” col 6 lines 16-18 and 21-23 FIG. 1D-1F);
current efficiency of the first color sub-pixel is less than current efficiency of the second color sub-pixel (“a blue display pixel having the lowest emissive efficiency” and “a green display pixel having the highest emissive efficiency” col 6 lines18-19 and 23).
Shibusawa and Yamada teach array substrates. The array substrate in Yamada uses driving transistor TFTs with different channel sizes W/L. Each display pixel has an emissive layer and emissive efficiency of the emissive layer in each display pixel differs according to the emitted color depending on the organic emissive material constituting the emissive layer (19). By forming each display pixel with a size W/L corresponding to their emissive efficiency, the current from the power supply does not need to be adjusted and arranged in a manner where each display pixel receives different power from different lines to achieve a desired luminescence (28). In Yamada, the green pixel has the highest emissive efficiency and therefore has the smallest W/L. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that channel sizes W/L can be adjusted for pixels of different colors due to their different emissive efficiencies.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the array substrate in Shibusawa with the channel width-length ratios taught in Yamada. Current efficiencies vary with organic light emitting materials used for different colors. Their driving transistor channel width-length ratios can be made proportional to their current efficiency so that a desired luminance for each color sub-pixel is achieved.
However, Shibusawa, modified by Yamada, fail to teach a ratio of channel width-length ratios of driving transistors of the second color sub-pixel, the third color sub-pixel and the first color sub-pixel is about 1: 1: 2.
Nevertheless, Yamada teaches a ratio of sizes W/L of the channels of the red, green, and blue pixels being 5:13:28 (col 5 lines 43-44). Ishizuka teaches a drive current providing “FET 20.sub.B” of a blue cell having a channel width of W, a “FET 20.sub.G” of a green cell having a channel width of 2W, and a “FET 20.sub.R” of a red cell having a channel width of 3W, the three FETs 20 having a same length L (para. 0030). The different channel widths of the red, green, and blue driving transistors in Ishizuka produce different driving currents for each pixel (para. 0026), analogous to Yamada, but are at a ratio of channel-width ratios of 3:2:1. Similarly, Cheng teaches “channel regions 132a, 132b, and 132c” having different channel widths, each channel region corresponding to driving transistors in different light emission regions (Cheng para. 0023 and 0034). “Channel region 132a” drives the “light emitting region 112a” of red light, “channel region 132b” drives the “light emitting region 112b” of green light, and “channel region 132c” drives the “light emitting region 112c” of blue light (para. 0032). The ratio of the widths of the channels of red, green, and blue driving transistors is about 1.5-2.1:1:1.5-2.1 (para. 0034). In Yamada, the blue pixel is the least efficient; in Ishizuka, the green pixel is the least efficient; in Cheng, red and blue are less efficient than the green pixel. Yamada, Ishizuka, and Cheng teach different ratios between the sizes of sub-pixels based on their emission efficiency but achieve their desired light output. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the ratios of the channel width-length ratios is chosen according to the desired luminance of each color, where each color pixel emits light with different efficiency.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the ratio of channel width-length ratios of driving transistors depends on the current efficiency of each color sub-pixel and the desired light output of each color sub-pixel. In a case where the blue color sub-pixel is less efficient than the red and green color sub-pixel, its channel width-length ratio will need to be greater.
Regarding claim 2, Shibusawa, in view of Yamada, Ishizuka, and Cheng, teach the array substrate according to claim 1, wherein the current efficiency of the first color sub-pixel is less than current efficiency of the third color sub-pixel, and the current efficiency of the third color sub-pixel is greater than the current efficiency of the second color sub-pixel (as in the case in Yamada, “a blue display pixel having the lowest emissive efficiency”, “a red display pixel having the second highest emissive efficiency”, and “a green display pixel having the highest emissive efficiency” col 6 lines18-23).
Regarding claim 3, Shibusawa, in view of Yamada, Ishizuka, and Cheng, teach the array substrate according to claim 1, wherein the first color sub-pixel is a blue sub-pixel (“sub-pixel 134” emits blue light, para. 0054), the second color sub-pixel is a red sub-pixel (“sub-pixel 130” emits red light, para. 0054), and the third color sub-pixel is a green sub-pixel (“sub-pixel 132” emits green light, Shibusawa para. 0054).
Regarding claim 4, Shibusawa, in view of Yamada, Ishizuka, and Cheng, teach the array substrate according to claim 3, wherein a channel width-length ratio of the driving transistor of sub-pixel of each color is proportional to brightness of a corresponding sub-pixel in a case where white light formed by mixing light of sub-pixels of respective colors is in white balance (the ratio of sizes of the TFT for each driving TFT equals the ratio of necessary current to achieve the desired luminance, such that white balance is facilitated col 6 lines 59-67), and is inversely proportional to current efficiency of the corresponding sub-pixel (transistor size W/L for green display pixel is smallest because it has the highest emissive efficiency while the sizes W/L for the red and blue display pixel are larger, col 5 lines 52-32. The ratio of the sizes is the inverse of the ratio of the emission efficiencies, col 5 lines 43-44).
Regarding claim 8, Shibusawa, in view of Yamada, Ishizuka, and Cheng, teach the array substrate according to claim 1, wherein a channel length of the first driving transistor and a channel length of the second driving transistor are the same (in an embodiment, “the channel length L in each TFT is fixed”, col 5 lines 32-36), and a channel width of the first driving transistor and a channel width of the second driving transistor are different (W/L may be changed by changing W while L is fixed, Yamada col 5 lines 32-33, 36-40).
Regarding claim 9, Shibusawa, in view of Yamada, Ishizuka, and Cheng, teach the array substrate according to claim 1, wherein a channel length of the first driving transistor and a channel length of the second driving transistor are different, and a channel width of the first driving transistor and a channel width of the second driving transistor are different (W/L of display pixels may be varied by changing both W and L, Yamada col 5 line 33).
Regarding claim 10, Shibusawa, in view of Yamada, Ishizuka, and Cheng, teach the array substrate according to claim 9 but fails to expressly teach wherein the channel length of the first driving transistor is greater than the channel length of the second driving transistor, and the channel width of the first driving transistor is greater than the channel width of the second driving transistor.
Nevertheless, the sizes W/L of display pixels may be varied by changing both W and L (Yamada col 5 line 33). Based on the emission efficiencies of the different display pixels, the size W/L the channel of the TFT in the blue display pixel is the largest and the size W/L of the channel of the TFT in the red pixel is smaller (col 6 lines 18-23). The ratio between the size ratios of the blue and red pixel is 28:13 (col 5 line 43). As such, W and L of the TFT of the red pixel can be any combination as long as the ratio is maintained. For example, if W = 28microns and L = 5 microns for the blue display pixel such as in the example in col 5 lines 39-40, the red subpixel can have W and L such as W = 14.3microns and L = 5.5, W = 11.7microns and L = 4.5microns, W = 10.4microns and L = 4, and many more. Conversely, the W and L of the blue display pixel can be made larger, such as W = 33.6microns and L = 6microns. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that smaller values of W and L in the red display pixel than in the blue display pixel are suitable for achieving the desired ratio that provides balanced luminescence.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use widths and lengths of the channel in the first driving transistor that can be greater than the width and length of the width and length of the channel of the second driving transistor. Different combinations of width and length of the channel of each transistor can be used as long as they are at a ratio that provide the current to the sub-pixel that achieves the desired brightness.
Regarding claim 11, Shibusawa, in view of Yamada, Ishizuka, and Cheng, teach the array substrate according to claim 1 but fails to teach wherein a channel of the first driving transistor comprises two sub-portions arranged in parallel, there is a gap between the two sub-portions, and the sub-portions extend in one of the first direction and the second direction, and a size of the sub-portion is greater than a size of the gap in a direction perpendicular to an extension direction of the sub-portion.
wherein a channel of the first driving transistor (region of “semiconductor layer 141a” that overlaps “gate electrode 146” is the “channel region 142e” of “drive transistor DRT”, para. 0076 FIG. 4,6,8) comprises two sub-portions arranged in parallel (as seen in FIG. 8 and more clearly in FIG. 6, “semiconductor layer 141a” and “channel 142e” has two portions that appear parallel, as highlighted in annotated FIG. 6 below), there is a gap between the two sub-portions (there is a gap between both extending portions of “semiconductor layer 141a” and “channel 142e”).
However, Shibusawa, in view of Yamada, Ishizuka, and Cheng, fail to expressly teach the sub-portions extend in one of the first direction and the second direction, and a size of the sub-portion is greater than a size of the gap in a direction perpendicular to an extension direction of the sub-portion.
Nevertheless, FIG. 1 shows the “pixels 120” arranged along the X and Y directions and each sub-pixel in the “pixels 120” includes a “driving transistor DRT”. There are three possibilities for arranging the parallel portions of “semiconductor layer 141”, or “channel 142e”, formed on the planar “substrate 502”: along the X direction, the Y direction, or a mix of both. So long as the “driving transistor DRT” can drive the OLED in each sub-pixel, the examiner understands that the orientation of the parallel portions of “channel 142e” is merely subject to design choice. The “driving transistor DRT” is expected to perform in whichever direction it is arranged. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the direction in which substantially parallel portions of “channel 142e” extend is a matter of design choice.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the sub-portions of the channel can extend in any one of the first direction and the second direction. It is obvious to try both directions, since the first driving transistor is expected to perform equally in either configuration (see MPEP 2143.E).
However, Shibusawa, in view of Yamada, Ishizuka, and Cheng, fail to teach a size of the sub-portion is greater than a size of the gap in a direction perpendicular to an extension direction of the sub-portion.
Nevertheless, the length of “channel 142e” can be adjusted by the following manner: adjusting the length of one of the parallel portions of “channel 142a”, adjusting the length of both parallel portions of “channel 142a”, adjusting the length of the portion of “channel 142e” perpendicular to the parallel portion pair as highlighted in FIG. 6 below, or adjusting a combination of the three parts. If the perpendicular portion is adjusted in length, the gap between the parallel portions is therefore adjusted. As taught in Yamada, a channel’s width and length ratio is proportional to the current driving the sub-pixel and thus the brightness. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the length of “channel 142e” can be adjusted by adjusting the parallel portions, the perpendicular portion, or a combination of all portions so that a desired brightness of the “sub-pixel 134” can be achieved. Either adjustment of portions has an effect on the total length of “channel 142e” and are obvious to try, such as having the perpendicular portion shorter than the parallel portions.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the channel length is controlled by adjusting the length of the sub-portions and the perpendicular portion. The total length of the sub-portions and the perpendicular portion can be set based on the desired brightness of the first sub-pixel and the lengths of each individual portion are a matter of design choice.
Regarding claim 12, Shibusawa, in view of Yamada, Ishizuka, and Cheng, teach the array substrate according to claim 11, wherein a channel width of the first driving transistor is greater than a size of the gap in the extension direction of the sub-portion.
Nevertheless, the lengths of the parallel and the perpendicular portions of “channel 142e” can be set such that the desired brightness is achieved. As taught in Yamada, a channel’s width and length ratio is proportional to the current driving the sub-pixel and thus the brightness. As such, the width can also be adjusted accordingly. There are three possible relationships between the gap between the parallel portions of “channel 142e” and the width of “channel 142e”: the “channel 142e” has a greater width than a size of the gap, the gap has a greater size than a with of the “channel 142e”, or the gap size and “channel with 142e” are the same. Depending on the channel size W/L required to achieve a brightness level for “sub-pixel 134”, the width and length are adjusted accordingly. As in the case of Yamada, the blue pixel is the least efficient and requires the greatest size W/L, so an increase in the “channel 142e” width will further increase the size W/L than with decreasing the length alone. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “channel 142e” having a width greater than a size of the gap is an obvious arrangement to try when seeking to satisfy a size W/L based on the “sub-pixel 134” luminescence efficiency.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a channel width of the first driving transistor greater than the size of the gap between the sub-portions of the channel. It is a solution that is obvious to try for the expected result of increasing the channel width-length ratio.
Regarding claim 13, Shibusawa, in view of Yamada, Ishizuka, and Cheng, teach the array substrate according to claim 1, wherein the plurality of repeating units comprises a plurality of sub-pixels (“pixels 120” include “sub-pixel 134”, “sub-pixel 130”, and “sub-pixel 132”, para. 0113), at least part of the plurality of sub-pixels comprise an organic light emitting element (“light emitting element 160” para. 0121 FIG. 33) and a pixel circuit (pixel diagram as shown in FIG. 3) for driving the organic light emitting element to emit light, the organic light emitting element comprises a first electrode (“common electrode 166” para. 0121), a light emitting layer (“layer 176 can be a light emitting layer” para. 0122 FIG. 33) and a second electrode (“pixel electrode 162”) which are stacked, the second electrode of the organic light emitting element is located between the light emitting layer and the base substrate (“pixel electrode 162” lies between “layer 176” and “substrate 502” as seen in FIG. 33), the second electrode of the organic light emitting element is electrically connected to the pixel circuit (“pixel electrode 162” electrically connects to “drive transistor 434/drive transistor 440_3” though “”conductive layer 440_3”, para. 0120-0121 FIG. 33), the pixel circuit comprises a plurality of transistors (pixel circuit in FIG. 3 shows a plurality of transistors, para. 0061); the array substrate further comprising:
an active semiconductor layer (“semiconductor layer 141” para. 0075 FIG. 4 and 6), comprising channels, source regions and drain regions of the plurality of transistors;
a source-drain metal layer (layer with “drive power supply line 428” and “image signal line 409”, para. 0083 FIG. 14), located on a side of the active semiconductor layer away from the base substrate; wherein the source-drain metal layer comprises a first power signal line (“drive power supply line 428”), and the array substrate further comprises a second power signal line (“capacitor line 412” para. 0084) on a side of the source-drain metal layer away from the base substrate (“capacitor line 412” is on a side of the layer with “drive power supply line 428” and “image signal line 409” and away from “substrate 502” as seen in FIG. 15); the array substrate further comprises reset power signal lines, the reset power signal lines comprise a first reset power signal line (“reset control line 416_1” para. 0065) and a second reset power signal line (“reset control line 416_2” para. 0068); the first reset power signal line and the second reset power signal line are electrically connected to the pixel circuit and configured to provide a reset signal (“reset control lines 416_1 and 416_2” are connected to the circuit and provide a signal to the gate of “reset transistors RST(n) and RST2(n)”, para. 0065 and 0068); and the first power signal line and the second power signal line are electrically connected to the pixel circuit (drive power supply line 428” is connected to “capacitor line 412” and the source electrode of “drive transistor DRT”, para. 0084 and 0098).
Regarding claim 14, Shibusawa, in view of Yamada, Ishizuka, and Cheng, teach the array substrate according to claim 13, wherein the array substrate further comprises data lines (“image signal line 409” para. 0066), a data line is electrically connected to the pixel circuit to provide a data signal (“image signal line 409” connects to “selection transistor SST” to provide “image signal SL(m)”, para. 0066); at least one pixel circuit comprises a driving transistor (“driving transistor DRT” in FIG. 3 para. 0061, “driving transistor 434” in FIG. 33 para. 0112), a first light emitting control transistor (“power supply transistor PST” para. 0061), a second light emitting control transistor (“light emission control transistor BCT” para. 0061) and a first connection portion (“conductive layer 440_3” para. 0084 FIG. 4-5), the first connection portion is located in the source-drain metal layer (“conductive layer 440_3” is arranged in the same layer as “image signal line 409” and “drive power supply line 428”, para. 0083 FIG. 14-15), a second electrode of the first light emitting control transistor is electrically connected to a first electrode of the driving transistor (drain electrode of “power supply transistor PST” connects to “driving transistor DRT”, para. 0062 FIG. 3), a first electrode of the second light emitting control transistor is electrically connected to a second electrode of the driving transistor (drain of “driving transistor DRT” is connected to source of “light emitting control transistor BCT”, para. 0067 FIG. 3), and a second electrode of the second light emitting control transistor is electrically connected to the first connection portion through a second via (drain electrode of “light emitting control transistor BCT” is connected to the first terminal of the “light emitting element OLED”, para. 0067. Also, FIG. 4-5, “conductive layer 440_3 is electrically connected to the semiconductor layer 141 through the opening 152_1”, and “pixel electrode 162 is electrically connected to the conductive layer 440_3” suggest that the drain of “light emitting control transistor BCT” connects to “pixel electrode 162” through “opening 152_1” with “conductive layer 440_3”, para. 0084, 0086).
However, Shibusawa modified by Yamada, Ishizuka, and Cheng fails to teach the first electrode of the first light emitting control transistor is electrically connected to the first power signal line through a first via hole; a first straight line extending along the first direction passes through at least one first via hole and at least one second via.
Nevertheless, Shibusawa shows in FIG. 12-13 “openings 152_1” formed in “insulating film 108” that expose portions of “semiconductor layer 141”. The “openings 152_1” are spaced apart in a horizontal direction in FIG. 12. The examiner understands that the horizontal direction may correspond to the X direction, the Y direction, or a mix of both depending on design choice. A portion of “conductive layer 440_3” is formed in an “opening 152_1” that is understood to correspond to the via that connects the drain of “light emitting control transistor BCT” and “pixel electrode 162”. The source electrode of the “power supply transistor PST” is connected to the “drive power supply line 428” (para. 0098); from this teaching and noticing that “drive power supply line 428” passes over an “opening 152_1”, the examiner understands that “drive power supply line 428” is connected to “semiconductor layer 141” at the source of “power supply transistor PST” through the “opening 152_1”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the “openings 152_1” may be aligned in the first direction and that an “opening 152_1” serves to electrically connect the source electrode of “power supply transistor PST” to “drive power supply line 428”.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a straight line extending in the first direction passes through the first via hole and second via and the first electrode of the first light emitting control transistor is electrically connected to the first power signal line through the first via hole.
Regarding claim 15, Shibusawa, in view of Yamada, Ishizuka, and Cheng, teach the array substrate according to claim 14, wherein the pixel circuit further comprises a second connection portion (“reset potential line 414” para. 0081 FIG. 12), the second connection portion is arranged in the same layer as the second power signal line (“reset potential line 414” is at same level of “capacitor line 412”, para. 0081), the second connection portion is electrically connected to the first connection portion through a third via hole (“conductive layer 440_3” electrically connects to the “semiconductor layer 141”, which connects to “conductive layer 440_2”, which is electrically connected to the “reset potential line 414” through the “opening 152_3”, para. 0084), and the second power signal line is electrically connected to the first power signal line through a fourth via (“drive power supply line 428 is electrically connected to the capacitor line 412 through the opening 152_3” different from the “opening 152_3” for the “reset potential line 414”, para. 0084); a second straight line extending along the first direction passes through at least one fourth via hole and at least one third via (if “openings 152_1” are aligned in the first direction as taught in claim 14, “opening 152_3” on the “reset potential line 414” and “opening 152_3” on “capacitor line 412” extends at least partially along the first direction as drawn in annotated FIG. 12 below).
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Regarding claim 17, Shibusawa, in view of Yamada, Ishizuka, and Cheng teaches an organic light emitting diode display device (“display device 100” para. 0047 FIG. 1), comprising the array substrate according to claim 1 (“display device 100” comprises “substrate 502” and “pixels 120”).
Regarding claim 19, Shibusawa, in view of Yamada, Ishizuka, and Cheng teaches a manufacturing method for manufacturing the array substrate according to claim 1, comprising:
forming the first color sub-pixel including the first driving transistor and the second color sub-pixel including the second driving transistor on the base substrate (“sub-pixel 134” and “sub-pixel 130” are part of “pixel 120”, which is formed on “substrate 502”, Shibusawa para. 0047 and 0053 FIG. 33. Each sub-pixel is understood to include the circuitry, and therefore the “drive transistor DRT”, in FIG. 3.),
wherein forming the first driving transistor and the second driving transistor comprises:
acquiring preset brightness and preset current efficiency of the first color sub-pixel and the second color sub-pixel (the required luminance of each color is determined and expressed as luminance ratio “R:G:B=0.54:1:0.63”, Yamada col 6 lines 43-53 FIG. 6. The current efficiency of each driving transistor in each color display pixel is determined as “G.sub.eff:R.sub.eff:B.sub.eff=10:3.8:1.8”, col 5 lines 18-22), wherein the preset brightness is brightness of sub-pixel of each color in a case where white light formed by mixing light of sub-pixels of respective colors is in white balance (the required luminance of each color is determined based on the desired target white color, col 6 lines 48-53 FIG. 6);
calculating a ratio of the channel width-length ratio of the first driving transistor to the channel width-length ratio of the second driving transistor according to the preset brightness and the preset current efficiency of the first color sub-pixel and the second color sub-pixel (“The sizes of the driving TFTs for supplying current to the organic EL elements for R, G, and B can be determined such that the ratio of the current amounts for R, G, and B equals to the above example ratio by taking into account the chromaticity of R, G, and B, the chromaticity of the target white color, and the emissive efficiency for each color” col 6 lies 59-64), wherein the channel width-length ratio of the driving transistor of sub-pixel of each color is proportional to the preset brightness (since the size W/L of the green color pixel transistor is the smallest because it is the most efficient, col 5 lines 25-29, and the size W/L of the blue display pixel is the greatest because it is the least efficient, col 5 lines 39-40, the examiner understands that the size W/L of the driving transistor is proportional to the luminance) and is inversely proportional to the preset current efficiency (“W.sub.G:W.sub.R:W.sub.B=1/G.sub.eff:1/R.sub.eff:1/B.sub.eff” col 5 line 43); and
manufacturing the first driving transistor and the second driving transistor according to the ratio (the driving transistor of the blue and green display pixels are made according to the ratios, col 5 lines 34-45).
Regarding claim 20, Shibusawa, in view of Yamada, Ishizuka, and Cheng the manufacturing method according to claim 19, wherein acquiring the preset brightness of the first color sub-pixel and the second color sub-pixel comprises:
acquiring an optical parameter of a display device including the array substrate (“display device 100” Shibusawa para. 0047 FIG. 1), and calculating the preset brightness of sub-pixel of each color according to the optical parameter (“luminance required for each of R, G, and B to achieve the white color at 100% luminance is determined as, for example, 25%:46%:29%” based on the target white color chromaticity (0.31,0.32), col 6 lines 43-53),
wherein the optical parameter comprises preset brightness (“white color at 100% luminance”) and a preset white balance coordinate of white light formed by sub-pixels of respective colors (“chromaticity coordinates (x,y:0.31, 0.32)”), and preset color coordinates of the first color sub-pixel (coordinates of blue display pixel are (0.17, 0.17), FIG. 6) and the second color sub-pixel (coordinates of green display pixel are (0.30, 0.63), FIG. 6).
Claim 6-7 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Shibusawa, in view of Yamada, Ishizuka, and Cheng, as applied to claim 17 above, in view of Yoon et al. US 20200380915 A1 (hereinafter referred to as Yoon).
Regarding claim 6, Shibusawa, in view of Yamada, Ishizuka, and Cheng, teach the array substrate according to claim 1 but fail to expressly teach wherein the channel width-length ratio of the driving transistor of the first color sub-pixel is 4/25~6.5/25, and both the channel width-length ratios of the second color sub-pixel and the third color sub-pixel are 2.4/30~4/30.
Nevertheless, Yoon teaches several examples of how the ratio of “channel width W” and “channel length L” ratios of a “transistor T” can be modified. Examples include changing the length by adjust the length of “gate electrode G1” (para. 0193 FIG. 12A-12C), changing the width by adjusting the width of “semiconductor layer A” (para. 0194 FIG. 12B), changing the channel length by adding a bend to “semiconductor layer A” (para. 0193 and 0199 FIG. 12C and 13). The examiner understands that there are three possible relationships between “channel width W” and “channel length L”: “channel width W” is larger than “channel length L”, “channel width W” is smaller than “channel length”, or they are both the same. The luminance of the “pixel P” may be controlled by adjusting a ratio of the “channel width W” to the “channel length L” of the first transistor (para. 0187). In the case of Yamada, the widths of the channels are greater than their length. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the ratio of the “channel width W” and “channel length L” is a result effective variable than can be chosen based on the desired luminance of the pixel. The ratio can be greater or lesser than 1.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the array substrate taught between Shibusawa, Yamada, Ishizuka, and Cheng with the channel widths and lengths as further taught in Yoon. The channel width can be greater, lesser, or equal to the channel length depending on the desired luminance of the sub-pixel.
Regarding claim 7, Shibusawa, in view of Yamada, Ishizuka, and Cheng but fails to teach the array substrate according to claim 6, wherein the channel width-length ratio of the driving transistor of the first color sub-pixel is 5/25, and both the channel width-length ratios of the second color sub-pixel and the third color sub-pixel are 3/30.
Nevertheless, Yoon teaches several examples of how the ratio of “channel width W” and “channel length L” ratios of a “transistor T” can be modified. Examples include changing the length by adjust the length of “gate electrode G1” (para. 0193 FIG. 12A-12C), changing the width by adjusting the width of “semiconductor layer A” (para. 0194 FIG. 12B), changing the channel length by adding a bend to “semiconductor layer A” (para. 0193 and 0199 FIG. 12C and 13). The examiner understands that there are three possible relationships between “channel width W” and “channel length L”: “channel width W” is larger than “channel length L”, “channel width W” is smaller than “channel length”, or they are both the same. The luminance of the “pixel P” may be controlled by adjusting a ratio of the “channel width W” to the “channel length L” of the first transistor (para. 0187). In the case of Yamada, the widths of the channels are greater than their length. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the ratio of the “channel width W” and “channel length L” is a result effective variable than can be chosen based on the desired luminance of the pixel. The ratio can be greater or lesser than 1.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the array substrate taught between Shibusawa, Yamada, Ishizuka, and Cheng with the channel widths and lengths as further taught in Yoon. The channel width can be greater, lesser, or equal to the channel length depending on the desired luminance of the sub-pixel.
Regarding claim 18, Shibusawa, in view of Yamada, Ishizuka, and Cheng teach the organic light emitting diode display device according to claim 17 but fail to teach wherein the display device is a vehicle mounted display device.
Nevertheless, Yoon teaches a “display device 1A” that is used as a dashboard for vehicles but can also serve in smartwatches, laptops, or mobile phones (para. 0075 and 0087 FIG. 1). Shibusawa, Yamada, Ishizuka, and Cheng teach display devices but no description as to where they are implemented as displays is given. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the display taught between Shibusawa and Yamada can be used in vehicles dashboards.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the organic light emitting diode display device taught between Shibusawa and Yamada with the display device in Yoon. The organic light emitting diode display device can be a vehicle mounted display device.
Allowable Subject Matter
Claims 5 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, Shibusawa teaches a first light controlling transistor “power supply transistor PST” and data writing transistor “selection transistor SST” connected to the source driving transistor “drive transistor DRT” (FIG. 30 para. 0070). During light emission, “selection transistor SST” is in an off state and the potential of the source electrode of “drive transistor DRT” is VDD supplied by “drive power supply line 428” (para. 0098 FIG. 29). The examiner understands that the voltage difference between the source and drain of a transistor is proportional to the current through the transistor, and the channel width-length ratio is proportional to the current. However, Shibusawa fails to teach or render obvious wherein the channel width-length ratio of the driving transistor of sub-pixel of each color is also inversely proportional to a difference between a voltage of a data signal input to the corresponding sub-pixel and a power supply voltage. Therefore, claim 5 is considered to contain allowable subject matter.
Regarding claim 16, Shibusawa teaches a same “scan signal SG(n)” applied to the “scanning signal line 410” to “selection transistor SST” and “correction transistor TCT” (para. 0066) and the gate electrodes of “power supply transistor PST” and “light emitting control transistor BCT” are connected to the same “light emitting control line 418” to receive a same “light emitting control signal BG(n)”. Shibusawa fails to teach the gate electrode of the threshold compensation transistor is configured to be electrically connected to a second scanning signal line to receive a compensation control signal, a second light emitting control signal. Therefore, claim 16 is considered to contain allowable subject matter.
Conclusion
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/ERIC MANUEL MULERO FLORES/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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