DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
2. Claim 10 is objected to because of the following informalities.
Line 4 recites the limitation, “wherein one of the plurality of delay circuits is selected based on first internal signal.” Here, “first internal signal” clearly refers to “a first internal signal” of claim 9 (see also claims 11-12). Therefore, the limitation should read, “wherein one of the plurality of delay circuits is selected based on the first internal signal.”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 20110258475 A1).
Regarding independent claim 1, Lee teaches an apparatus comprising:
a data bus (FIG. 5, dqs, dq) including a first portion (FIG. 5, right of flip-flops 505) having a timing domain which is controlled based on a first timing signal (FIG. 5, Core_Clk domain) and further including a second portion (FIG. 5, left of flip-flops 505) having a timing domain which is controlled based on a second timing signal (FIG. 5, dqs domain); and
a data transfer circuit coupled to the data bus (FIG. 5, delay circuit 507 and flip-flops 505), the data transfer circuit including a data driver (FIG. 5, flip-flops 505) between the first portion of the data bus and the second portion of the data bus and a timing control circuit coupled to the data driver (FIG. 5, 507);
wherein the timing control circuit includes a variable delay (¶ [0039] teaches Delay 507 is programmable) to add an amount of delay to a first control signal (FIG. 5, Core_Clk 508) to generate a second control signal (FIG. 5, Capture_Clk 506); and
wherein the data driver is configured to drive data from the second portion of the data bus to the first portion of the data bus responsive to the second control signal (Lee FIG. 5, “data driver” 505 drives data dq from the dqs domain to the Core_Clk domain as clocked by “second control signal” 506).
Regarding claim 9, Lee teaches the limitations of claim 1.
Lee further teaches the delay amount of the timing control circuit is controlled based on a first internal signal (¶ [0039] teaches programmable delay element is controlled by a self-configuring logic circuit as shown in FIG. 10 (see output signal 1004)).
Claim Rejections - 35 USC § 103
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
9. Claims 2-3 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, et al (20110258475), hereinafter Lee, in view of Takada (US 20220301607 A1).
Regarding claim 2, Lee teaches the limitations of claim 1.
Lee does not teach a delay amount of the timing control circuit is changed based on a frequency of the first timing signal.
Takada teaches a delay amount of the timing control circuit is changed based on a frequency of the first timing signal (in Equation 6 in the discussion of the training process in ¶ [0063-0065], there is an inverse relationship between the replica clock frequency and delay, the replica clock based on data P0 clocked by “first timing signal” CK0 (FIG. 2, 34; ¶ [0061-0065]), the CK0 domain of Takada is analogous or mapped to the Core_Clk domain of Lee).
Note Lee as modified by Takada substitutes the programmable delay circuit of Takada (FIG. 4) and its affiliated control circuits (e.g., FIG. 4, training circuit 34, control circuit 33) for the programmable delay circuit of Lee (FIG. 5, 507). See Figure A which follows.
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Figure A: Delay circuit of Takada (right) substituted for delay circuit of Lee (left).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Takada into the method of Lee to include changing the delay amount of the timing control circuit based on a frequency of the first timing signal. The ordinary artisan would have been motivated to modify Lee in the above manner for the purpose of retraining so sampling can be normally performed when the fluctuations in the measured frequency exceed a permissible range (Takada ¶ [0066]).
Regarding claim 3, Lee as modified by Takada teaches the limitations of claim 2.
Lee further teaches the second timing signal has the same frequency as the first timing signal (¶ [0012] describes synchronization of dqs (“second timing signal”) and the core clock (“first timing signal”) as an implied design goal. However, such synchronization is also understood as necessary in a synchronous system to avoid lost bits when dqs is faster than Core_Clk and resampling “stale” bits when Core_Clk is faster than dqs. See also FIG. 6.).
Regarding claim 10, Lee teaches the limitations of claim 9.
Lee does not teach the timing control circuit includes a plurality of delay circuits having mutually different delay amounts, and wherein one of the plurality of delay circuits is selected based on first internal signal.
Takada teaches the timing control circuit includes a plurality of delay circuits having mutually different delay amounts (FIG. 4, delay circuits 3-1..3-K are arranged such that each signal input to multiplexer 4 has been delayed by a mutually different delay amount), and
wherein one of the plurality of delay circuits is selected based on first internal signal (FIG. 4, the delayed signal/circuit is selected by the STAGE NUMBER ADJUSTMENT SIGNAL via multiplexer 4).
Because the delay circuits of both Lee and Takada delay flip-flop clocks used to transfer write data (Lee FIG. 5, programmable delay element 507 and flip-flops 505 transferring data dq; Takada FIG. 2, programmable delay element DL2 and flip-flops FF0 transferring data DQ’), it would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the programmable delay element of Takada with the programmable delay element of Lee to yield predictable results (see Figure A). See MPEP § 2143(I)(B).
10. Claims 4-8 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, et al (20110258475), hereinafter Lee, in view of Fujisawa (US 20110058443 A1).
Regarding claim 4, Lee teaches the limitations of claim 1.
Lee does not teach a data terminal supplied with a write data from outside.
Fujisawa teaches a data terminal (FIG. 1, 14) supplied with a write data from outside (FIG. 1, DQ; ¶ [0037]).
Lee as modified by Fujisawa teaches an input receiver circuit (Lee FIG. 5, Phy; Fujisawa FIG. 1, 82) configured to capture the write data on the data terminal (Lee FIG. 5, input latches 502 clocked by dqs 503; Fujisawa FIG. 1, data input circuit 82 is shown synchronized with data strobe DQS),
wherein the data bus is configured to convey the write data output from the input receiver circuit (Fujisawa ¶ [0037]).
Lee as modified by Fujisawa (see Figure B which follows) substitutes the Phy circuit of Lee (Lee FIG. 5, flip-flops 502 and Delay 504, clocked by dqs) for the data input circuit of Fujisawa (Fujisawa FIG. 1, 82, clocked by DQS), and substitutes the data transfer circuit of Lee (Lee FIG. 5, flip-flops 505 and Delay 507) for the FIFO circuit of Fujisawa (Fujisawa FIG. 1, 84).
Because the Phy circuit of Lee and Data Input Circuit of Fujisawa synchronize the data input to the data strobe, and because both the “data transfer circuits” of Lee (FIG. 5, flip-flops 505) and Fujisawa (FIG. 1, 84) serve to transfer data across two different clock domains (Lee, FIG. 5, dqs and Core_Clk; Fujisawa, FIG. 1, DQS and CK), it would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the data input and FIFO circuits of Fujisawa with the Phy and flip-flop (505) circuits of Lee to yield predictable results. See MPEP § 2143(I)(B).
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Figure B: Data capture and transfer circuits of Lee FIG. 5 mapped to Fujisawa FIG. 1.
Regarding claim 5, Lee as modified by Fujisawa teaches the limitations of claim 4.
Lee further teaches the input receiver circuit is configured to capture the write data responsive to the second timing signal (FIG. 5, input latches 502 capture data dq as clocked by “second timing signal” dqs 503).
Regarding claim 6, Lee as modified by Fujisawa teaches the limitations of claim 5.
Fujisawa further teaches the second timing signal is a data strobe signal supplied from outside (FIG. 1, DQS is received from “outside” via terminal 15a).
Regarding claim 7, Lee as modified by Fujisawa teaches the limitations of claim 6.
Fujisawa further teaches the first timing signal is a clock signal supplied from outside (FIG. 2, “first timing signal” CK is received from “outside” via terminal 11a and is the basis for internal clock ICLK supplied to various internal circuits except those that form a data output system (¶[0027])).
Regarding claim 8, Lee as modified by Fujisawa teaches the limitations of claim 7.
Fujisawa further teaches a memory cell array (FIG. 1, 70); and
a write amplifier circuit (FIG. 1, 75) configured to store the write data on the first portion of the data bus to the memory cell array (¶ [0036-0037]) responsive to a write timing signal (FIG. 1, writing amplifier 75 is responsive to write control circuit 54; ¶ [0036]),
wherein a timing domain of the write timing signal is controlled based on the first timing signal (FIG. 1, write control circuit 54 is coupled to ICLK, which is based upon “first timing signal” CK (¶[0027])).
11. Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, et al (20110258475), hereinafter Lee, in view of Oh, et al (US 20190172512 A1), hereinafter Oh, and further in view of Takada (US 20220301607 A1).
Regarding claim 11, Lee teaches the limitations of claim 9.
Lee does not teach a mode register circuit configured to store the first internal signal.
Oh teaches a mode register circuit (FIG. 3, 222; ¶ [0071]) configured to store the first internal signal (¶ [0071]) teaches mode register 222 stores an internal mode signal (SMS); Claim 2 teaches internal mode signal SMS reflects the clock frequency).
Lee as modified by Oh does not teach their respective internal signals are necessarily analogous.
Takada teaches a delay amount of the timing control circuit is changed based on a frequency of the first timing signal (in Equation 6 in the discussion of the training process in ¶ [0063-0065], there is an inverse relationship between the replica clock frequency and delay, the replica clock based on data P0 clocked by “first timing signal” CK0 (FIG. 2, 34; ¶ [0061-0065]), the CK0 domain of Takada is analogous or mapped to the Core_Clk domain of Lee).
Therefore, because Lee teaches an internal signal controlling the delay, Oh teaches an internal signal reflecting the clock frequency and stored in a mode register, and Takada teaches an internal signal reflecting clock frequency controlling the delay, Lee as modified by Oh and Takada teaches a mode register circuit configured to store the first internal signal (that controls the delay amount of the timing control circuit – see claim 9).
Note Lee as modified by Takada substitutes the programmable delay circuit of Takada (FIG. 4) and its affiliated control circuits (e.g., FIG. 4, training circuit 34, control circuit 33) for the programmable delay circuit of Lee (FIG. 5, 507). See Figure A.
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Oh into the method of Lee to include relating the internal mode signal to a frequency of clock/timing signal (Oh, claim 2). The ordinary artisan would have been motivated to modify Lee in the above manner for the purpose of determining whether to generate a strobe signal based on a frequency of the main clock signal (Oh ¶ [0008]).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Takada into the method of Lee to include changing the delay amount of the timing control circuit based on a frequency of the first timing signal. The ordinary artisan would have been motivated to modify Lee in the above manner for the purpose of retraining so sampling can be normally performed when the fluctuations in the measured frequency exceed a permissible range (Takada ¶ [0066]).
Regarding claim 12, Lee as modified by Oh and Takada teaches the limitations of claim 11.
Takada further teaches the first internal signal relates to a frequency of the first timing signal (In Equation 6 in the discussion of the training process in ¶ [0063-0065], there is an inverse relationship between the replica clock frequency and delay, the replica clock based on data P0 clocked by “first timing signal” CK0 (FIG. 2, 34; ¶ [0061-0065]). The appropriate delay amount is selected via “first internal signal” STAGE NUMBER ADJUSTMENT SIGNAL (FIG. 4) as received from the training circuit (FIG. 2, 34) or control circuit (FIG. 2, 33) as taught in ¶ [0054].).
12. Claims 13 and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Fujisawa (US 20110058443 A1) in view of Lee, et al (20110258475), hereinafter Lee, and further in view of Takada (US 20220301607 A1).
Regarding independent claim 13, Fujisawa teaches an apparatus comprising:
a memory cell array (FIG. 1, 70);
a data bus (FIG. 1, DQ, DQS) configured to convey a write data (FIG. 1, DQ; ¶ [0037]) to the memory cell array;
a data transfer circuit (FIG. 1, 84) configured to transfer the write data to the data bus (¶ [0037]).
Fujisawa does not teach a timing control circuit configured to activate the data transfer circuit after a first delay time elapsed after activating a timing signal according to a first operation mode, and activate the data transfer circuit after a second delay time different from the first delay time elapsed after activating the timing signal according to a second operation mode.
Lee teaches a timing control circuit (FIG. 5, Delay 507) configured to activate the data transfer circuit (FIG. 5, Capture_Clk 506 output by Delay 507 “activates” flip-flops 505) after a first delay time (the delay of FIG. 5, 507) elapsed after activating a timing signal (FIG. 5, Core_Clk 508).
Lee does not teach the timing control circuit is configured to activate the data transfer circuit after a first delay time elapsed after activating a timing signal according to a first operation mode.
It appears from ¶ [0014-0015] of the present application that the “operation mode” in view is indicated by “mode signal MR13,” which determines the amount of delay in the timing control circuit. In this sense, “mode signal MR13” is analogous to Lee’s delay control signal (FIG. 10, 1004). However, Lee does not disclose the operation of control signal 1004.
Takada teaches a timing control circuit (FIG. 2, DL2) configured to activate the data transfer circuit (FIG. 2, SAMPLER 31) based on a control signal (FIG. 4, STAGE NUMBER ADJUSTMENT SIGNAL) analogous to Applicant’s “mode signal MR13” in operation (compare Takada FIG. 4 to FIGS. 3A and 3B of the present application). The STAGE NUMBER ADJUSTMENT SIGNAL is determined by a training circuit (FIG. 2, 34) or control circuit (FIG. 2, 33) and may change with frequency (¶ [0064-0065]), and represents a number of delay stages used (see FIG. 4, 3-1..3-K), each number of delay stages used represents a different “operation mode.”
Therefore, Fujisawa as modified by Lee and Takada teaches after a first delay time elapsed after activating a timing signal according to a first operation mode (a first number of delay stages selected via Takada’s multiplexer 4 in FIG. 4 (see ¶ [0068-0069]), indicated by the STAGE NUMBER ADJUSTMENT SIGNAL), and activate the data transfer circuit after a second delay time different from the first delay time elapsed after activating the timing signal according to a second operation mode (a second number of delay stages different from the first and selected via multiplexer 4 in FIG. 4, indicated by the STAGE NUMBER ADJUSTMENT SIGNAL).
Note Fujisawa as modified by Lee and Takada substitutes the programmable delay circuit of Takada (FIG. 4) and its affiliated control circuits (e.g., FIG. 4, training circuit 34, control circuit 33) for the programmable delay circuit of Lee (FIG. 5, 507). See Figure A.
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Lee into the device of Fujisawa to include a programmable delay element to create the capture clock for the data transfer circuit. The ordinary artisan would have been motivated to modify Fujisawa in the above manner for the purpose of minimizing the effects of system delays and increasing both device and system yield (Lee, Abstract).
Because the delay circuits of both Lee and Takada delay flip-flop clocks used to transfer write data (Lee FIG. 5, programmable delay element 507 and flip-flops 505 transferring data dq; Takada FIG. 2, programmable delay element DL2 and flip-flops FF0 transferring data DQ’), it would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the programmable delay element of Takada with the programmable delay element of Lee to yield predictable results. See MPEP § 2143(I)(B).
Regarding claim 15, Fujisawa as modified by Lee and Takada teaches the limitations of claim 13.
Fujisawa further teaches a timing domain of the timing signal is controlled based on a clock signal supplied from outside (FIG. 2, timing signal CK is received from “outside” via terminal 11a and is the basis for internal clock ICLK supplied to various internal circuits except those that form a data output system (¶[0027])).
Regarding claim 16, Fujisawa as modified by Lee and Takada teaches the limitations of claim 15.
Takada further teaches wherein the first operation mode is selected when the clock signal has a first frequency, and
wherein the second operation mode is selected when the clock signal has a second frequency different from the first frequency (Takada teaches in Equation 6 in the discussion of the training process in ¶ [0063-0065], there is an inverse relationship between clock frequency and delay. This means frequency is indirectly indicated by the number of delay stages represented by the STAGE NUMBER ADJUSTMENT SIGNAL; therefore, a first number of delay stages (first operation mode) used with a first clock frequency will be different from a second number of delay stages (second operation mode) used with a second clock frequency.).
Regarding claim 17, Fujisawa as modified by Lee and Takada teaches the limitations of claim 16.
Takada further teaches wherein the first frequency is higher than the second frequency, and
wherein the first delay time is shorter than the second delay time (in Equation 6 in the discussion of the training process in ¶ [0063-0065], there is an inverse relationship between clock frequency and delay; therefore, a lower clock frequency (here, the “second frequency”) accompanies a longer delay and a higher clock frequency (here, the “first frequency”) accompanies a shorter delay).
Regarding independent claim 18, Fujisawa teaches an apparatus comprising:
a memory cell array (FIG. 1, 70);
a control logic circuit (FIG. 1, 22) configured to generate a first timing signal (FIG. 1, ICLK; ¶ [0027]) based on a clock signal (FIG. 1, CK) in a data write operation (¶ [0037]); and
a data bus (FIG. 1, DQ, DQS) configured to convey a write data to the memory cell array (¶ [0037]).
Fujisawa does not teach a variable delay circuit configured to generate a second timing signal by delaying the first timing signal.
Lee teaches a variable delay circuit (FIG. 5, 507; ¶ [0039] teaches delay element 507 is programmable) configured to generate a second timing signal (FIG. 5, Capture_Clk 506) by delaying the first timing signal (FIG. 5, Core_Clk 508, analogous to the CK domain of Fujisawa).
Note Fujisawa as modified by Lee (see Figure B) substitutes the PHY circuit of Lee (Lee FIG. 5, flip-flops 502 and Delay 504, clocked by dqs) for the data input circuit of Fujisawa (Fujisawa FIG. 1, 82, clocked by DQS), and substitutes the data transfer circuit of Lee (Lee FIG. 5, flip-flops 505 and Delay 507) for the FIFO circuit of Fujisawa (Fujisawa FIG. 1, 84).
Fujisawa does not teach a delay amount of the variable delay circuit when the clock signal has a first frequency is shorter than a delay amount of the variable delay circuit when the clock signal has a second frequency lower than the first frequency.
Takada teaches a delay amount of the variable delay circuit when the clock signal has a first frequency is shorter than a delay amount of the variable delay circuit when the clock signal has a second frequency lower than the first frequency (in Equation 6 in the discussion of the training process in ¶ [0063-0065], there is an inverse relationship between clock frequency and delay; therefore, a lower clock frequency (here, the “second frequency”) accompanies a longer delay and a higher clock frequency (here, the “first frequency”) accompanies a shorter delay).
Note Fujisawa as modified by Lee and Takada substitutes the programmable delay circuit of Takada (FIG. 4) and its affiliated control circuits (e.g., FIG. 4, training circuit 34, control circuit 33) for the programmable delay circuit of Lee (FIG. 5, 507). See Figure A.
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Lee into the device of Fujisawa to include a programmable delay element to create the capture clock for the data transfer circuit. The ordinary artisan would have been motivated to modify Fujisawa in the above manner for the purpose of minimizing the effects of system delays and increasing both device and system yield (Lee, Abstract).
Because the delay circuits of both Lee and Takada delay flip-flop clocks used to transfer write data (Lee FIG. 5, programmable delay element 507 and flip-flops 505 transferring data dq; Takada FIG. 2, programmable delay element DL2 and flip-flops FF0 transferring data DQ’), it would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the programmable delay element of Takada with the programmable delay element of Lee to yield predictable results. See MPEP § 2143(I)(B).
Regarding claim 19, Fujisawa as modified by Lee and Takada teaches the limitations of claim 18.
Takada further teaches a delay amount of the variable delay circuit when the clock signal has the second frequency is shorter than a delay amount of the variable delay circuit when the clock signal has a third frequency lower than the second frequency (in Equation 6 in the discussion of the training process in ¶ [0063-0065], there is an inverse relationship between clock frequency and delay; therefore, a lower clock frequency (here, the “third frequency”) accompanies a longer delay and a higher clock frequency (here, the “second frequency”) accompanies a shorter delay).
13. Claims 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Fujisawa (US 20110058443 A1) in view of Lee, et al (20110258475), hereinafter Lee, further in view of Takada (US 20220301607 A1), and further in view of Oh, et al (US 20190172512 A1), hereinafter Oh.
Regarding claim 14, Fujisawa as modified by Lee and Takada teaches the limitations of claim 13.
Fujisawa further teaches a mode register circuit (FIG. 2, 56) configured to select one of a plurality of operation modes (¶ [0029]) including first and second operation modes (¶ [0029] teaches “DLL on” and “DLL off” modes). However, these modes do not obviously reflect operating frequency, and Fujisawa’s delay (DLL) circuit (FIG. 1, 23) is not analogous to that of the present application.
Therefore, Fujisawa does not teach “the first and second operation modes” as taught in claim 13.
Oh teaches a mode register circuit (FIG. 3, 222; ¶ [0071]) configured to select one of a plurality of operation modes (¶ [0071] teaches an access mode and strobe mode), the plurality of operation modes related to the operating frequency (¶ [0008]; claim 2).
Takada further teaches the operating frequency is related to delay (Equation 6, ¶ [0063-0065]).
Therefore, Fujisawa as modified by Lee, Takada, and Oh teaches a mode register circuit configured to select one of a plurality of operation modes including the first and second operation modes.
Regarding claim 20, Fujisawa as modified by Lee and Takada teaches the limitations of claim 18.
Fujisawa further teaches a mode register circuit (FIG. 2, 56) configured to store a mode signal (FIG. 1, M).
Fujisawa does not teach the mode signal relates to a frequency of the clock signal.
Oh teaches a mode register circuit (FIG. 3, 222; ¶ [0071]) configured to select one of a plurality of operation modes (¶ [0071] teaches an access mode and strobe mode), the plurality of operation modes related to the operating frequency (¶ [0008]; claim 2) and indicated by mode signal SMS (FIG. 3; ¶ [0071]).
Takada further teaches the operating frequency is related to delay (Equation 6, ¶ [0063-0065]), the delay selected by internal signal STAGE NUMBER ADJUSTMENT SIGNAL (FIG. 4, STAGE NUMBER ADJUSTMENT SIGNAL selects the delay via multiplexer 4) and representing the “operation mode” (see the relationship between frequency, delay, and the mode signal/register in ¶ [0014] of the present application).
Therefore, Fujisawa as modified by Lee, Takada, and Oh teaches a mode register circuit configured to store a mode signal that relates to a frequency of the clock signal,
wherein a delay amount of the variable delay circuit is changed based on the mode signal.
Regarding claims 14 and 20, it would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Oh into the method of Lee to include relating the internal mode signal to a frequency of clock/timing signal (Oh, claim 2). The ordinary artisan would have been motivated to modify Lee in the above manner for the purpose of determining whether to generate a strobe signal based on a frequency of the main clock signal (Oh ¶ [0008]).
Conclusion
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827