DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. This office action is in response to the Amendment filed on April 30, 2026.
Claims 1, 3, 10, 13, 16, and 18 are amended. Claims 2 and 15 are canceled. No claims are added.
Applicant' s amendments to claim 10 are acknowledged and objections to claim 10 set forth in the previous Office Action are withdrawn.
Response to Arguments
3. Applicant’s arguments, see pages 6-7, filed April 30, 2026, with respect to claim 1 have been fully considered and are persuasive. The rejection of claim 1 under 35 USC § 102 has been withdrawn.
Applicant asserts that in Takada (US 20220301607 A1), the delay amount of the unit delay elements 5-1 to 5-M is not changed by a frequency of the delay strobe signal CK0, which is mapped to the recited “first timing signal” in the previous Office Action and therefore, the delay amount of the unit delay elements 1-N and 3-K is also not changed by the frequency of the delay strobe signal CK0 and accordingly, Takada does not teach or suggest “wherein a delay amount of the timing control circuit is changed based on a frequency of the first timing signal” as recited in amended claim 1.
Examiner notes that while Takada Equation 6 describes a relationship between the frequency of the replica oscillation circuit and delay, Takada does not explicitly teach frequency determines delay. In addition, Takada does not explicitly specify the replica oscillation circuit has the same frequency as CK0. Therefore, Applicant’s arguments are persuasive and the rejection of claim 1 is withdrawn in light of the amendments.
4. Applicant’s arguments, see pages 8-9, filed April 30, 2026, with respect to claim 13 have been fully considered and are persuasive. The rejection of claim 13 under 35 USC § 103 has been withdrawn.
Applicant submits, and Examiner agrees, as recited in amended claim 13, the “timing signal” is generated by a control logic circuit “at a predetermined timing of a timing domain that is controlled based on the clock signal in a write operation,” but Lee's (US20110258475A1) CoreClk 508 is not derived from a clock signal provided in a write operation (i.e., the context is the operation of the read data path in response to read commands). Therefore, Applicant’s arguments are persuasive and the rejection of claim 13 is withdrawn in light of the amendments.
5. Applicant’s arguments, see pages 9-10, filed April 30, 2026, with respect to claim 13 have been fully considered but are not persuasive.
Applicant asserts Lee's delay element 507 is not a standalone component that can be removed from Lee's architecture and inserted into Fujisawa's (US 20110058443 A1) write path, but the amount of delay assigned to programmable delay element 507 is controlled by a self-configuring logic circuit (SCL) contained within the memory controller. However, the modification used in the previous Office Action is concerned only with a delay element generating a capture clock. How much delay is provided by the element and how that delay amount is determined is not important to the modification.
6. Applicant’s arguments, see page 10, filed April 30, 2026, with respect to claim 18 have been fully considered and are persuasive. The rejection of claim 18 under 35 USC § 103 has been withdrawn.
Applicant submits, and Examiner agrees, because claim 18 has been amended to incorporate amendments analogous to those discussed above with respect to amended claim 1, the cited references do not teach, for example, “wherein a delay amount of the variable delay circuit is changed based on a frequency of the clock signal” as recited in amended claim 18. Therefore, Applicant’s arguments are persuasive and the rejection of claim 18 is withdrawn in light of the amendments.
Claim Rejections - 35 USC § 112
7. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
8. Claims 1, 3-12, and 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “wherein the timing control circuit includes a variable delay to add an amount of delay to a first control signal to generate a second control signal” in lines 8-9, and “wherein a delay amount of the timing control circuit is changed based on a frequency of the first timing signal” in lines 10-11.
It is unclear if “a variable delay” in line 8 refers to a circuit or a quantity of time. It is also unclear if “a delay amount of the timing control circuit” in line 10 refers to the “a variable delay” included in the timing control circuit in lines 8-9, or if it refers to “an amount of delay” in lines 8-9. Claims 3-12 depend on claim 1.
Claim 12 recites the limitation “the first internal signal relates to a frequency of the first timing signal,” which is indefinite. For the purpose of this action, the limitation “the first internal signal relates to a frequency of the first timing signal” shall be interpreted as “the first internal signal relates to [[a]] the frequency of the first timing signal,” which finds antecedent basis in claim 1, lines 10-11.
Claim 19 recites the limitation “wherein a delay amount of the variable delay circuit when the clock signal has the second frequency,” which is indefinite. For the purpose of this action, the limitation “wherein a delay amount of the variable delay circuit when the clock signal has the second frequency” shall be interpreted as “wherein [[a]] the delay amount of the variable delay circuit when the clock signal has the second frequency,” which finds antecedent basis in claim 18, lines 13-14.
Claim 20 recites the limitation “a mode signal that relates to a frequency of the clock signal, wherein a delay amount of the variable delay circuit is changed based on the mode signal,” which is indefinite. For the purpose of this action, the limitation “a mode signal that relates to a frequency of the clock signal, wherein a delay amount of the variable delay circuit is changed based on the mode signal” shall be interpreted as “a mode signal that relates to [[a]] the frequency of the clock signal, wherein [[a]] the delay amount of the variable delay circuit is changed based on the mode signal,” which finds antecedent basis in claim 18, lines 10-11.
Allowable Subject Matter
9. Claim 13-14 and 16-18 are allowed.
Claim 1 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claims 19-20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
10. The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 1, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein a delay amount of the timing control circuit is changed based on a frequency of the first timing signal. Claims 3-12 depend on claim 1.
Regarding claim 13, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of a timing control circuit configured to activate the data transfer circuit after a first delay time elapsed after activating the signal according to a first operation mode, and activate the data transfer circuit after a second delay time different from the first delay time elapsed after activating the timing signal according to a second operation mode. Claims 14 and 16-17 depend on claim 13.
Regarding claim 18, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein a delay amount of the timing control circuit is changed based on a frequency of the first timing signal. Claims 19-20 depend on claim 18.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMIR ZARABIAN can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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