Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following is in response to the communication filed 6/27/2024.
Claims 1-20 are currently pending.
Claims 1-20 have been examined.
Claim Objections
Claim 20 objected to because of the following informalities:
Claim 20 includes the preamble “The HBM of claim 19.” However, claim 19 which claim 20 depends on is a “A NAND stack.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-18 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the limitation "a second semiconductor die" on page 5 as part of . Previously on page 4 as part of a first CBA memory die there is “a second substrate”. It is unclear on if the this second semiconductor die is intended to be the same second semiconductor die or a new semiconductor. There is insufficient antecedent basis for this limitation in the claim.
For the purposes of examination the “second semiconductor die” in the second CBA memory die will be read separate semiconductor die (i.e. “fourth semiconductor die”.)
Furthermore, claim 11 also recites “fourth semiconductor die(s)” in “a second set of electrical connections within the third and fourth semiconductor dies electrically coupled to the second group of bump pads in the second major surface.” Dependent claims 15 and 17 also recite the “fourth semiconductor die.” There is insufficient antecedent basis for this limitation in the claim.
Claims 12-14, 16, and 18 are rejected based on their dependence to claim 11.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Vodrahalli et al. US 20210104495 A1 (hereinafter Vodrahalli).
The following annotated drawings will be used in discussion of claims 1-10:
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Regarding claim 1, Vodrahalli discloses:
A high bandwidth memory, ( [0038]a memory system in the semiconductor dies in wafer 100 and wafer 200) comprising:
a plurality of paired CMOS bonded array (CBA) memory dies, (Figs. 4-7 first semiconductor dies 102 and second semiconductor die 112) each paired CBA memory die of the plurality of paired CBA memory dies comprising:
a first CBA memory die, (annotated Fig. 2, CBA memory die 1) comprising:
a first semiconductor die, (Fig. 4, first semiconductor die 102_1) comprising:
a first memory array formed in a first face of the first semiconductor die, (memory array circuits 122 on semiconductor die 102_1) the first memory array having a first coefficient of thermal expansion, (The material would by necessity have a coefficient of thermal expansion as a material property.)
a first substrate next to the first memory array (dielectric substrate 124) and having a second coefficient of thermal expansion, (The material would by necessity have a coefficient of thermal expansion as a material property.)
a first group of bump pads formed in the first face of the first semiconductor die, and (bond pads 108)
a second semiconductor die, (Fig. 2, second semiconductor die 112_1 ) comprising:
a first CMOS logic circuit formed in the second semiconductor die, ( [0032], an integrated memory module may include logic circuits such as a CMOS logic circuit.)
a second substrate next to the first CMOS logic circuit, (dielectric substrate 134)
a second group of bump pads; and (bond pads 118)
a second CBA memory die, (annotated Fig.3, CBA memory die 2) comprising:
a third semiconductor die, (Fig. 5, third semiconductor die 102_2) comprising:
a second memory array formed in a second face of the second semiconductor die, (memory cell array 122 on semiconductor die 102_2) the second memory array having a third coefficient of thermal expansion, (The material would by necessity have a coefficient of thermal expansion as a material property.)
a third substrate next to the second memory array (dielectric substrate 124 on semiconductor die 102_2) and having a fourth coefficient of thermal expansion, (The dielectric substrate is made material that would have a specific coefficient of thermal expansion as part of the material property.)
a third group of bump pads formed in the second face of the second semiconductor die, and (bond pads 108 on third semiconductor 102_2)
a fourth semiconductor die, (Fig. 3, fourth semiconductor die 112_2 ) comprising:
a second CMOS logic circuit formed in the fourth semiconductor die, ( [0032], an integrated memory module may include logic circuits such as a CMOS logic circuit.)
a fourth substrate next to the first CMOS logic circuit, and (dielectric substrate 134 on fourth semiconductor die 112_2)
a fourth group of bump pads; (bond pads 118 on semiconductor die 112_2)
wherein the paired CBA memory die is configured to avoid warping by bonding the first and second CBA memory dies together first face to second face so that the first and third coefficients of thermal expansion balance each other out. (Fig. 7, [0065], using face-to-face mounting the active surfaces which in include the first semiconductor die 102 facing the second semiconductor die 112 the disparate coefficients of thermal expansion are balanced out.)
Regarding claim 2, Vodrahalli further discloses:
first and second CBA memory dies (CBA memory die 1 including first semiconductor die 102_1 and second semiconductor die 112_1) are bonded to each other face-to-face by coupling the first and second groups of bump pads to each other. ([0030], the pairs of dies are affied in a face to face manner.)
Regarding claim 3, Vodrahalli further discloses:
the first CBA memory die (CBA memory die 1) comprises a first set of electrical connections extending between major planar surfaces of the first CBA memory die, the first set of electrical connections comprising the first and second groups of bump pads. ([0042] and [0047], bond pads 108 and 118 are electrically connected to the circuits below.)
Regarding claim 4, Vodrahalli further discloses:
the first set of electrical connections further comprises a plurality of vias (Fig. 7, vias 128 and 138 in first and second semiconductor 102_1 and 112_1 ) connected between the first and second groups of bump pads. (bump pads 108 and 118 on first and second semiconductor dies 102_1 and 112_1) (See Fig. 7.)
Regarding claim 5, Vodrahalli further discloses:
the second CBA memory die (CBA memory die 2 including third semiconductor die 102_2 and fourth semiconductor die 112_2) comprises a second set of electrical connections extending between major planar surfaces of the second CBA memory die, the second set of electrical connections comprising the third and fourth groups of bump pads. ([0042] and [0047], bond pads 108 and 118 on semiconductor dies 102_2 and 112_2 are electrically connected to the circuits below.)
Regarding claim 6, Vodrahalli further discloses:
the second set of electrical connections further comprises a plurality of vias (Fig. 7, vias 128 and 138 in third and fourth semiconductor 102_1 and 112_1 ) connected between the third and fourth groups of bump pads. (bump pads 108 and 118 on third and fourth semiconductor dies 102_1 and 112_1) (See Fig. 7.)
Regarding claim 7, Vodrahalli further discloses:
the paired CBA memory die is further configured to avoid warping by bonding the first and second CBA memory dies together first face to second face so that the second and fourth coefficients of thermal expansion of the first and third substrates balance each other out. (Fig. 7, [0065], using face-to-face mounting the active surfaces which in include the first semiconductor die 102_1 facing the second semiconductor die 112_1 and the third semiconductor die 102_2 facing the fourth semiconductor die 112_2 the disparate coefficients of thermal expansion are balanced out.)
Regarding claim 8, Vodrahalli further discloses:
the first CMOS logic circuit comprises a fifth coefficient of thermal expansion (third semiconductor die 102_2 having a CMOS logic circuit would by necessity have a coefficient of thermal expansion.) and the second CMOS logic circuit comprises a sixth coefficient of thermal expansion, (fourth semiconductor die 112_2 having a CMOS logic circuit would by necessity have a coefficient of thermal expansion.) wherein the paired CBA memory die is further configured to avoid warping by bonding the first and second CBA memory dies together first face to second face so that the fifth and sixth coefficients of thermal expansion balance each other out. (Fig. 7, [0065], using face-to-face mounting the active surfaces which in include the first semiconductor die 102_1 facing the second semiconductor die 112_1 and the third semiconductor die 102_2 facing the fourth semiconductor die 112_2 the disparate coefficients of thermal expansion are balanced out.)
Regarding claim 9, Vodrahalli further discloses:
the second substrate comprises a seventh coefficient of thermal expansion (dielectric substrate 134 on the second semiconductor die 112_2 would by necessity have a coefficient of thermal expansion as a material property) and the fourth substrate comprises an eighth coefficient of thermal expansion, (dielectric substrate 134 on the fourth semiconductor die 102_2 would by necessity have a coefficient of thermal expansion as a material property) wherein the paired CBA memory die is further configured to avoid warping by bonding the first and second CBA memory dies together first face to second face so that the seventh and eighth coefficients of thermal expansion balance each other out. (Fig. 7, [0065], using face-to-face mounting the active surfaces which in include the first semiconductor die 102_1 facing the second semiconductor die 112_1 and the third semiconductor die 102_2 facing the fourth semiconductor die 112_2 the disparate coefficients of thermal expansion are balanced out.)
The following annotated figure will be used for discussion of claims 11-18:
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Regarding claim 11, Vodrahalli discloses:
A paired CMOS bonded array (CBA) memory die, ( Fig. 1, [0038]a memory system in the semiconductor dies in wafer 100 and wafer 200 which are affixed together) comprising:
a first CBA memory die, (annotated Fig. 2, CBA memory die 1) comprising:
a first major surface, (major planar surface 104)
a first group of bump pads formed in the first major surface, (Fig. 2, bond pads 108 in 102_1 and 102_2)
a first semiconductor die, (Fig. 2 and 4, semiconductor die 102_1) comprising:
a first memory array (memory array circuits 122) having a first coefficient of thermal expansion, (The material would by necessity have a coefficient of thermal expansion as a material property.)
a first substrate (dielectric substrate 124 on semiconductor die 102_1) next to the first memory array (See Fig. 4) and having a second coefficient of thermal expansion, and (The material would by necessity have a coefficient of thermal expansion as a material property.)
a second semiconductor die, (Fig. 2 and 4, semiconductor die 102_2)comprising:
a first CMOS logic circuit having a third coefficient of thermal expansion, ([0032], an integrated memory module may include logic circuits such as a CMOS logic circuit. The CMOS logic circuit would have by a coefficient of thermal expansion as part of the material properties.))
a second substrate next to the first CMOS logic circuit (dielectric substrate 124 on semiconductor die 102_2) and having a fourth coefficient of thermal expansion, and (The material would by necessity have a coefficient of thermal expansion.)
a first set of electrical connections (bond pads 108) within the first and second semiconductor dies electrically coupled to the first group of bump pads in the first major surface; and (See Fig. 2 and 4)
a second CBA memory die, (annotated Fig. 3, CBA memory die 2) comprising:
a second major surface, (major surface 114)
a second group of bump pads formed in the second major surface, (Fig. 3, bond pads 108 in 112_1 and 112_2)
a third semiconductor die, (Fig. 3 and 5, semiconductor die 112_1) comprising:
a second memory array (memory array circuit 132) having a fifth coefficient of thermal expansion, (The material would by necessity have a coefficient of thermal expansion.)
a third substrate (dielectric substrate 134 on semiconductor die 112_1) next to the second memory array (See Fig. 5) and having a sixth coefficient of thermal expansion, and (The material would by necessity have a coefficient of thermal expansion as a material property.)
a fourth semiconductor die, (Fig. 3 and 5, semiconductor die 112_2) comprising:
a second CMOS logic circuit having a seventh coefficient of thermal expansion, ([0032], an integrated memory module may include logic circuits such as a CMOS logic circuit. The CMOS logic circuit would have by a coefficient of thermal expansion as part of the material properties.)
a fourth substrate next to the second CMOS logic circuit (dielectric substrate 134 on semiconductor die 102_2) and having an eighth coefficient of thermal expansion, and (The material would by necessity have a coefficient of thermal expansion.)
a second set of electrical connections (bond pads 118) within the third and fourth semiconductor dies electrically coupled to the second group of bump pads in the second major surface; (See Fig. 3 and 5)
wherein the paired CBA memory die is configured to avoid warping by bonding the first and second CBA memory dies together first major surface to second major surface so that the coefficients of thermal expansion in the first and second CBA memory dies balance each other out. (Fig. 7, [0065], using face-to-face mounting the active surfaces which in include the CBA memory die 1 facing CBA memory die 2 the disparate coefficients of thermal expansion are balanced out.)
Regarding claim 12, Vodrahalli further discloses:
the first major surface is formed in the first semiconductor die, (Fig. 2, major planar surface 104 is part of the semiconductor die 102_1) and the second major surface is formed in the third semiconductor die. (Fig. 3, major planar surface 114 is part of the semiconductor die 112_1)
Regarding claim 13, Vodrahalli further discloses:
the first set of electrical connections (metal interconnects 126 on semiconductor die 102_1) electrically couple the first memory array (memory array circuits 122 on semiconductor die 102_1) to the first group of bump pads, ([0042] the bond pads 108 on semiconductor die 102_1 are electrically connected) and the first set of electrical connections(metal interconnects 126 on semiconductor die 102_2) electrically couple the first CMOS logic circuits (CMOS logic circuits on semiconductor die 102_2) to the first group of bump pads through the first semiconductor die. ([0042] the bond pads 108 on semiconductor die 102_2 are electrically connected)
Regarding claim 14, Vodrahalli further discloses:
the second set of electrical connections (metal interconnects 136 on semiconductor die 112_1) electrically couple the second memory array(memory array circuits 132 on semiconductor die 112_1) to the second group of bump pads, ([0042] the bond pads 118 on semiconductor die 112_1 are electrically connected) and the second set of electrical connections (metal interconnects 136 on semiconductor die 112_2) electrically couple the second CMOS logic circuits (CMOS logic circuits on semiconductor die 112_2) to the second group of bump pads through the third semiconductor die. ([0042] the bond pads 118 on semiconductor die 112_2 are electrically connected)
Regarding claim 15, Vodrahalli further discloses:
the first major surface (major planar surface 104) is formed in the second semiconductor die, (semiconductor die 102_2) and the second major surface (major planar surface 114) is formed in the fourth semiconductor die. (semiconductor die 112_2)
Regarding claim 16, Vodrahalli further discloses:
the first set of electrical connections (metal interconnects 126 on semiconductor die 102_2) electrically couple the first CMOS logic circuits (CMOS logic circuits on semiconductor die 102_2) to the first group of bump pads, ([0042] the bond pads 118 on semiconductor die 102_1 are electrically connected) and the first set of electrical connections (metal interconnects 126 on semiconductor die 102_2) electrically couple the first memory array(memory array circuits 122 on semiconductor die 102_1) to the first group of bump pads through the second semiconductor die. ([0042] the bond pads 108 on semiconductor die 102_2 are electrically connected)
Regarding claim 17, Vodrahalli further discloses:
the second set of electrical connections (metal interconnects 136 on semiconductor die 112_2) electrically couple the second CMOS logic circuits (CMOS logic circuits on semiconductor die 112_2) to the second group of bump pads, ([0042] the bond pads 118 on semiconductor die 112_2 are electrically connected) and the second set of electrical connections (metal interconnects 136 on semiconductor die 112_1) electrically couple the second memory array (memory array circuits 132 on semiconductor die 112_1) to the second group of bump pads through the fourth semiconductor die. ([0042] the bond pads 118 on semiconductor die 112_1 are electrically connected.)
Regarding claim 18, Vodrahalli further discloses:
the first set of electrical connections (metal interconnects 126) comprise a first set of vias (vias 128) physically connected to the first group of bump pads (bump pads 108) at the first surface. (See Fig. 4.)
Regarding claim 19, Vodrahalli discloses:
A NAND stack ( [0038]a memory system in the semiconductor dies in wafer 100 and wafer 200 including a NAND memory system), comprising:
a plurality of paired non-volatile memory dies, (Figs. 4-7 first semiconductor dies 102 and second semiconductor die 112) each paired non-volatile memory die of the plurality of paired non-volatile memory dies comprising:
a first semiconductor die, (Fig. 4, first semiconductor dies 102) comprising:
a first non-volatile memory formed in a first face of the first semiconductor die, (memory array circuits 122) the first non-volatile memory having a first coefficient of thermal expansion, (The material would by necessity have a coefficient of thermal expansion.)
a first substrate next to the first non-volatile memory (dielectric substrate 124) and having a second coefficient of thermal expansion, (The dielectric substrate is made material that would have a specific coefficient of thermal expansion.)
a first group of bump pads formed in the first face of the first semiconductor die, (bond pads 108) and
a second semiconductor die, (Fig. 5, second semiconductor dies 112 ) comprising:
a second non-volatile memory formed in a second face of the second semiconductor die, (memory cell array 132) the second non-volatile memory having a third coefficient of thermal expansion, (The material would by necessity have a coefficient of thermal expansion.)
a second substrate next to the second non-volatile memory (dielectric substrate 134) and having a fourth coefficient of thermal expansion, (The dielectric substrate is made material that would have a specific coefficient of thermal expansion.)
a second group of bump pads formed in the second face of the second semiconductor die; (bond pads 118)
wherein the paired non-volatile memory die is configured to avoid warping by bonding the first and second non-volatile memory dies together first face to second face so that the coefficients of thermal expansion in the first and second non-volatile memory dies balance each other out. (Fig. 7, [0065], using face-to-face mounting the active surfaces which in include the first semiconductor dies 102 facing the second semiconductor dies 112 the disparate coefficients of thermal expansion are balanced out.)
Regarding claim 20, Vodrahalli further discloses:
the plurality of paired non-volatile memory dies are bonded directly to each other using hybrid bonding.([0031], the wafers may be bonded by a hybrid boding process. )
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HEIM KIRIN GREWAL whose telephone number is (703)756-1515. The examiner can normally be reached Monday - Thursday 9:30 a.m. - 5:30 p.m. EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HEIM KIRIN GREWAL/ Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812
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