Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following is in response to the communication filed 6/27/2024.
Claims 1-20 are currently pending.
Claims 1-20 have been examined.
Prior to examination claims 21-32 were canceled.
Priority
The applicant' s claim for benefit of U.S. Provisional Application No. 63/549,857 filed on February 5, 2024 has been received and acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 6/27/2024 and 6/18/2025, are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the " the 1st source/drain region has a greater length than the 2nd source/drain region in a 2nd direction intersecting the 1st direction." must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 11-13, 17, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. US 20220037509 A1 (hereinafter Huang).
Regarding claim 1, Huang discloses:
A semiconductor device (Huang, [0013]) comprising:
a plurality of 1st channel layers (Fig. 10, semiconductor layer 215 including 215A-215D) arranged in a 1st direction; (See Fig. 10, stacked in the z-direction))
a 1st source/drain region (epitaxial source/drain features 260) on the plurality of 1st channel layers;
a 1st gate structure (gate electrode layer 284 and high-k dielectric layer 282) comprising a 1st inner gate structure (gate electrode layer 284) between two adjacent 1st channel layers among the plurality of 1st channel layers; (see Fig. 10, the gate electrode layer 284 is between the 215A and 215B) and
a 1st inner spacer (inner spacer 255A) between the 1st inner gate structure (gate electrode layer 284) and the 1st source/drain region,(source/drain features 260)
wherein a top surface of the 1st inner spacer (inner spacer 255A) is at a higher level than a top surface of the 1st inner gate structure, (See Fig. 10) and a bottom surface of the 1st inner spacer is at a lower level than a bottom surface of the 1st inner gate structure, (See Fig. 10) in the 1st direction.
Regarding claim 2, Huang further discloses:
each of the two adjacent 1st channel layers (semiconductor layers 215A and 215B) comprises a body structure (Fig. 6, length of semiconductor defined by LA and LB) and a fin structure which is formed at each lateral side of the body structure (Fig. 6, areas of the semiconductor layer 215A and 215B outside the body structure) and penetrates into the 1st source/drain region. (Fig. 10 , the fin structures of 215A and 215B penetrate into the source/drain 260.)
Regarding claim 3, Huang further discloses:
the body structure has a greater thickness than the fin structure in the 1st direction. (See Fig. 10.)
Regarding claim 4, Huang further discloses:
the 1st inner spacer is disposed between two vertically adjacent fin structures of the two adjacent 1st channel layers. (See Fig. 10)
Regarding claim 5, Huang further discloses:
the 1st source/drain region comprises p-type impurities. ([0042], the source/drain features 260 are doped with p-type dopants.)
Regarding claim 6, Huang further discloses:
the 1st inner spacer has a substantially rectangular shape. (see Fig. 10)
Regarding claim 11, Huang discloses:
A semiconductor device (Huang, [0013]) comprising:
a plurality of 1st channel layers (Fig. 10, semiconductor layer 215 including 215A-215D) arranged in a 1st direction; (Z-direction)
a 1st source/drain region on the plurality of 1st channel layers; (source/drain features 260)
a 1st gate structure (gate electrode layer 284 and high-k dielectric layer 282) comprising a 1st inner gate structure (gate electrode layer 284) between two adjacent 1st channel layers among the plurality of 1st channel layers; (see Fig. 10, the gate electrode layer 284 is between the 215A and 215B) and
a 1st inner spacer (inner spacer 255A) between the 1st inner gate structure (gate electrode layer 284) and the 1st source/drain region, (source/drain features 260)
wherein the 1st inner spacer (inner spacer 255A) has a greater thickness than the 1st inner gate structure in the 1st direction. (See Fig. 10, the inner spacer is thicker than the gate electrode layer 284.)
Regarding claim 12. Huang further discloses:
wherein the 1st source/drain region (source/drain feature 260) comprises a protrusion toward the 1st inner gate structure, (See Fig. 10)
wherein the protrusion of the 1st source/drain region contacts a side surface the 1st inner spacer, and (See Fig. 10, source/drain 260 contacts the side surface of the inner spacer 255.)
wherein the protrusion of the 1st source/drain region has a same thickness as the 1st inner spacer in the 1st direction. (See Fig. 10)
Regarding claim 13, Huang further discloses:
the 1st source/drain region comprises p-type impurities. ([0042], the source/drain features 260 are doped with p-type dopants.)
Regarding claim 17, Huang further discloses:
A semiconductor device (Huang, [0013]) comprising:
a 1st channel layer; (Fig. 10, semiconductor layer 215A)
a 1st source/drain region on the 1st channel layer; (source/drain features 260 on semiconductor 215A.)
a 1st gate structure (gate electrode layer 284 and high-k dielectric layer 282) comprising a plurality of 1st inner gate structures (gate electrode layer 284) surrounding the 1st channel layer; and ([0048]-[0049], the gate electrode is formed around the high-k dielectric layer 282 and the high-k dielectric layer wraps/surrounds the channel.)
a plurality of 1st inner spacers (inner spacers 255 including 255A-255D) at sides of the plurality of 1st inner gate structures, respectively, (See Fig. 10)
wherein the 1st channel layer (semiconductor layer 215A) penetrates into the 1st source/drain region (source/drain feature 260) through two adjacent 1st inner spacers (inner spacer 255A and 255B) among the plurality of 1st inner spacers. (See Fig. 10)
Regarding claim 18, Huang further discloses:
the 1st channel layer comprises a body structure(Fig. 6, length of semiconductor defined by LA) and a fin structure (Fig. 6, area of channel 215 that is outside LA) protruded from each lateral side of the body structure, and (See Fig. 6 and Fig. 10.)
wherein the body structure has a greater thickness than the fin structure in the 1st direction. (See Fig. 10. The channel body is thicker in the z-direction than the outside fins.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7-10, 14, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Huang as applied to claim 1 above, and further in view of Cheng et al. US 20230187551 A1 (hereinafter Cheng).
Regarding claim 7, Huang discloses all the elements of claim 1.
Huang does 1st channel layers (Huang, Fig. 10, semiconductor layer 215).
Huang does not appear to disclose:
a plurality of 2nd channel layers arranged in the 1st direction above or below the 1st channel layers;
a 2nd source/drain region on the plurality of 2nd channel layers;
a 2nd gate structure comprising a 2nd inner gate structure between two adjacent 2nd channel layers among the plurality of 2nd channel layers; and
a 2nd inner spacer between the 2nd inner gate structure and the 2nd source/drain region,
wherein a top surface and a bottom surface of the 2nd inner spacer are at same levels as a top surface and a bottom surface of the 2nd inner gate structure, respectively, in the 1st direction.
Cheng, which discloses a stacked complementary transistor structure (Cheng, Abstract), discloses:
a plurality of 2nd channel layers (Fig. 1, channel layers 112 and 114) arranged in the 1st direction (z-direction) above or below the 1st channel layers; (channel layer 122 and 124) (See Fig. 1)
a 2nd source/drain region (source/drain elements 160-1 and 160-2) on the plurality of 2nd channel layers; (channel layers 112 and 114)
a 2nd gate structure ([0091], metal gate 180 which includes a high-k gate dielectric and metal gate electrode layer.) comprising a 2nd inner gate structure between two adjacent 2nd channel layers among the plurality of 2nd channel layers; (Fig. 1, [0091], metal gate electrode would be between channel layers 112 and 114.) and
a 2nd inner spacer (sidewall spacers 136) between the 2nd inner gate structure and the 2nd source/drain region, (See Fig. 1)
wherein a top surface and a bottom surface of the 2nd inner spacer are at same levels as a top surface and a bottom surface of the 2nd inner gate structure, respectively, in the 1st direction. (See Fig. 1)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Huang to have a plurality of 2nd channel layers arranged in the 1st direction above or below the 1st channel layers, a 2nd source/drain region on the plurality of 2nd channel layers, a 2nd gate structure comprising a 2nd inner gate structure between two adjacent 2nd channel layers among the plurality of 2nd channel layers, and a 2nd inner spacer between the 2nd inner gate structure and the 2nd source/drain region, wherein a top surface and a bottom surface of the 2nd inner spacer are at same levels as a top surface and a bottom surface of the 2nd inner gate structure, respectively, in the 1st direction as taught by Cheng for purposes of increasing the transistor density by stacking PFET and NFET devices. (Cheng, [0002].)
Regarding claim 8, Huang and Cheng disclose all the elements of claim 7.
Cheng further discloses:
the 2nd inner spacer has a different shape than the 1st inner spacer. (Fig. 1, sidewall spacers being shown having square a shape which is different from the polygon shape of the inner spacers of Huang Fig. 10.)
Regarding claim 9, Huang and Cheng disclose all the elements of claim 7.
Heng discloses that the 1st inner spacer (inner spacer 255) is thicker than the inner gate. Whereas Cheng shows that that the 2nd inner spacer (sidewall spacer 136 is the same height as the metal gate 180.) Therefore the combination of Huang and Cheng disclose the 1st inner spacer is thicker than the 2nd inner spacer in the 1st direction.
Regarding claim 10, Huang and Cheng disclose all the elements of claim 7.
Huang discloses:
the 1st source/drain region comprises p-type impurities, ([0042], the source/drain features 260 are doped with p-type dopants.)
Cheng further discloses:
the 2nd source/drain region comprises n-type impurities. ([0080], source/drain elements 160-1 and 160-2 include N-type dopants including phosphorus or arsenic.)
Regarding claim 14, Huang discloses all the elements of claim 11.
Huang does 1st channel layers (Huang, Fig. 10, semiconductor layer 215).
Huang does not appear to disclose:
a plurality of 2nd channel layers arranged in the 1st direction above or below the 1st channel layers;
a 2nd source/drain region on the plurality of 2nd channel layers;
a 2nd gate structure comprising a 2nd inner gate structure between two adjacent 2nd channel layers among the plurality of 2nd channel layers; and
a 2nd inner spacer between the 2nd inner gate structure and the 2nd source/drain region,
wherein the 2nd inner spacer has a same thickness as the 2nd inner gate structure in the 1st direction.
Cheng, which discloses a stacked complementary transistor structure (Cheng, Abstract), discloses:
a plurality of 2nd channel layers (Fig. 1, channel layers 112 and 114) arranged in the 1st direction (z-direction) above or below the 1st channel layers; (channel layer 122 and 124) (See Fig. 1)
a 2nd source/drain region (source/drain elements 160-1 and 160-2) on the plurality of 2nd channel layers; (channel layers 112 and 114)
a 2nd gate structure ([0091], metal gate 180 which includes a high-k gate dielectric and metal gate electrode layer.) comprising a 2nd inner gate structure between two adjacent 2nd channel layers among the plurality of 2nd channel layers; (Fig. 1, [0091], metal gate electrode would be between channel layers 112 and 114.) and
a 2nd inner spacer (sidewall spacers 136) between the 2nd inner gate structure and the 2nd source/drain region, (See Fig. 1)
wherein the 2nd inner spacer has a same thickness as the 2nd inner gate structure in the 1st direction. (See Fig. 1)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Huang to have a plurality of 2nd channel layers arranged in the 1st direction above or below the 1st channel layers, a 2nd source/drain region on the plurality of 2nd channel layers, a 2nd gate structure comprising a 2nd inner gate structure between two adjacent 2nd channel layers among the plurality of 2nd channel layers, and a 2nd inner spacer between the 2nd inner gate structure and the 2nd source/drain region, wherein the 2nd inner spacer has a same thickness as the 2nd inner gate structure in the 1st direction as taught by Cheng for purposes of increasing the transistor density by stacking PFET and NFET devices. (Cheng, [0002].)
Regarding claim 19, Huang discloses all the elements of claim 17.
Huang does 1st channel layers (Huang, Fig. 10, semiconductor layer 215).
Huang does not appear to disclose:
a 2nd channel layer;
a 2nd source/drain region on the 2nd channel layer;
a 2nd gate structure comprising a 2nd inner gate surrounding the 2nd channel layers; and
a plurality of 2nd inner spacers at sides of the plurality of 2nd inner gate structures, respectively,
wherein the 2nd channel layer has a different shape than the 1st channel layer.
Cheng, which discloses a stacked complementary transistor structure (Cheng, Abstract), discloses:
a 2nd channel layer; (Fig. 1, channel layer 112)
a 2nd source/drain region on the 2nd channel layer; (source/drain element 160-1)
a 2nd gate structure comprising a 2nd inner gate surrounding the 2nd channel layers; and ([0091], metal gate 180 which includes a high-k gate dielectric and metal gate electrode layer.)
a plurality of 2nd inner spacers (sidewalls spacers 136) at sides of the plurality of 2nd inner gate structures (metal gate 180), respectively,
wherein the 2nd channel layer (See sidewall spacer 136) has a different shape than the 1st channel layer. (See Fig. 1.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Huang to have a 2nd channel layer, a 2nd source/drain region on the 2nd channel layer, a 2nd gate structure comprising a 2nd inner gate surrounding the 2nd channel layers, and a plurality of 2nd inner spacers at sides of the plurality of 2nd inner gate structures, respectively, wherein the 2nd channel layer has a different shape than the 1st channel layer as taught by Cheng for purposes of increasing the transistor density by stacking PFET and NFET devices. (Cheng, [0002].)
Regarding claim 20, Huang and Cheng disclose all the element of claim 19.
Huang further discloses:
the 1st channel layer (semiconductor layer 215) has a thickness in the 1st direction varying (z-direction) along a 2nd direction (y-direction) intersecting the 1st direction, and (See Fig. 10.)
Cheng further discloses:
wherein the 2nd channel layer (channel layer 112) has a uniform thickness in the 1st direction (z-direction) along the 2nd direction (x-direction). (See Fig. 1.)
Allowable Subject Matter
Claims 15 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 15, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, a semiconductor device comprising “the 1st source/drain region has a greater length than the 2nd source/drain region in a 2nd direction intersecting the 1st direction."
Regarding claim 16, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, a semiconductor device comprising "the 1st inner spacer has a smaller length than the 2nd inner spacer in a 2nd direction intersecting the 1st direction."
Prior Art Considered Pertinent
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Dewey et al. US 20200335501 A1 – The top source/drain region is has a smaller length than the bottom source/drain region.
Xie et al. US 20230085628 A1 (hereinafter Xie). – The top source/drain region has a smaller length than the bottom source/drain region.
Min et al. US 11715803 B2 – Channel 208 at the bottom of Fig. 19 has fins and the channels above it do not have fins.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HEIM KIRIN GREWAL whose telephone number is (703)756-1515. The examiner can normally be reached Monday - Thursday 9:30 a.m. - 5:30 p.m. EST.
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/HEIM KIRIN GREWAL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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