DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Application filed June 27, 2024.
Claims 1-20 are pending. Claims 1, 13 and 20 are independent.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on June 27, 2024. This IDS has been considered.
Drawings
The drawings are objected to because:
Figures 1A-3B should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g).
Applicant’s Figures 1A-3B are identical to U.S. 2020/0342926 Figures 1A-3B.
Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mantegazza (U.S. 11,087,854).
Regarding independent claim 1, Mantegazza discloses an apparatus (Fig. 4) comprising:
a memory cell (Fig. 4: 402) comprising a magnetic memory element (see col. 14, ll. 1-23) coupled in series with a selector element (Fig. 4: 421), the memory cell comprising a first terminal coupled to a word line driver circuit (Fig. 4: circuitry that apply signal to the gate of 421 (not shown in Figures)) and a second terminal coupled to a bit line driver circuit (Fig. 4: circuitry that apply signal to the gate of 419 (not shown in Figures)); and
an amplifier circuit (Fig. 415/431) comprising an input terminal coupled to the bit line driver circuit (Fig. 4: input terminals of 415/431 electrically coupled to the circuitry that apply signal to transistors 406, 417 and 419 (not shown in Figures)), and an output terminal coupled to a current source configured to conduct a read current (Fig. 4: output terminals of 415 and 431 electrically coupled to 404, 411/413 and read-reference-current),
wherein the amplifier circuit is configured to amplify a voltage that is based on a voltage across the memory cell (see col. 7, ll. 40-63).
Regarding claim 2, Mantegazza discloses wherein the amplifier circuit comprises a common gate amplifier (Fig. 4: 415/432).
Regarding claim 3, Mantegazza discloses wherein the amplifier circuit comprises a transistor comprising a first terminal coupled to the output terminal of the amplifier circuit (Fig. 4: gate of 444 coupled to the output terminal of 432), a second terminal coupled to the input terminal of the amplifier circuit (Fig. 4: source/drain terminal electrically coupled to an input of 432 through 442), and a third terminal coupled to a power supply voltage (Fig. 4: source/drain terminal of 444 electrically coupled to VNN Supply through 404 and 405).
Regarding claim 4, Mantegazza discloses wherein the amplifier circuit comprises a transistor comprising a drain terminal comprising the output terminal of the amplifier circuit (Fig. 4: drain terminal of 444 coupled to 405), a source terminal comprising the input terminal of the amplifier circuit (Fig. 4: source terminal electrically coupled to + sign of 432 through 442)), and a gate terminal coupled to a power supply voltage (Fig. 4: gate terminal of 444 coupled to the output supply by 432).
Regarding claim 5, Mantegazza discloses wherein the amplifier circuit comprises a p-channel transistor configured to operate in a saturation region of operation (Fig. 4: 442).
Regarding claim 6, Mantegazza discloses wherein the current source comprises a current mirror (Fig. 4: 411/413).
Regarding claim 7, Mantegazza discloses a sense amplifier circuit comprising an input terminal coupled to the output terminal of the amplifier circuit (Fig. 4: an input terminal of 432 is electrically coupled to a source/drain terminal of 444).
Regarding claim 8, Mantegazza discloses wherein the sense amplifier circuit is configured to compare a signal at the input terminal of the sense amplifier circuit with a reference voltage to determine a memory state of the memory cell (see col. 7, ll. 40-63).
Regarding claim 9, Mantegazza discloses wherein the magnetic memory element is configured to switch between a first resistance state and a second resistance state (see col. 2, ll. 22-49).
Regarding claim 10, Mantegazza discloses wherein the magnetic memory element conducts the read current (see col. 1, ll. 64-67 and col. 2, ll. 1-4);
the first voltage comprises a voltage drop across the magnetic memory element in a first resistance state (see col. 4, ll. 46-67 and col. 5, ll. 1-15), and
the second voltage comprises a voltage drop across the magnetic memory element in a second resistance state (see col. 4, ll. 46-67 and col. 5, ll. 1-15).
Regarding claim 11, Mantegazza discloses wherein the selector element comprises an ovonic threshold switch (see col. 10, ll. 23-40).
Regarding claim 12, Mantegazza discloses a cross-point memory array comprising the memory cell (see col. 1, ll. 6-8).
Regarding independent claim 13, Mantegazza discloses an apparatus (Fig. 4) comprising:
a memory cell (Fig. 4: 402) comprising a magnetic memory element (see col. 14, ll. 1-23) coupled in series with an ovonic threshold switch (see col. 10, ll. 23-40), the memory cell comprising a first terminal coupled to a word line (Fig. 4: LWL), and a second coupled to a bit line (Fig. 4: LBL); and
a voltage regulator circuit (Fig. 415, 408, 405 and 431) comprising an output terminal coupled to the bit line, and an input terminal coupled to a second power supply voltage (Fig. 4: 415/431 comprises output terminals electrically coupled to LBL, VNN Supply and VPP Supply), the voltage regulator circuit configured to provide a lower limit on a voltage of the bit line (see col. 9, ll. 37-62),
wherein voltage regulator circuit amplifies a voltage that is based on a voltage across the memory cell (see col. 7, ll. 40-63).
Regarding claim 14, Mantegazza discloses wherein the voltage regulator circuit comprises a source follower transistor (Fig. 4: 408).
Regarding claim 15, Mantegazza discloses wherein the voltage regulator comprises a common gate amplifier (Fig. 4: 415/432).
Regarding claim 16, Mantegazza discloses wherein the voltage regulator circuit comprises a p-channel transistor configured to operate in a saturation region of operation (Fig. 4: 442).
Regarding claim 17, Mantegazza discloses a sense amplifier circuit comprising an input terminal coupled to a third terminal of the voltage regulator circuit (Fig. 4: 432).
Regarding claim 18, Mantegazza discloses wherein the sense amplifier circuit is configured to compare a signal at the input terminal of the sense amplifier circuit with a reference voltage to determine a memory state of the memory cell (see col. 7, ll. 40-63).
Regarding claim 19, Mantegazza discloses wherein the magnetic memory element is configured to switch between a first resistance state and a second resistance state (see col. 2, ll. 22-49).
Regarding independent claim 20, Mantegazza discloses a method comprising:
providing a memory cell (Fig. 4: 402) comprising a magnetic memory element (see col. 14, ll. 1-23) coupled in series with an ovonic threshold switch (see col. 10, ll. 23-40), the memory cell comprising a first terminal coupled to a word line (Fig. 4: LWL), and a second terminal coupled to a bit line (Fig. 4: LBL);
coupling the word line to a first power supply voltage (Fig. 4: LWL_SEL);
coupling a source terminal of a p-channel transistor to the bit line (Fig. 4: 442 electrically coupled to LBL);
coupling a gate terminal of the p-channel transistor to a second power supply voltage (Fig. 4: Bypass control);
coupling a drain terminal of the p-channel transistor to a current mirror transistor (Fig. 4: 442 electrically coupled to 405, 411 and 413) and an input terminal of a sense amplifier (Fig. 4: 442 coupled to 432); and
operating the p-channel transistor as a common gate amplifier to amplify a voltage at the input terminal of a sense amplifier (Fig. 4: 432), which voltage is based on a voltage across the memory cell (see col. 7, ll. 40-63).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825